MoBL-USB™ FX2LP18
`Technical Reference Manual
`Document # 001-11981 Rev. *B
`
`Cypress Semiconductor
`198 Champion Court
`San Jose, CA 95134-1709
`Phone (USA): 800.858.1810
`Phone (Intnl): 408.943.2600
`http://www.cypress.com
`
`Exhibit 2033 - Page 01 of 346
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`Copyrights
`
`Copyrights
`Copyright © 2002–2011 Cypress Semiconductor Corporation. All rights reserved.
`Cypress, the Cypress Logo, MoBL-USB, Making USB Universal, Xcelerator, and ReNumeration are trademarks or registered
`trademarks of Cypress Semiconductor Corporation. Macintosh is a registered trademark of Apple Computer, Inc. Windows is
`a registered trademark of Microsoft Corporation. I²C is a registered trademark of Philips Electronics. SmartMedia is a trade-
`mark of Toshiba Corporation. All other product or company names used in this manual may be trademarks, registered trade-
`marks, or servicemarks of their respective owners.
`
`Disclaimer
`The information in this document is subject to change without notice and should not be construed as a commitment by
`Cypress Semiconductor Corporation Incorporated. While reasonable precautions have been taken, Cypress Semiconductor
`Corporation assumes no responsibility for any errors that may appear in this document.
`No part of this document may be copied or reproduced in any form or by any means without the prior written consent of
`Cypress Semiconductor Corporation.
`Cypress Semiconductor products are not designed, intended, or authorized for use as components in systems intended for
`surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the
`failure of the Cypress Semiconductor product could create a situation where personal injury or death may occur. Should
`Buyer purchase or use Cypress Semiconductor products for any such unintended or unauthorized application, Buyer shall
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`against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
`personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Cypress Semi-
`conductor was negligent regarding the design or manufacture of the product.
`The acceptance of this document will be construed as an acceptance of the foregoing conditions.
`The MoBL-USB™ FX2LP18 Technical Reference Manual, Version 1.0 provides information for the CY7C68053.
`
`2
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`MoBL-USB™ TRM, Document # 001-11981 Rev. *B
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`Contents Overview
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`1.
`
`Introducing MoBL-USB™ FX2LP18
`
`2. Endpoint Zero
`
`3. Enumeration and ReNumeration™
`
`4.
`
`Interrupts
`
`5. Memory
`
`6. Power Management
`
`7. Resets
`
`8. Access to Endpoint Buffers
`
`9. Slave FIFOs
`
`10. General Programmable Interface
`
`11. CPU Introduction
`
`12. Instruction Set
`
`13. Input/Output
`
`14. Timers/Counters and Serial Interface
`
`15. Registers
`
`Appendix A. Descriptors for Full-Speed Mode
`
`Appendix B. Descriptors for High-Speed Mode
`
`Appendix C. Device Register Summary
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`MoBL-USB™ TRM, Document # 001-11981 Rev. *B
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`Contents Overview
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`4
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`MoBL-USB™ TRM, Document # 001-11981 Rev. *B
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`Contents
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`1.
`
`1.7
`1.8
`
`15
`Introducing MoBL-USB™ FX2LP18
`1.1
`Introduction.....................................................................................................................................15
`1.2
`An Introduction to USB ...................................................................................................................15
`1.3
`The USB Specification....................................................................................................................16
`1.4
`Host Is Master ................................................................................................................................16
`1.5
`USB Direction .................................................................................................................................16
`1.6
`Tokens and PIDs............................................................................................................................17
`1.6.1
`Receiving Data from the Host........................................................................................18
`1.6.2
`Sending Data to the Host...............................................................................................18
`USB Frames...................................................................................................................................18
`USB Transfer Types .......................................................................................................................18
`1.8.1
`Bulk Transfers................................................................................................................18
`1.8.2
`Interrupt Transfers .........................................................................................................19
`1.8.3
`Isochronous Transfers ...................................................................................................19
`1.8.4
` Control Transfers ..........................................................................................................19
`Enumeration ...................................................................................................................................20
`1.9.1
`Full-Speed / High-Speed Detection ...............................................................................20
`The Serial Interface Engine............................................................................................................20
`1.10
`1.11 ReNumeration™.............................................................................................................................21
`1.12 MoBL-USB FX2LP18 Architecture .................................................................................................21
`1.13 MoBL-USB FX2LP18 Features Summary ......................................................................................22
`1.14 MoBL-USB FX2LP18 Integrated Microprocessor...........................................................................23
`1.15 MoBL-USB FX2LP18 Block Diagram .............................................................................................24
`1.16 Package..........................................................................................................................................25
`1.16.1
` 56-Pin Package ............................................................................................................25
`1.16.2
`Signals Available ...........................................................................................................25
`1.17 Package Diagram ...........................................................................................................................27
`1.18 MoBL-USB FX2LP18 Endpoint Buffers ..........................................................................................28
`1.19 External FIFO Interface ..................................................................................................................29
`1.20
` MoBL-USB FX2LP18 Part Number ...............................................................................................31
`1.21 Document History ...........................................................................................................................32
`
`1.9
`
`33
`2. Endpoint Zero
`2.1
`Introduction.....................................................................................................................................33
`2.2
`Control Endpoint EP0 .....................................................................................................................33
`2.3
`USB Requests................................................................................................................................36
`2.3.1
`Get Status......................................................................................................................37
`2.3.2
`Set Feature....................................................................................................................39
`2.3.3
`Clear Feature.................................................................................................................41
`2.3.4
`Get Descriptor................................................................................................................41
`2.3.4.1 Get Descriptor-Device....................................................................................43
`2.3.4.2 Get Descriptor-Device Qualifier .....................................................................44
`2.3.4.3 Get Descriptor-Configuration .........................................................................44
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`2.3.4.4 Get Descriptor-String .....................................................................................44
`2.3.4.5 Get Descriptor-Other Speed Configuration ...................................................45
`Set Descriptor................................................................................................................45
`2.3.5.1 Set Configuration ..........................................................................................47
`Get Configuration ..........................................................................................................47
`Set Interface ..................................................................................................................47
`Get Interface..................................................................................................................48
`Set Address...................................................................................................................48
`Sync Frame ...................................................................................................................49
`Firmware Load ..............................................................................................................49
`
`2.3.5
`
`2.3.6
`2.3.7
`2.3.8
`2.3.9
`2.3.10
`2.3.11
`
`51
`3. Enumeration and ReNumeration™
`3.1
`Introduction ....................................................................................................................................51
`3.2
`MoBL-USB FX2LP18 Startup.........................................................................................................51
`3.3
`The Default USB Device ................................................................................................................52
`3.4
`‘C2’ EEPROM Boot-load Data Format ...........................................................................................53
`3.5
`EEPROM Configuration Byte .........................................................................................................54
`3.6
`The RENUM Bit..............................................................................................................................55
`3.7
`MoBL-USB FX2LP18 Response to Device Requests (RENUM=0) ...............................................55
`3.8
`MoBL-USB FX2LP18 Vendor Request for Firmware Load ............................................................56
`3.9
`How the Firmware ReNumerates...................................................................................................57
`3.10 Multiple ReNumerations™ .............................................................................................................57
`
`4.
`
`4.3
`
`4.4
`
`59
`Interrupts
`4.1
`Introduction ....................................................................................................................................59
`4.2
`SFRs ..............................................................................................................................................59
`4.2.1
`803x/805x Compatibility ................................................................................................62
`Interrupt Processing .......................................................................................................................62
`4.3.1
`Interrupt Masking...........................................................................................................62
`4.3.1.1
`Interrupt Priorities...........................................................................................63
`Interrupt Sampling .........................................................................................................63
`4.3.2
`Interrupt Latency ...........................................................................................................64
`4.3.3
`USB-Specific Interrupts..................................................................................................................64
`4.4.1
`Resume Interrupt...........................................................................................................64
`4.4.2
`USB Interrupts...............................................................................................................64
`4.4.2.1 SUTOK, SUDAV Interrupts............................................................................68
`4.4.2.2 SOF Interrupt .................................................................................................68
`4.4.2.3 Suspend Interrupt ..........................................................................................68
`4.4.2.4 USB RESET Interrupt ....................................................................................68
`4.4.2.5 HISPEED Interrupt.........................................................................................68
`4.4.2.6 EP0ACK Interrupt ..........................................................................................68
`4.4.2.7 Endpoint Interrupts ........................................................................................69
`4.4.2.8
`In-Bulk-NAK (IBN) Interrupt ...........................................................................69
`4.4.2.9 EPxPING Interrupt .........................................................................................69
`4.4.2.10 ERRLIMIT Interrupt........................................................................................69
`4.4.2.11 EPxISOERR Interrupt ....................................................................................69
`USB-Interrupt Autovectors .............................................................................................................69
`4.5.1
`USB Autovector Coding ................................................................................................71
`I2C™ Bus Interrupt ........................................................................................................................72
`FIFO/GPIF Interrupt (INT4) ............................................................................................................73
`FIFO/GPIF-Interrupt Autovectors ...................................................................................................74
`4.8.1
`FIFO/GPIF Autovector Coding ......................................................................................75
`
`4.5
`
`4.6
`4.7
`4.8
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`6
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`Contents
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`77
`5. Memory
`5.1
`Introduction.....................................................................................................................................77
`5.2
`Internal Data RAM ..........................................................................................................................77
`5.2.1
`The Lower 128...............................................................................................................78
`5.2.2
`The Upper 128...............................................................................................................78
`5.2.3
`SFR (Special Function Register) Space ........................................................................78
`External Program Memory and External Data Memory..................................................................78
`MoBL-USB FX2LP18 Memory Map................................................................................................79
`On Chip Data Memory at 0xE000 – 0xFFFF..................................................................................81
`
`5.3
`5.4
`5.5
`
`83
`6. Power Management
`6.1
`Introduction.....................................................................................................................................83
`6.2
`USB Suspend.................................................................................................................................85
`6.2.1
`SUSPEND Register.......................................................................................................85
`6.3 Wakeup/Resume............................................................................................................................86
`6.3.1
`Wakeup Interrupt ...........................................................................................................87
`USB Resume (Remote Wakeup) ...................................................................................................88
`6.4.1
`WU2 Pin.........................................................................................................................88
`
`6.4
`
`7. Resets
`7.1
`7.2
`7.3
`
`7.4
`7.5
`7.6
`7.7
`
`89
`Introduction.....................................................................................................................................89
`Hard Reset .....................................................................................................................................89
`Releasing the CPU Reset...............................................................................................................90
`7.3.1
`RAM Download..............................................................................................................90
`7.3.2
`EEPROM Load ..............................................................................................................90
`CPU Reset Effects..........................................................................................................................91
`USB Bus Reset...............................................................................................................................91
`MoBL-USB FX2LP18 Disconnect...................................................................................................91
`Reset Summary .............................................................................................................................92
`
`93
`8. Access to Endpoint Buffers
`8.1
`Introduction.....................................................................................................................................93
`8.2
`MoBL-USB FX2LP18 Large and Small Endpoints .........................................................................93
`8.3
`High-Speed and Full-Speed Differences........................................................................................93
`8.4
`How the CPU Configures the Endpoints ........................................................................................94
`8.5
`CPU Access to MoBL-USB FX2LP18 Endpoint Data.....................................................................95
`8.6
`CPU Control of MoBL-USB FX2LP18 Endpoints ...........................................................................96
`8.6.1
`Registers That Control EP0, EP1IN, and EP1OUT .......................................................96
`8.6.1.1 EP0CS ...........................................................................................................96
`8.6.1.2 EP0BCH and EP0BCL ...................................................................................97
`8.6.1.3 USBIE and USBIRQ.......................................................................................97
`8.6.1.4 EP01STAT .....................................................................................................98
`8.6.1.5 EP1OUTCS....................................................................................................98
`8.6.1.6 EP1OUTBC....................................................................................................98
`8.6.1.7 EP1INCS........................................................................................................98
`8.6.1.8 EP1INBC........................................................................................................99
`Registers That Control EP2, EP4, EP6, EP8.................................................................99
`8.6.2.1 EP2468STAT .................................................................................................99
`8.6.2.2 EP2ISOINPKTS, EP4ISOINPKTS, EP6ISOINPKTS, EP8ISOINPKTS .......100
`8.6.2.3 EP2CS, EP4CS, EP6CS, EP8CS ................................................................100
`8.6.2.4 EP2BCH:L, EP4BCH:L, EP6BCH:L, EP8BCH:L..........................................101
`
`8.6.2
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`8.6.3
`
`Registers That Control All Endpoints ..........................................................................102
`8.6.3.1
`IBNIE, IBNIRQ, NAKIE, NAKIRQ.................................................................102
`8.6.3.2 EPIE, EPIRQ ...............................................................................................103
`8.6.3.3 USBERRIE, USBERRIRQ, ERRCNTLIM, CLRERRCNT............................103
`8.6.3.4
`TOGCTL ......................................................................................................104
`The Setup Data Pointer................................................................................................................104
`8.7.1
`Transfer Length ...........................................................................................................105
`8.7.2
`Accessible Memory Spaces ........................................................................................105
`Autopointers .................................................................................................................................105
`
`8.7
`
`8.8
`
`107
`9. Slave FIFOs
`9.1
`Introduction ..................................................................................................................................107
`9.2
`Hardware......................................................................................................................................107
`9.2.1
`Slave FIFO Pins ..........................................................................................................108
`9.2.2
`FIFO Data Bus (FD) ....................................................................................................109
`9.2.3
`Interface Clock (IFCLK)............................................................................................... 110
`9.2.4
`FIFO Flag Pins (FLAGA, FLAGB, FLAGC, FLAGD) ................................................... 111
`9.2.5
`Control Pins (SLOE, SLRD, SLWR, PKTEND, FIFOADR[1:0])................................... 112
`9.2.6
`Slave FIFO Chip Select............................................................................................... 114
`9.2.7
`Implementing Synchronous Slave FIFO Writes........................................................... 114
`9.2.8
`Implementing Synchronous Slave FIFO Reads .......................................................... 117
`9.2.9
`Implementing Asynchronous Slave FIFO Writes......................................................... 119
`9.2.10
`Implementing Asynchronous Slave FIFO Reads ........................................................121
`Firmware ......................................................................................................................................122
`9.3.1
`Firmware FIFO Access................................................................................................122
`9.3.2
`EPx Memories .............................................................................................................123
`9.3.3
`Slave FIFO Programmable-Level Flag........................................................................124
`9.3.4
`Auto-In / Auto-Out Modes............................................................................................124
`9.3.5
`CPU Access to OUT Packets, AUTOOUT = 1 ............................................................126
`9.3.6
`CPU Access to OUT Packets, AUTOOUT = 0 ............................................................126
`9.3.7
`CPU Access to IN Packets, AUTOIN = 1 ....................................................................129
`9.3.8
`Access to IN Packets, AUTOIN=0...............................................................................131
`9.3.9
`Auto-In / Auto-Out Initialization....................................................................................132
`9.3.10
`Auto-Mode Example: Synchronous FIFO IN Data Transfers ......................................133
`9.3.11
`Auto-Mode Example: Asynchronous FIFO IN Data Transfers.....................................134
` Switching Between Manual-Out and Auto-Out............................................................................134
`
`9.4
`
`9.3
`
`135
`10. General Programmable Interface
`10.1
`Introduction ..................................................................................................................................135
`10.1.1
`Typical GPIF Interface.................................................................................................137
`10.2 Hardware......................................................................................................................................138
`10.2.1
`The External GPIF Interface........................................................................................138
`10.2.2
`Default GPIF Pins Configuration .................................................................................139
`10.2.3
`Six Control OUT Signals .............................................................................................139
`10.2.3.1 Control Output Modes..................................................................................139
`Six Ready IN signals ...................................................................................................139
`10.2.4
`Nine GPIF Address OUT Signals ................................................................................139
`10.2.5
`Three GSTATE OUT Signals.......................................................................................139
`10.2.6
`8/16-Bit Data Path, WORDWIDE = 1 (default) and WORDWIDE = 0 .........................139
`10.2.7
`Byte Order for 16-bit GPIF Transactions .....................................................................140
`10.2.8
`Interface Clock (IFCLK)...............................................................................................140
`10.2.9
`10.2.10 Connecting GPIF Signal Pins to Hardware .................................................................141
`10.2.11
`Example GPIF Hardware Interconnect........................................................................141
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`10.3.3
`10.3.4
`
`10.4
`
`10.3 Programming the GPIF Waveforms .............................................................................................142
`10.3.1
`The GPIF Registers.....................................................................................................142
`10.3.2
`Programming GPIF Waveforms...................................................................................143
`10.3.2.1 The GPIF IDLE State ...................................................................................143
`10.3.2.2 Defining States.............................................................................................144
`Re-Executing a Task Within a DP State.......................................................................147
`State Instructions .........................................................................................................150
`10.3.4.1 Structure of the Waveform Descriptors ........................................................153
`10.3.4.2 Terminating a GPIF Transfer .......................................................................154
`Firmware ......................................................................................................................................155
`10.4.1
`Single-Read Transactions ...........................................................................................161
`10.4.2
`Single-Write Transactions............................................................................................166
`10.4.3
`FIFO-Read and FIFO-Write (Burst) Transactions........................................................170
`10.4.3.1 Transaction Counter.....................................................................................170
`10.4.3.2 Reading the Transaction-Count Status in a DP State..................................170
`GPIF Flag Selection.....................................................................................................170
`GPIF Flag Stop ............................................................................................................170
`10.4.5.1 Performing a FIFO-Read Transaction..........................................................171
`Firmware Access to IN Packets, (AUTOIN=1).............................................................176
`Firmware Access to IN Packets, (AUTOIN = 0)...........................................................177
`10.4.7.1 Performing a FIFO-Write Transaction ..........................................................179
`Firmware Access to OUT Packets, (AUTOOUT=1).....................................................184
`10.4.8
`Firmware access to OUT packets, (AUTOOUT = 0)....................................................185
`10.4.9
`10.5 UDMA Interface ............................................................................................................................187
`10.6 ECC Generation ...........................................................................................................................187
`
`10.4.4
`10.4.5
`
`10.4.6
`10.4.7
`
`189
`11. CPU Introduction
`11.1
`Introduction...................................................................................................................................189
`11.2
`8051 Enhancements.....................................................................................................................190
`11.3 Performance Overview .................................................................................................................190
`11.4 Software Compatibility..................................................................................................................191
`11.5
`803x/805x Feature Comparison ...................................................................................................191
`11.6 MoBL-USB FX2LP18/DS80C320 Differences..............................................................................192
`11.6.1
`Serial Ports ..................................................................................................................192
`11.6.2
`Timer 2.........................................................................................................................192
`11.6.3
`Timed Access Protection .............................................................................................192
`11.6.4
`Watchdog Timer...........................................................................................................192
`11.6.5
`Power Fail Detection....................................................................................................192
`11.6.6
`Port IO .........................................................................................................................192
`11.6.7
`Interrupts......................................................................................................................192
`11.7 MoBL-USB FX2LP18 Register Interface ......................................................................................193
`11.8 MoBL-USB FX2LP18 Internal RAM..............................................................................................193
`11.9
`IO Ports ........................................................................................................................................193
`11.10 Interrupts ......................................