Reprint
`
`from
`
`IEEE Micro
`
`Volume 15, Number 4
`
`August 1995
`
`2D SiliconIFerroelectric Liquid Crystal Spatial Light Modulators
`
`Timothy J. Drabik, Albert H. Titus, Mark A. Handschy,
`David Banas, Stephen D. Gaalema, David J. Ward
`
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`

`

`

`

`2D Silicon/Ferroelectric Liquid Crystal
`Spatial Light Modulators
`
`We have developed a spatial light modulator technology based on foundry silicon fabrication
`processes. This technology employs a thin, ferroelectric liquid crystal light-modulating layer
`at the substrate's surface, producing electrically addressed display devices with resolutions
`up to 256x256 and frame rates up to 10 kHz. We have also fabricated optically addressed
`smart-pixel arrays for low-level image processing. Performance has advanced rapidly due
`to design innovations and effective use of modern process features.
`
`J. Drabik
`Timothy
`
`. Titus
`Albert H
`
`Georgia Institute of
`Technology
`
`MarkA. Handschy
`
`David Banas
`
`Displaytech, Inc.
`
`Stephen D. Gaalema
`
`David J. Ward
`
`Black Forest Engineering
`
`patial light modulator (SLM) tech-
`nologies have received fresh interest
`with the widening of applications for
`optical signal processing and the ris-
`ing demand for small-format displays. Wide
`recognition of the versatility of silicon as an elec-
`tronic material and the wealth of ltnowledge
`available on it has motivated researchers to
`devise SLM technqlogies that combine silicon
`with various light-modulating materials and
`devices.'
`Investment in time and nloney for silicon fab-
`rication is enormous, malting cornrnodity silicon
`a bargain that is hard to beat. Using standard
`processes is so inexpensive colnpared to the
`alternative that it is worth adapting a design
`approach to the nature of this resource. Our chal-
`lenge is to accorn~nodate those characteristics of
`foundiy VLSI that are at odds with the require-
`nlents of good SLMs.
`We use standard or nearly standard cornmod-
`ity CMOS fabrication setvices provided by silicon
`foundries to produce chips that realize all but the
`light-modulating function of electrically or opti-
`cally addressed SLMs. Post-processing steps can
`then incorporate a light-modulating layer onto
`the chips to turn them into colnplete SLMs.
`The properties of the light-modulating mater-
`ial incorporated with the VLSI determine the use-
`
`fulness and practicability of the resulting SLM
`technology. Ferroelectric liquid crystals (FLCs)
`with switching speeds at or below 100 ps oper-
`ate 100 times faster than the twisted-nematic
`materials used in early liquid crystal light valves.
`Further, their mechanical properties are conve-
`nient. Being isotropic liquids at convenient tem-
`peratures (around 100°C), FLCs are compatible
`with straightfo~ward procedures for creating and
`filling thin cells.
`
`Ferroelectric liquid crystals and SLMs
`Figure 1 (next page) shows how we incorpo-
`rate a light-mod~~lating layer on the surface of a
`
`chip. Cells are specified at chip design time by
`laying out cuts in the passivation glass above
`metal pads. The pads serve both as mirrors and
`switching electrodes. A window carrying a trans-
`parent conductive layer, l usually indium-tin oxide
`(ITO), and a rubbed polymer ~nolecular align-
`ment layer, is contacted directly to the chip sur-
`face. The window forms the top bounding
`surface of the cells and provides a colninon ref-
`erence electrode. Attaching the window and fill-
`ing the chips with FLC material are the only steps
`performed to turn them into SLMs.
`The thinness of the cells (1 to 2 pm) causes
`the FLC ~nolecules to align in the surface-stabi-
`
`lized config~ration.~ In this mode, the FLC layer
`
`0272-1732/95/$04.00 O 1995 IEEE
`
`August 1995 67
`
`

`

`Ontical nrocessina
`
`Silicon
`
`dioxide ,
`
`, Transparent
`- Rubbed polymer
`/ conductor
`
`alignment layer
`
`A Metal-:! pad
`Silicon substrate
`
`Figure 1. Typical siliconIFLC light modulator cell cross sec-
`tion.
`
`Word 0
`
`Word 1
`
`Bit 0 KO Bit 1
`
`-
`Bit 1
`
`Figure 2. Pixel array circuitry o f SRAM-based 64x64 SLM
`
`behaves optically as a uniaxially anisotropic slab with its
`slow axis in the plane of the bounding surfaces. When the
`electric field reverses, the slow axis rotates through 45
`degrees. Suitable c o ~ ~ f i g i ~ s a t i o ~ ~ of the input polarization
`
`yields a 90 degree n~oclulation of polarization rotation, which
`gives rise to amplitude modulation between crossecl polar-
`izers. Electric fields of 2.5V/ym effect switching of the newer
`materials in 50 to 100 ps. Such fields are easily generated on
`a CMOS VLSI chip, and the circuit loading of a 50-ymx50-ym
`
`68
`
`IEEE Micro
`
`Figure 3. Photographs of a few cells o f the 64x64 SRAM
`SLM (a), and most of the array (b), with an image dis-
`played.
`
`FLC cell is comparable to that of a few minimum-geollletry
`logic gate inputs. This match in clrive req~~irenlents makes
`silicon and FLCs a natural technology combination.
`
`Three generations of electrically addressed
`SLMs
`We have constructed electrically addressed SLMs by aug-
`nlenting conventional static or dynamic random-access mem-
`ory ( S W I or DRAM) designs with FLC light modulators. Our
`devices associate one modulator with each RAM cell; the
`I>inary-valued cell state drives the modulator. Interfacing to
`these devices is straigl~tforwasd because, electrically, they
`resemble standard RAM parts. The designs we describe next
`appearecl at approximately equal intervals over a five-year
`pesiod. Their clescriptions sl~oulcl convey a sense of the evo-
`lutionary pace of this SLM technology, how its progress has
`been tied to advances in silicon technology, and future
`improvements to anticipate.
`64x64 SRAM-based SLM with 60-ym cell pitch. Our first
`device was fabricated in a 3-~n1, double-metal process, based
`on SRAM cells of the for111 shown in Figure 2. The cross-cou-
`pled static inverters, coupled by nMOS pass transistors to a
`pair of Bit lines, constitute a standard, six-transistor, static
`design. An additional inverter buffers the stored state and
`drives a second-metal pad that colnpletely covers the cell.
`This switching electrode is driven to OV or 5V. With the com-
`nlon window electrode held at 2.5V, the two possible cell
`states result from generating equal but opposite electric fields
`across the FLC. We chose an 8-bit-wide data input for easy
`interfacing to a PC provided with a plug-in interface card.
`Thus, each row of the 64x64 array fills in eight write cycles.
`Choosing a static cell design eli~ninatecl the need for com-
`plex clsive circuitl.y wit11 critical tinling specifications, and
`tlli~s easecl the verification ancl clemonstration of this first
`clevice. Also, the aclclitional buffer in each cell assures that the
`electrical state of the menlory cell is isolated from that of the
`
`

`

`Word 0
`
`d
`
`LL
`
`1 T
`
`Metal
`pad
`
`1 T
`
`-.+
`
`d
`. L I ' ~
`- cL
`
`1 T
`
`1 5
`
`Word 1
`
`d
`
`Bit 0
`
`d "+
`
`d
`
`.L
`
`1 T
`
`Word line
`Pass transistor V
`
`Bit line
`
`(a)
`
`FLC cell voltage
`
`Slope = ,
`
`1
`
`Total charge Q
`
`Qmax
`
`Figure 5. DRAM-style SLM pixel design: equivalent circuit
`(a) and voltage-charge characteristics (b).
`
`the Bit line, charge dynalnics within the cell become impor-
`tant, as does lnaxirnizing the time the cells connect with their
`Bit lines. To accomplish the latter, we incorporated a 256-
`bit-wide pipeline register into the data path. To write a row,
`32-bit words are read sequentially into eight registers. These
`word registers then dump in parallel into the full-row
`pipeline register. The register's contents are gated onto the
`Bit lines, while the word registers are loaded with the next
`row's data. Thus, each cell is driven by its Bit line during the
`active phase of a Word line cycle that lasts practically 1/256th
`of the frame time. At televisio~l frame rates, the resultillg 65-
`ps Word cycle is comlnensurate with the FLC switching time.
`However, framing at 4 kHz reduces this time to less than 1
`ps. How does this affect the writing process?
`Charge dynamics of the FLC now come into play.
`Physically, we can model the modulator cell as a suspension
`of electric dipoles in a viscous dielectric fluid, bounded by
`parallel-plate electrodes. Figure 5a shows the pass transistor
`represents the combination of an explic-
`as a switch, and C,,,
`it MOS capacitor with other parasitic circuit capacitances. We
`represent the FLC cell as the parallel combination of linear
`
`August 1995 69
`
`Bit 1
`
`...
`
`Figure 4. Pixel array circuitry of DRAM-based 256x256
`SLMs. Each cell comprises a single-pass transistor con-
`trolled by a Word line, which gates the cell's internal
`capacitance onto a Bit line.
`
`FLC. This means that a group of eight cells can be selected,
`written, and deselected in just nanoseconds, and writing a
`new group can begin while the first group is still switching.
`In fact, the entire array can be written in mucl~ less than the
`approximately 100-ps FLC cell switching time.
`Photographs of a few cells and of the whole array with a
`displayed image appear in Figure 3. Cells are on a 60-pm
`pitch. The texture visible within the bright cells results from
`thicltness variations in the FLC film. Variations occur because
`of the undulating topography of the circuitly beneath the
`second-metal layer. The fabrication process' 5-pin second-
`metal spacing rule and the provision for individual passiva-
`tion cuts for each cell deterlnined the 67-percent area fill
`factor. We measured intensity contrast ratios of 12:l using
`633-nm HeNe laser light. The SLM operated at a 4.5-kHz
`frame rate witllout attenuation of the peak-to-peak optical
`r e ~ p o n s e . ~
`256x256 DRAM-based SLM with 20-pm cell pitch. The
`static cell design has advantages, such as easily met drive
`requirements and drive pipelining, but requires too inucl~
`area for use in high-resolution displays. We implemetlted
`our next design in a 2-pm process and also moved to a
`dynamic cell configuration, shown in Figure 4.
`Since all the FLC switching charge must now come through
`
`

`

`Optical processing
`
`is 1/C, and they intercept the charge axis at +P. The solid line
`shows state evolutio~l for very slow rnoclulatio~l of Vbetween
`
`- v,:,,;,, ancl v,,,,;,,.
`Dashed lines represent fast SLM operation.
`When Vchanges slowly over a time that is large compared
`to z, the plot traverses the solid path sl~own. When I QI < P,
`an aclclitional charge increment causes clipoles to flip ancl
`cloes no1 substantially affect voltage. When I QI exceecls P,
`clipoles are all alignecl with the api~liecl fielcl, ancl a charge
`increnle~lt is storecl on the linear capacitance C, with a con-
`conlitant change in voltage. Charging the circuit slowly to
`1/; ,,;,, (or - y ,,:, ,,;,,) leaves it in the state labeled S+ (or S-).
`Now suppose the cell is in state S-, is charged rapidly to
`v,,;,,,
`and then isolated fro111 its Bit line. There is no time dur-
`ing charging for dipoles to flip, so the cell behaves like a lin-
`ear capacitor ancl follows the "fast-charge" path to F', in
`which state a total charge of Q,,
`is stored. Isolated from its Bit
`line, the cell now seeks equilibri~inl as its dipoles begin to
`flip. Since charge is conserveci, the cell's state follows the ver-
`tical equilibration path to state F+,<,, and the cell voltage drops
`by 2P/C. However, as long as QC2,, > P, the cell equilibrates to
`a fiilly switcl~ecl state. A certain ~nargill is desirable to com-
`pensate for charge lealtages that occur between refreshes. A
`reasonable figure of nlerit for the electrical cell design is
`
`which s l ~ o ~ ~ l c l be ~nade greater than unity. For a given FLC
`
`nlaterial and chosen operating wavelength, C,,/P
`is con-
`stant. y,,:,, is typically limited to half the supply voltage, so
`the key to a robust, fast DRAM SLM design is providing ade-
`quate "ballast" capacitance in the cell.
`The Generation-2 SLM e~nploys an explicit MOS capacitor
`that occupies the 16 percent of the pixel area available for it,
`and contributes about 50 fF to the cell capacitance. This is suf-
`ficient to switch FLC nlaterials with polarizations up to at least
`30 nC/cm2. We also i~nproved fill factor over the Generation-
`1 device to 72 percent, despite a reduction in pixel pitch.
`Exploiting the tighter metal-2 design rule and eliminating indi-
`vidual passivation openings above the lnodulator pads in favor
`of a common, large cut accomplishes this.
`A sophisticated interface drives the SLM. Part of it resides
`on a PC-compatible plug-in card, and the renlainder fits with-
`in the inounting fixture for the device. FLC materials, like all
`liquid ciystals, are susceptible to degradation from sustained
`DC electric fields. Although refinelllent of these nlaterials to
`extreme purity levels has increased their tolerance of the
`mechanis~ns involvecl, it is still ilnportant to render the aver-
`age voltage applied to each cell as close to zero as possible.
`The clriver circuitry cloes this auto~natically by alternately clis-
`playing assertecl ancl invertecl versions of each input image.
`Slrobing the i~lciclent illumination to coincicle with only the
`assertecl phase of each image prevents the clisplayecl image
`from washing out. This strategy halves the usable frame rate
`
`Figure 6. Photographs of images displayed on 256x256
`Generation-2 SLMs: entire array (a) and a few cells (b).
`Similar images from a Generation-3 SLM: entire array (c)
`and a few cells (d).
`
`capacitance C,,, with a field-controllecl dipole distribution
`having spontaneous polarization P.
`Spontaneous ferroelectric polarization p, of these materi-
`als is between 30 ancl40 nC/cm2. Under DC bias, all dipoles
`align with the electric field. When the field reverses, the
`dipoles follow, hindered by viscosity. To reverse all dipoles
`in a cell of area A, a charge of
`
`mnust pass between the electrocles, \vherc Pclenotes the cell's
`total spontaneous polarization charge. 'I'his charge move-
`ment takes place over the FLC switching rime z, ;~ppsoxi-
`lnately equal to 100 ps.
`Figure 5b is a plot of cell voltage Vversus the total c11;uge
`Q stored in the pixel circuit under the simplifying assump-
`tion that C = C,,,+ C,,, is linear. The slope of the asymptotes
`
`70
`
`IEEE Micro
`
`

`

`but does not reduce optical throughput.
`Full-aperture and close-up pllotographs of an image writ-
`ten to the Generation-2 SLM appear in Figures 6a and 6b. The
`p ~ e l s appear mn~~cll more uniform than those of the SRAM
`device, and contrast improved to 29:l at a 4-ltHz frame rate.4
`Table 1 summarizes the Generation-2 SLM's electrical and
`optical cllaracteristics, and introduces two important perfor-
`mance criteria: optical throughput and illumination tolerance.
`Optical throughput is the efficiency with which the SLM
`transforms incident light into a usable output image. Area
`fill factor of the modulator electrodes is important because
`incident light falling between these reflectors is lost and
`counts against throughput. However, for information-pro-
`cessing applications, other factors play a role. The pixelated
`nature of the SLM means that filndarnentally, it displays a
`sampled version of a desired image. Sampling an image man-
`ifests in the frequency domain as a replication o f the origi-
`nal image's spectrum. Pl~ysically, these replicas propagate
`in different directions away from the device, and it is prac-
`tical to use only one of them-usually
`the zero-order (on-
`axis) copy-in a coherent image-processing system.
`The optical structure o f individual pixels is important
`because, according to sampling tlleoly, the Fourier transforln
`of the light from a single "on" pixel constitutes a multiplica-
`tive envelope for the entire spectrum. An optically smooth
`pixel gives rise to an envelope concentrated at the origin and
`enhances the energy in the zeroth diffracted order. A highly
`textured pixel diffuses reflected-light energy into higher
`orders at the expense of the zeroth order. Thus the smoot11-
`ness of the pixel mirror is as important as its area fill factor.
`The second performance issue, illurnination tolerance,
`relates both to area fill and to the previously discussed cell
`figure of merit QoJP. The source/drain implant regions of the
`cell's pass transistor form parasitic p-n junctions with the sub-
`strate. Even when the transistor is o f f , the inboard junction
`connects across the storage capacitor and FLC cell. This junc-
`tion acts as a photodiode, and light illulninating the substrate
`causes cells to discharge. The more completely we cover the
`substrate with metal, the less light-sensitive the device
`becomes. For a given effective light responsivity of the par-
`asitic photodiode, the time constant o f discharge is propor-
`tional to illumination intensity and inversely proportional to
`the total cell capacitance. The illumination tolerance report-
`ed in Table 1 is the incident light intensity that makes a bright
`cell fade to half its initial output (over a period of four mini-
`mum refresh times) after isolation o f the cell from its Bit line.4
`The Generation-2 SLM demonstrated good speed perfor-
`mance and reasonable contrast. Howevel; it possessed poor
`optical througl~put and only marginal tolerance to bright illu-
`mination. As we see later, increases in area fill factor, cell
`smootlmess, and cell capacitance alleviate these sho~tcomings,
`256x256 DRAM-based SLM with 30-pm cell pitch. The
`Generation-3 design shows how effective use o f silicon
`
`Table 'l. Characteristics of 256x256 DRAM SLMs.
`
`Type
`
`Characteristic
`
`Generation
`2
`3
`
`7.68
`1.2
`30
`1.6
`90
`32
`80
`100
`25.6
`105
`10
`1OO:l
`
`10
`
`c 1
`
`Optical
`
`5.12
`Geometric Aperture (mm2)
`Design rule (pm)
`2
`2 0
`Pixel pitch (pm)
`Mirror gaps (pm)
`3
`Mirror area f i l l factor (percent) 72
`Electrical Data-bus width (bits)
`3 2
`Nominal data clock (MHz)
`2 0
`Row address time (ns)
`460
`Frame update time (ps)
`118
`Optical rise/fall time (ps)
`225
`Frame rate ( k H z )
`4
`Image contrast ratio
`2911
`Throughput into zero order
`(percent)
`Illumination tolerance
`(mW/cm2)
`
`20 >10,000
`
`process refinements can lead to large performance gains. We
`did not change the circuit design in this device qualitative-
`ly, but reengineered it to support a total information through-
`put of 2.6 Gbps4 Two significant changes were moving to a
`1.2-pm CMOS fabrication process and increasing pixel pitch
`to 30 pm. Full-aperture and close-up photographs o f an
`image written to the Generation-3 SLM appear in Figures 6c
`and 6d. Reengineering dramatically improved contrast and
`pixel homogeneity. Table 1 summarizes Generation-3 SLM
`cllaracteristics and reveals additional improvements; we
`account for these as follows.
`In the finer-line process, we could rnalte the cell pass tran-
`sistor smaller. Straightfolward scaling together with the larg-
`er pixel pitch left 62 percent of the pixel area for the MOS
`capacitor, up from 16 percent. The reduction o f gate oxide
`tl~ickness in the 1.2-pin process also increased the specific
`MOS capacitance by a factor o f 1.8, to 1.5 fF/pmZ. The com-
`bined effect o f these changes was to increase cell capaci-
`tance to nearly 1 pF. This change, together with an increase
`in fill factor to 90 percent, contributed to the realization o f a
`500-fold improvement in illu~nination tolerance,
`The doubling o f frame rate derives partly from using a
`faster FLC material and partly from a reduction in cell thiclt-
`ness to less than 1 pm. The latter resulted from improved
`fabrication techniques.
`Throughput into the zeroth diffracted order also ilnproved
`dramatically (to 10 percent), thanks to three factors. First, the
`metal-2 fill factor is higher. Second, the topographically uni-
`form MOS capacitor stlzlcture occupies a larger fraction of the
`
`August 1995 71
`
`

`

`Optical processing
`
`process. Contrast, improved to 100:1, also benefited from the
`flatter nlirrors of the Generation-3 design.
`The Generation-3 SLM characteristics cross the threshold
`into practical usefi~lness. I-Iowever, the technology is young,
`
`and performance will progress much f ~ ~ r t l ~ e r before exhaust-
`ing the potential of SLM fabrication refinenlents ancl mocl-
`ern VLSI processes.
`
`Optical-in, optical-out smart focal plane
`devices
`Edge detection and enhancement have long been impor-
`tant aspects of image preprocessing for pattern recognition
`and computer vision. Mahowald and Mead introduced a bio-
`logically inspired family of 2D, analog, VLSI focal plane struc-
`tures that mimic aspects of the biological retina. They also
`exhibit edge detection, notion enhancement, and dynamic
`range co~npression.~ These devices ernploy parasitic bipolar
`devices as photodetectors to provide direct image input and
`convey their output image in serial electrical form.
`As optical pattern recognition systems based on 2D cor-
`relation become nlore prevalent, delnand rises for image pre-
`processing and low-level feature-extraction techniques that
`retain their outputs in optical form. We believe that smart,
`optically addressed SLMs in silicon VLSI/FLC technology are
`well matched to these tasks. We have therefore researched
`real-time edge- ancl motion-enhancing focal planes with opti-
`cal inrage outputs.
`Mahowald-style, edge-enhancing focal planes. Figure
`7a reproduces the functional structure of the Mahowald reti-
`na in slightly augnlented form. A hexagonal resistive net
`interconnects a 2D array of analog circuit cells. In each cell,
`a photoreceptor circuit exploiting the exponential sub-
`threshold current-voltage characteristic of diode-connected
`MOSFETs, generates an activation voltage. This voltage varies
`logarithmically with incident light intensity and drives a
`transconcluctance amplifier that tugs the net in the direction
`of its input. The net tends to diffuse away large spatial gra-
`dients to produce a smoothed version of the logaritl~mical-
`ly cornpressed input scene. Capacitive loading causes
`temporal, as well as spatial, filtering. A difference amplifier
`that subtracts the snloothed signal from the incident signal
`generates each Mahowald cell's output. We have added the
`simple functionality of a cornparator with prograrnrnable
`threshold driving an FLC modulator pad.
`Figure 713 shows how the retina responds to a stationary
`bright band of illumination spanning ~n~lltiple cells. The dif-
`ference between the incident and stnoothed activation profile
`is a bipolar, analog signal with peaks near contrast edges. The
`space constant of the device, eviclent in the decay profile of the
`pealts, clepencls on the ratio of the lateral concluctance of the
`net lo the amplifi er transconcluctance. lJlacing the conlparator
`tl~resholcl within the excursion range of the analog output gen-
`erates a bina~y signal. In Figure 7b, the cllosen tl~reshold leads
`
`Transconductance Differential Comparator
`
`voltage
`
`Bright band
`
`Moving bright band
`
`Difference
`
`(b)
`
`, , Binarized
`
`(4
`
`Larger
`
`I , / response
`
`Wider
`
`Figure 7. Mahowald-Mead silicon retina concept aug-
`mented with thresholding and optical output functions:
`focal plane circuit (a), response t o a stationary bright
`band of illumination (b), and response t o a moving band
`of illumination (c).
`
`cell. Finally, the finer fabrication process is inherently more
`planar. VLSI process developers nlust tl~emselves improve pla-
`narity as lateral geometries clecrease, Electrical perfornlance
`demands force metal and clieleclric thicltnesses to remain near-
`ly constant. To avoid problems with the cleposition of suc-
`cessive layers, process developers introduce explicit steps that
`smooth the wafer topograplly. Fabricating a given layout in the
`1.2-pm process yields a smoother device than in the 2-pm
`
`72
`
`IEEE Micro
`
`

`

`to "on" pixels on the bright side of contrast eclges. Shalper con-
`trast steps generate wider bancls of "on" pixels.
`Figure 7c shows the rctina's response to a moving bright
`band. The srnoothecl activation lags thc inciclcnt signal
`because encrgy is stored on the net. 'I'he ratio of net capac-
`itance to lateral co~lductance determines thc tinlc constant of
`this spatio-ten~poral filtering. Moving the illumination band
`cnhances thc analog output at the leacling eclge, and in turn
`produces a wider binary signal upon thresholcling.
`Thus the Mahowald retina detects cdgcs and cnhances
`motion. In a typical circuit realization, time and space con-
`stants arc voltage tunable, which etlliances the concept's
`flexibilily. The thrcsholding ancl light moclulation filnctions
`we have added turn the retina into a "magic mirror" that
`rcflccts only tllc intcrcsting parts of an incident image.
`A continuous-time retina design. Wc impleine~ltecl a
`design of a 20x22 retina array in a 0.8-pn, triple-mctal, CMOS
`process brol~erecl througll the MOS Implementation System.
`To acldress the challenge of preventing process parameter
`variations from corrupting intencled circuit operation, we test-
`. -
`
`ed a photoreceptor circ~~il itltenclecl to reduce systelnatic input
`noise arising from global tl~sesl~olcl variations. We used a clual-
`rail (clifferential) signal reprcscntation in conjunction with dif-
`fere~ltial difference ainplifiers for the gain clcmcnts. 'l'hey fit
`naturally with the detectors' differential outputs and provicl-
`ed for easy programming of the comparator threshold.
`The horizontal resistors of the hexagonal net arc I'Kl's
`
`Figure 8. Phbtograph of a portion of the continuous-time
`retina cell array before FLC layer incorporation showing
`high fill factor and good flatness. The square notch cut
`from each rectangular modulating electrode exposes the
`phototransistor active region.
`
`cm2. Figure 8 shows the surface topography of a fcw cclls or
`thc fabricatecl chip before liiglt modulator assembly. We usccl
`the metal-3 layer exclusively for the reflective switching elec-
`trodes. Thc mctal-3 gap rulc is only 1.2 ptn, IILIC the provi-
`sion of separate glass cuts abovc i~~cliviclual pacls wicle~lecl the
`dead space between pixels. Thc planarity of this process is
`so good that no hint of unclerlying circuit topography is vis-
`ible in a pllotograph of the rop laycr.
`having both a signal
`Array layo~rts such as these-thosc
`beam ailcl reaclout (pump) light inciclent upon then-put
`three nletal layers to good use. We inust avoid lcaltage of
`the P L I I I I ~ light onto the pl~otocletectors, which woulcl wash
`out the input image. In our clcsign, i~ltercligitatecl metal-2
`power and ground buscs occluclc no st of the area in the
`gapsbetween the metal-3 inoclulator pacls. This greatly
`recluces capacitive coupling between thc pads ancl the ~under-
`lying circuitry. The resultitlg near-total occlusion of'thc sub-
`
`Figure 9. Photos of continuous-time retina output for a
`static dark bar (a) and dark bar moving t o the left (b)
`showing motion enhancement.
`
`strate between rows or phototransistors lets us fornlat ~ L I I I I ~
`light into continuous parallel stripes. Imaging a Iiotlchi rul-
`ing nlask (a transparency carrying opaque parallel stripes)
`onto the clevice accomplishes this easily.
`Futldainen(ally, our retina is a 3terminal device because an
`input dakt itllage controls the tlisposition of power fro111 ;t sep-
`beam into an output beam. Figure 9
`arate supply ( ~ L I I I I ~ )
`shows two o~rtput frames of the device under excitation by a
`stationary ancl moving clark band on a Ijright I~ackgrouncl. In
`
`August 1995 73
`
`

`

`Optical processing
`
`Figure 921, a clark, vertical I~ar is slationay in the centcr of the
`input image. Two vertical lines of dark pixels appear at the
`bar's edges. In Figure 9b, the bar is rnoving to the left: tlie
`right bane1 of clark pixels widens, and the left b;u11cl alnlost dis-
`appears. This verfles edge detection ancl motion enhance-
`ment. Nonunifornlities ancl spuriotlsly switchecl pixels evident
`in the images are manifestations of process notlunilhrmity ancl
`boundary effects at the edge of the resistive net.
`
`Speed, power, concurrency, and scaling
`We can appreciate the ~echnology match between silicon
`CMOS ancl I'I,Cs 11y loolti~~g at the energetics of SLM operation.
`Lilte f ~ ~ l l y complemenk~ry silico~l CMOS circuitry, FLC modu-
`lator cells consume power only during switching transients.
`This lneans that total clissipatecl power varics linearly with tlic
`SLM I'~1rne rate. Frame rate is bouncled by tlie lieat retnoval
`capability of the S1.M pacltaging; we express tliis conelition as
`
`where J'is tlic fmme rate in 1 Jz, q,. is switching energy per
`unit area, II,,~,,,,. is dissipated switching power per unit arca,
`;und p,,,?g is tl~e pcltaging-lilnited power dissipation per unil
`area. The energy required to switch a representative 1:I.C cell
`operating in thc visible spectrum is e,,, = 5 f'J/~rn2.
`
`Correspondingly, a m i n i l l ~ u ~ ~ ~ - g e o l ~ ~ e t ~ y transistor in a mod-
`ern VLSl process might have a gate capacil;~nce of al~out 8
`fF. Charging or clischarging it tllrough 5V requires an ener-
`gy &,.= 0.1 pJ. '1'0 relate this energy to area, we Llse the tran-
`sistor density of our retina arrays: 48 devices per
`72-~tmx62.4-pm cell, or 1 I:JCT per 100 pmL, 'l'l~us, the area-
`spccific switching energy of FE'I's in our arrays is about
`
`Acltnowledging our use of Palgel--than-mitlirnum-geome-
`tiy transistors and conccding some static power clissipation
`
`to analog circuitry, we can infer [hat epE;;,,- inight realistically
`hc a few times larger. In other words, the power dissipated
`by a 1'I.C ligl~t-moclulating layer is about the sanx as that of
`
`thc CMOS c i r ~ ~ ~ i l r y beneath it.
`Tlierc cam bc 110 IIettcr circumstance! Neitlier the FLC nor
`tlie silicon burdens the other wit11 poorer speccl-power per-
`Pormatlcc. We can now nlalte a thclrubnail calculation of max-
`~IIILIIII f r a ~ ~ i e rate for a dissipation of 100 mW/cmz (or I
`nW/pn12), whicl~ is a comPortable rcginle for a clevice with-
`out explicit lieat sinking:
`
`In tliis scenario, we lose some (but not much) performance
`potential to the switching speecl limitations of current FT,C
`materials.
`
`Esticnates of the equivalent number of explicit computing
`operations performeel by such clevices as silicon retinas
`always give startlingly large numl~ers. Such high equivalent
`tllroughputs are partly due Lo the efficiency of purpose-
`clesignetl harclware. Purpose-clesignecl harclware exhibits
`high processing concurrency: a high fraction of lransistors
`change slate every cycle and tllereby perfor111 usefiul com-
`putation. A highly concurrent systeln can generale high corn-
`putational througl~put at nlodest cloclc rates.
`The previous analysis hypothesized transistors ancl light
`moclulators switching at the sanle rate. Pelformance scaling
`POI. such devices is trivial I~ecause they expcnd a fixed power
`per unit area at a given moch~lator switching ratc, regal-dless
`of array sizc.
`A clualitalive cliffcrencc exists in tlie scaling of devices
`whose transislol-s switcli more frequently th;un tllcir n~odu-
`lators, when the ratio clcpends on array size. Our eleclrical-
`ly addressed SLMs arc perfect examples: the Hit lines of an
`MNdevicc must cycle Ntilnes d ~ ~ r i n g onc frame tinlc (pixel-
`switclling time). 'l'his tencls to recluce tlic dissipation-limited
`fhme rate because the circuitry becomes ever inore powcr-
`hung~y than tlie light modulators. lkundschy et al." examines
`li~nits for the case of large, electrically addressed SLMs and
`conclude