Trials@uspto.gov
`571-272-7822
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`
`
`
`Paper 7
`Entered: January 21, 2015
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`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`ATOPTECH, INC.,
`Petitioner,
`
`v.
`
`SYNOPSYS, INC.,
`Patent Owner.
`____________
`
`Case IPR2014-01145
`Patent 6,237,127 B1
`____________
`
`Before TRENTON A. WARD, PETER P. CHEN, and
`FRANCES L. IPPOLITO, Administrative Patent Judges.
`
`IPPOLITO, Administrative Patent Judge.
`
`
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`
`
`571-272-7822
`
`
`
`
`Paper 7
`Entered: January 21, 2015
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`ATOPTECH, INC.,
`Petitioner,
`
`v.
`
`SYNOPSYS, INC.,
`Patent Owner.
`____________
`
`Case IPR2014-01145
`Patent 6,237,127 B1
`____________
`
`Before TRENTON A. WARD, PETER P. CHEN, and
`FRANCES L. IPPOLITO, Administrative Patent Judges.
`
`IPPOLITO, Administrative Patent Judge.
`
`
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`
`
`
`IPR2014-01145
`Patent 6,237,127 B1
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`
`I. INTRODUCTION
`Petitioner ATopTech, Inc. filed a Petition on July 11, 2014,
`requesting an inter partes review of claims 1–13 of U.S. Patent No.
`6,237,127 B1 (Ex. 1001, “the ’127 patent”). Paper 1 (“Pet.”). Patent Owner
`Synopsys, Inc. timely filed a Preliminary Response to the Petition. Paper 6
`(“Prelim. Resp.”).
`We have jurisdiction under 35 U.S.C. § 314, which provides that an
`inter partes review may be authorized only if “the information presented in
`the petition . . . and any [preliminary] response . . . shows that there is a
`reasonable likelihood that the petitioner would prevail with respect to at least
`one of the claims challenged in the petition.” 35 U.S.C. § 314(a).
`Pursuant to 35 U.S.C. § 314, we conclude there is a reasonable
`likelihood that Petitioner would prevail with respect to claims 1–4 and 7–11
`of the ’127 patent. We deny the Petition as to claims 5, 6, 12, and 13.
`A. Related Proceedings
`The ’127 patent is involved in a district court proceeding in the U.S.
`District Court of the Northern District of California captioned Synopsys, Inc.
`v. ATopTech, Inc., Case No. 3:13-cv-02965-MMC (N.D. Cal. 2013). Pet. 1.
`Additionally, Petitioner has filed Petitions challenging the patentability of
`certain claims of Patent Owner’s US Patent Nos. 6,567,967 (IPR2014-01150
`and IPR2014-01159), 6,507,941 (IPR2014-01153), and 6,405,348
`(IPR2014-01160).
`
`
`B. The ’127 Patent
`The ’127 patent relates generally to the static timing analysis of digital
`electronic circuits, and in particular applies static timing analysis to
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`synthesis of circuits by analyzing certain paths of a circuit using “non-
`default timing constraints known as ‘exceptions.’” Ex. 1001, Title, 1:8–11.
`Exceptions allow a circuit designer, working with a circuit synthesis system,
`to specify certain paths through the circuit to be synthesized as being subject
`to non-default timing constraints. Id., Abstract. The ’127 patent discloses
`that static timing analysis had been used to verify that the design of a digital
`electronic circuit would perform correctly at the target clock speeds, and
`“[f]or similar reasons, it would be useful to apply, as efficiently as possible,
`static timing analysis to the synthesis process.” Id. at 1:40–42. Specifically,
`the ’127 patent discloses performing static timing analysis on units of a
`circuit, referred to as “sections,” which comprise a set of “launch” flip flops,
`non-cyclic combinational circuitry, and a set of “capture” flip flops. Id. at
`2:1–4.
`The static timing analysis described in the ’127 patent is accomplished
`in two main phases: (1) propagation of tagged rise-fall (RF) timing tables
`and (2) relative constraint analysis. Ex. 1001, 8:37–41. In the first phase of
`the timing analysis, delays between inputs and outputs of circuit devices are
`represented by “timing arcs.” Ex. 1001, 8:44–45. Using the timing arcs for
`the circuit devices, maximum and minimum delay values for the rise time
`and the fall time are determined and stored in RF timing tables. Id. at 9:54–
`67. The timing tables are propagated through the circuit and the delays at
`each circuit node are added to the minimum and maximum values of the
`timing table from the previous node. Id. at 9:58–13:2, Fig. 5. Additionally,
`each timing table is associated with a “tag” that may include clock identifier
`and a variety of “labels.” Ex. 1001, 3:11–15, 10:21–25. The labels of a
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`“tag” also may identify points in the circuit referenced by an exception.
`Ex. 1001, 3:29–32.
`After the propagation of the timing tables through the circuit, the
`second phase of the timing analysis, relative constraint analysis, is
`performed. Ex. 1001, 13:3–4. Relative constraint analysis involves the
`comparison of the delay values included in the timing tables with the timing
`constraints of the circuit. Id. at 13:66–14:27. The ’127 patent describes
`maximum allowable path delays (MAPDs) and shortest allowable path
`delays (SAPDs), which are default timing constraints alterable by
`exceptions. Id. at 13:34–63, 14:30–38. The delay values stored in the
`timing tables are compared to the MAPD and SAPD values, and if the
`MAPD and SAPD timing constraints are satisfied, the circuit has passed the
`static timing analysis. Id. at 13:56–14:26.
`Additionally, with respect to exceptions, the ’127 patent instructs
`“[e]xceptions are specified by the circuit designer as individual syntactic
`units called ‘exception statements’ which are comprised of a ‘timing
`alteration’ and a ‘path specification.’” Ex. 1001, 1:58–61. The timing
`alteration instructs the timing analyzer how to alter the default timing
`constraints for paths through the circuit to be analyzed which satisfy the path
`specification. Id. at 1:61–63. For example, a “set_false_path” exception
`indicates that for paths satisfying the path specification, the relevant MAPD
`value is set to infinity and the relevant SAPD value is set to zero for the
`relative constraint analysis. Id. at 14:47–54.
`C. Illustrative Claim
`Of the challenged claims, claim 1 is independent. Claim 1 reproduced
`below is illustrative of the subject matter of the ’127 patent:
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`1. A method performed in a circuit analysis process, comprising
`the steps performed by a data processing system of:
`marking certain points in a circuit description according
`to their being referenced by at least a first exception;
`propagating a plurality of timing tables through the
`circuit description; and
`wherein at least a first timing table, of the plurality of
`timing tables, refers to a tag comprising at least a first label
`indicating a marked point in the circuit description, through
`which the table has been propagated.
`D. The Asserted Grounds
`Petitioner asserts that the challenged claims are unpatentable over the
`following grounds:
`
`Reference(s)
`
`Basis
`
`Claims Challenged
`
`Belkhale1
`Belkhale
`Belkhale and Tom2
`
`§ 102
`§ 103
`§ 103
`
`1–11 and 13
`1–13
`1–13
`
`
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`II. ANALYSIS
`
`A. Claim Construction
`In an inter partes review, claim terms in an unexpired patent are given
`their broadest reasonable construction in light of the specification of the
`patent in which they appear. See 37 C.F.R. § 42.100(b); see also Office
`Patent Trial Practice Guide, 77 Fed. Reg. 48,756, 48,766 (Aug. 14, 2012).
`Under the broadest reasonable construction standard, claim terms are given
`
`1 Krishna Belkhale, Timing Analysis with Known False Sub Graphs, in
`IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN,
`DIGEST OF TECHNICAL PAPERS 736–740 (Nov. 5–9, 1995) (Ex. 1005,
`“Belkhale”).
`2 U.S. Patent No. 5,210,700, issued May 11, 1993 (Ex. 1006, “Tom”).
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`their ordinary and customary meaning, as would be understood by one of
`ordinary skill in the art in the context of the entire disclosure. See In re
`Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007). Any special
`definition for a claim term must be set forth with reasonable clarity,
`deliberateness, and precision. In re Paulsen, 30 F.3d 1475, 1480 (Fed. Cir.
`1994).
`1. “exception” (claim 1)
`
`Petitioner asserts one of ordinary skill in the art would understand that
`an “exception” is a “non-default timing constraint,” and “marking” is not
`limited to physical marking but refers to “defining the points within the
`circuit description that are referenced by the recited first exception.” Pet.
`19–20. Patent Owner does not propose a construction.
`With respect to the term “exception,” the Specification expressly
`states that “the present invention relates to analyzing certain paths of a
`circuit under non-default timing constraints known as exceptions.”
`Ex. 1001, 1:8–11 (emphasis added); see id. at Title, Abstract. The
`Specification adds “[e]xceptions are specified by the circuit designer as
`individual syntactic units called ‘exception statements’ which are comprised
`of a ‘timing alteration’ and a ‘path specification.’” Ex. 1001, 1:58–61. The
`timing alteration instructs the timing analyzer as to how to alter the default
`timing constraints for paths through the circuit to be analyzed which satisfy
`the path specification. Id. at 1:61–63. The Specification further states,
`“[t]he path specification consists of one or more ‘path specifiers,’ with each
`path specifier taking an ‘argument.’ In order for a path specification to be
`satisfied, each argument of each of its path specifiers must be satisfied.” Id.
`at 1:64–67.
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`Based on the current record, we construe the term “exception” as
`“non-default timing constraints.”
`2. timing table (claim 1)
`Petitioner submits that the term “timing table” is not limited to the
`four values3 disclosed as an “RF timing table” in the ’127 patent but refers to
`the propagation of any delay value. Pet. 23–24. Patent Owner asserts that
`the plain and ordinary meaning of table “must include a set of data, i.e.,
`more than a single data item.” Prelim. Resp. 7–8. Patent Owner relies on
`dictionary definitions shown in Exhibits 2001 and 2002 to support its
`proposal. Prelim. Resp. 7–8.
`For purposes of this decision, we agree with Petitioner the term
`“timing table” does not require multiple delay values. Although the
`Specification discloses an exemplary “RF timing table” as having four RF
`values (Ex. 1001, 9:54–57), the claim language is broader and not restricted
`to a specific type of table or number of data items in the table. To require
`otherwise would improperly import a limitation from the Specification into
`the claim. See, e.g., SuperGuide Corp. v. DirecTV Enters, Inc., 358 F.3d
`870, 875 (Fed. Cir. 2004) (“Though understanding the claim language may
`be aided by the explanations contained in the written description, it is
`important not to import into a claim limitations that are not a part of the
`claim.”). Based on the current record, we determine the broadest reasonable
`interpretation of “timing table” is a “table having a timing value.”
`
`
`3 “The RF timing tables propagated are comprised of the following four
`values: minimum rise time (minRT), maximum rise time (maxRT),
`minimum fall time (minFT) and maximum fall time (maxFT).” Ex. 1001,
`3:8–11.
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`2. “satisfying an exception, prior to comparing the first timing value,
`with the first label” (claim 5)
`Petitioner asserts the phrase “with the first label” recited in claim 5 is
`a typographical error and submits that the claim language should read “with
`the first constraint value.” Pet. 31. Petitioner adds it would “not make sense
`to compare a timing value with a label like those in the ’127 patent because a
`label is never a timing constraint.” Id.
`We are not persuaded that claim 5 requires a timing value to be
`compared to a first label. As written, a comma separates the phrase “prior to
`comparing first timing value” from the phrase “with the first label.” Thus,
`rather than comparing the timing value with the first label, we read claim 5
`to recite “satisfying an exception . . . with the first label.” This interpretation
`is consistent with the Specification, which discloses checking a pin
`associated with a RF timing table for an exception flag. Ex. 1001, 18:31–35.
`If an exception flag exists, then a label, representing how the pin is referred
`in an exception statement, is considered for the purpose of adding it to the
`timing table tag. Id. at 18:44–46. “If the label being considered, by itself or
`in conjunction with any selection of labels already on the tag, satisfies, or
`can possibly satisfy, a path specification of at least one of the preprocessed
`exception statements, then the label is added to the tag.” Id. at 18:46–50
`(emphasis added). Accordingly, we are not persuaded by Petitioner that
`claim 5 includes a drafting error requiring the term “first label” to be
`substituted by “first constraint value.”
`B. Claims 1–11 and 13 – Anticipation by Belkhale (Ex. 1005)
`1. Summary of Belkhale (Ex. 1005)
`Belkhale, titled “Timing Analysis with known False Sub Graphs,”
`discloses that a static timing analysis, widely used at that time, determined
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`timing violations in circuits by computing the difference of slack (SLK)
`between an arrival time (AT) and required time (RAT) at each vertex in a
`timing graph. Ex. 1005, 6. Belkhale adds that while SLK gives a good local
`measure of the magnitude of a timing violation, the analysis does not take
`logic into account and results in the algorithm considering paths that may
`not be “logically realizable.” Id. Belkhale uses the term “false path” to refer
`to paths that are not logically realizable. Id. Belkhale teaches that false
`paths “must be detected and eliminated from consideration from the timing
`analysis.” Id. Additionally, Belkhale describes the use of false sub graphs
`as a way to eliminate multiple false paths from the timing analysis. Id.
`Specifically, “the ability to remove entire sub graphs from consideration
`from timing is a powerful feature.” Id.
`Belkhale further provides examples of false paths and false sub
`graphs. Figure 2 is reproduced below as an example of a false path.
`
`
`Figure 2 depicts two multiplexers MUX1 and MUX2 each having a first pin
`I1. Each multiplexer receives input from a control signal, which is inverted
`when input into MUX2. Belkhale teaches that all paths between pin I1 of
`MUX1 to pin I1 of MUX2 are false because a control signal allowing
`propagation of I1 at the first MUX1 will block propagation at the second pin
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`I1 at MUX2 due to the inverted control signal. Id. at 7, Fig. 2. Belkhale
`discloses these false paths can be represented by a false sub graph with an
`ordered pair specifying {(MUX1/ I1, MUX2/ I1)}. Id. at 7.
`Belkhale further describes false sub graphs as “in general, equivalent
`to many individual paths.” Ex. 1005, 9. Figure 1 is reproduced below.
`
`
`Figure 1 depicts false sub graphs, identified as F1 and F2, for timing
`graph G. Ex. 1005, Fig. 1. False graph F1 represents the false paths from v1
`to v7 and false graph F2 represents the false paths from v1 to v8 within
`timing graph G. Ex. 1005, Fig. 1.
`Additionally, Belkhale discloses “Algorithm 1,” which computes
`multiple arrival and required times at a node, and distinguishes the different
`times based on a set attribute. Ex. 1005, 7. The set attribute is a subset of
`the set of false sub graphs {1, . . . , k} where k is the number of input false
`sub graphs. For the example shown in Figure 1, k is 2 and the possible
`values of the set attribute are {}, {1}, {2}, and {1, 2}. Id. The set attribute
`value provides the set of false sub graphs that a signal has come through. Id.
`2. Analysis
`Petitioner challenges claims 1–11 and 13 under 35 U.S.C. § 102 based
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`on Belkhale. Pet. 18–39. Although this is a separate challenge from that
`presented for the same claims based on Belkhale under § 103, Petitioner
`blends the arguments for these grounds together in the same section of the
`Petition. Id. In several instances, this hybrid approach leaves us to
`speculate on the distinction line between the anticipation and obviousness
`arguments. Nonetheless, in our review, we discern Petitioner’s anticipation
`arguments rely on hypotheticals that modify Belkhale’s disclosure. As an
`example, for the “tag” recited in claim 1, Petitioner relies on a modification
`of the false sub graph notation from v1 to v7, to x1 to x2 to argue Belkhale’s
`disclosure of tags that are “logically identical to those used in the ’127
`patent.” Pet. 26 (citing Ex. 1007 ¶¶ 130–133). Similarly, for claim 2,
`Petitioner modifies the labeling of v1 to x1 and v7 to x2 to show Belkhale
`discloses the logically identical notation in Figure 12 of the ’127 Patent.
`Pet. 29–30 (Ex. 1007 ¶ 148). Petitioner’s modifications are based on
`underlying hypotheticals described in Dr. Soheil Ghiasi’s supporting
`declaration. See Ex. 1007 ¶¶ 132–133, 148.
`
`To establish anticipation, each and every element in a claim, arranged
`as is recited in the claim, must be found in a single prior art reference. Net
`MoneyIN, Inc. v. VeriSign, Inc., 545 F.3d 1359, 1369 (Fed. Cir. 2008);
`Karsten Mfg. Corp. v. Cleveland Golf Co., 242 F.3d 1376, 1383 (Fed. Cir.
`2001). The rule requiring that every element of the claim appear in a single
`reference is flexible to accommodate the situation when common knowledge
`is not recorded in the reference. Continental Can Co. USA v. Monsanto Co.,
`948 F.2d 1264, 1268 (Fed. Cir. 1991). Here, Dr. Ghiasi’s notation
`hypotheticals and accompanying modifications go beyond describing
`common knowledge “known to those in the field of the invention, albeit not
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`known to judges.” See Continental Can Co. USA, 948 F.2d at 1268. Dr.
`Ghiasi’s testimony does not simply provide the common knowledge of a
`skilled artisan reviewing Belkhale, but seeks to supplement that knowledge
`with modifications similar to the embodiment disclosed in the Specification
`of the ’127 patent. Thus, we determine these arguments are not persuasive
`for an anticipation challenge and, further, do not demonstrate a reasonable
`likelihood of Petitioner prevailing on this ground for claims 1–11 and 13.
`B. Claims 1–11 and 13 – Obviousness over Belkhale (Ex. 1005)
`We have considered the arguments and evidence presented, and are
`persuaded that there is a reasonable likelihood that Petitioner would prevail
`on its assertion that claims 1–4 and 7–11 would have been obvious in view
`of Belkhale. We are not persuaded of the same for claims 5, 6, and 13.
`1. Claims 1–4 and 7–11
`Petitioner contends that Belkhale teaches or suggests all the
`limitations of claims 1–4 and 7–11. Pet. 18–39. Below we discuss
`independent claim 1, which is fundamental to dependent claims 2–4 and 7–
`11.
`
`Claim 1 recites the step of “marking certain points in a circuit
`description according to their being referenced by at least a first exception.”
`To satisfy this limitation, Petitioner asserts that Belkhale teaches that a user
`can specify false sub graphs using an ordered pair of vertices. Pet. 20–21.
`Referring to the multiplexer example in Figure 2, Petitioner explains
`Belkhale shows marking by defining a false path with ordered pair
`{(MUX1/ I1, MUX2/ I1)}. Pet. 21 (citing Ex. 1005, 7). Petitioner asserts the
`’127 patent discloses false paths as an exception and, therefore, a person of
`ordinary skill would appreciate the false paths and false sub graphs disclosed
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`in Belkhale to be exceptions. Pet. 21 (citing Ex. 1001, 14:44–54; Ex. 1007
`¶¶ 103–106).
`Separate from the argument above, Petitioner also asserts that
`Belkhale’s Algorithm 1 satisfies the marking step recited in claim 1. Pet. 21.
`Specifically, Petitioner argues that Belkhale teaches an alternative
`embodiment for marking points within a circuit where the marking takes
`place within the timing analysis software. Id. Petitioner asserts Algorithm 1
`uses three data sets BG(v), EG(v), and IN(e) to reference points or edges in
`circuit modeled by graph G based on false sub graphs. Pet. 21–22 (citing
`Ex. 1005, 7; Ex. 1007 ¶¶ 110–111). Petitioner argues that the false sub
`graphs are exceptions. Id. at 21.
`For the purposes of this decision, we are persuaded by Petitioner’s
`arguments. First, we are persuaded that Belkhale’s false paths and false sub
`graphs teach or suggest an “exception.” As Petitioner observes, Belkhale
`describes false paths as paths that are not logically realizable and must be
`detected and eliminated from the timing analysis. Pet. 13 (citing Ex. 1005,
`6). Likewise, Belkhale explains that removing an entire false sub graph
`from timing consideration is advantageous because multiple paths may be
`simultaneously removed from consideration. See Pet. 13–14 (citing
`Ex. 1005, 6). Thus, we are persuaded by Petitioner’s argument that
`Belkhale’s false path and false sub graph are each a non-default timing
`constraint (i.e., an exception) because they represent circuit pathways that
`are not logically realizable and must be eliminated from the timing analysis.
`Id.
`
`Second, we also are persuaded Petitioner has explained sufficiently,
`for purposes of this decision, how Belkhale’s ordered pair vertices or
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`Algorithm 1 disclose “marking certain points in a circuit description
`according to their being referenced by” recited in claim 1, a false path or
`false sub graph. As Petitioner points out, Belkhale defines false paths in a
`multiplexer circuit with ordered pair vertices. Additionally, Petitioner
`separately asserts Belkhale’s use of “three separate data structures” BG(v),
`EG(v), and IN(e) to associate points in the circuit description with the false
`sub graph. Pet. 21–22; see Pet. 16–18 (explaining Algorithm 1 in
`operation). We understand Petitioner’s latter argument to be that Belkhale’s
`described “G” discloses a circuit description, the false sub graphs disclose
`exceptions, and the three data sets define vertices and edges according to a
`relationship to the false sub graphs.
`Claim 1 further recites “propagating a plurality of timing tables
`through the circuit description.” For this limitation, Petitioner asserts
`“Belkhale calculates multiple delay values – arrival times (AT) – at each
`point of the circuit and propagates those delay values through the circuit.”
`Pet. 22 (citing Ex. 1005, 7) (emphasis added). Petitioner further argues the
`propagated delay values are shown in timing tables in Belkhale’s Figure 3.
`Pet. 23. Figure 3 depicts vertices v1–v9 with delay value(s) and set
`attribute(s) for each vertex. Pet. 23 (showing annotated Figure 3).
`In response, Patent Owner asserts Belkhale does not disclose the
`propagating step because Belkhale discloses calculating a single delay value
`for each tag, and the single delay value is not a “timing table,” as claimed.
`Prelim. Resp. 11–13. Further, Patent Owner argues the “timing table”
`limitation should be construed as requiring more than a single data item, and
`under this proper construction, Belkhale’s calculation of the single delay
`value does not meet the “timing table” limitation of claim 1. Id. at 12.
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`We are not persuaded by Patent Owner’s arguments because these are
`based on Patent Owner’s proposed claim construction, which we have not
`adopted. As discussed above, for the purposes of this decision, our
`construction of “timing table” is a table having a timing value. Our
`construction does not require multiple values in a timing table. Thus, we are
`persuaded that Petitioner’s arguments sufficiently establish, for purposes of
`this decision, that Belkhale’s timing tables and delay values, shown in
`Figure 3, satisfy the propagating limitation recited in claim 1.
`Additionally, Petitioner also presents an alternative argument based
`on the testimony of its declarant, Dr. Ghiasi, who states “propagating timing
`tables with multiple values was well known to one skilled in the art at the
`time of the ’127 Patent . . . , and that [o]ne skilled in the art at the time . . .
`knew that minimum and maximum values and/or rise times and fall times
`could be propagated in the exact same manner as explained for the
`maximum value in Belkhale.” Ex. 1007 ¶ 124; see Pet. 24. Patent Owner
`contends Petitioner’s statements are conclusory. Prelim. Resp. 12–13. Here,
`we understand Petitioner to rely on Dr. Ghiasi’s testimony that a skilled
`artisan would have been aware of propagating timing tables with multiple
`values and that it would have been obvious to propagate multiple values in
`Belkhale based on that knowledge. Id. Based on the current record, we also
`determine Petitioner has explained sufficiently, for purposes of this decision,
`how Belkhale’s timing tables with multiple delay values, as suggested by Dr.
`Ghiasi, meet the propagating step recited in claim 1.
`Claim 1 further recites “wherein at least a first timing table, of the
`plurality of timing tables, refers to a tag comprising at least a first label
`indicating a marked point in the circuit description, through which the table
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`has been propagated.” Petitioner asserts that Figure 3 described in Belkhale
`discloses the plurality of timing tables with a “set attribute” tag. Pet. 25.
`Petitioner further asserts “Belkhale teaches that when the timing table passes
`through a false path, a ‘set attribute’ is appended to the timing table.” Id. at
`26 (citing Ex. 1005, 7). “The set attribute value gives the set of false sub
`graphs the signal has come through.” Id. (emphasis omitted). Essentially,
`Petitioner takes the position that the false sub graphs or false paths disclose
`“a marked point in the circuit description,” recited in claim 1, and the set
`attribute shown in Belkhale’s Figure 3 is a tag with a label indicating a
`signal arriving at a particular vertex has passed through a false sub graph.
`Id. Based on the current record, we are persuaded Petitioner sufficiently
`demonstrates how Belkhale teaches or suggests this limitation.
`In its Preliminary Response, Patent Owner generally argues the
`Petition includes no substantive arguments concerning how claim 1 is
`allegedly obvious over Belkhale.4 Prelim. Resp. 8. Patent Owner asserts
`Petitioner does not identify which limitations may not be disclosed in
`Belkhale, nor does Petitioner provide specific reasoning as to how any
`limitations not taught in Belkhale would have been obvious. Id. at 11.
`We are not persuaded by Patent Owner’s arguments. As discussed
`above for the propagating step recited in claim 1, Petitioner relies on Dr.
`Ghiasi’s testimony for the position a skilled artisan was aware of how to
`propagate multiple timing values and would have found it obvious to do
`with Belkhale based on that knowledge. Thus, upon consideration of the
`Petition, Preliminary Response, and evidence presented, we conclude that
`
`
`4 Patent Owner also applies this argument to claims 2–11 and 13, which
`depend from claim 1. Prelim. Resp. 8.
`16
`
`
`
`
`
`IPR2014-01145
`Patent 6,237,127 B1
`
`Petitioner has established a reasonable likelihood of prevailing on its
`assertion that claim 1 is obvious over Belkhale. Further, Petitioner provides
`detailed explanations of how each limitation of dependent claims 2–4 and 7–
`11 is taught by Belkhale. Pet. 29–31, 34–37. The Preliminary Response
`does not specifically address any of the limitations recited in dependent
`claims 2–4 or 7–11. We have reviewed Petitioner’s analysis and supporting
`evidence with respect to claims 2–4 and 7–11 and are persuaded that
`Petitioner has demonstrated that there is a reasonable likelihood that it would
`prevail with respect to claims 2–4 and 7–11 on this ground.
`2. Claims 5 and 6
`Claim 5 depends from claim 4 and recites “satisfying an exception,
`prior to comparing the first timing value, with the first label.” Petitioner
`argues the “the first label” is a typographical error that should be replaced
`with “the first constraint value,” which is recited in claim 4. Pet. 31–32.
`Then, Petitioner argues claim 5 is obvious over Belkhale under Petitioner’s
`proposed construction. Id. Nonetheless, as discussed above, we do not
`adopt Petitioner’s proposed construction and determine, instead, that a
`reasonable construction applies the “satisfying an exception” phrase to “with
`the first label” recited in claim 5. Petitioner has not provided arguments
`indicating how Belkhale discloses the recited limitations under this
`construction. Thus, Petitioner has not demonstrated a reasonable likelihood
`that it would prevail with respect claim 5 on this ground. Claim 6 depends
`from claim 5 and requires the same satisfying step recited in claim 5. Based
`on the same reasons discussed for claim 5, Petitioner also has not
`demonstrated a reasonable likelihood that it would prevail with respect claim
`6 on this ground.
`
`
`
`17
`
`
`
`IPR2014-01145
`Patent 6,237,127 B1
`
`
`3. Claim 13
`Claim 13 depends from claim 1 and, further, recites the steps of
`determining that a second argument of a second path
`specification of a second exception is satisfied with the first
`label; and
`
`substituting the second argument, indicative of a higher
`level boolean relationship among marked circuit points than the
`first label, for at least the first label comprising the tag.
`
`Petitioner asserts “[a]s the delay values propagate through the circuit,
`the labels associated with those delay values are constantly being adjusted
`by Algorithm 1 as a new sink element set s’ is calculated.” Pet. 37 (citing
`Ex. 1005, 7–8). As an example, Petitioner argues when a delay value
`passing through only false sub graph F1 is subsequently propagated through
`both false sub graphs F1 and F2, Algorithm 1 “causes the existing first label
`{1} to be substituted with a new argument {1, 2}. Id. at 38. Petitioner
`further asserts Algorithm 1 determines that a second path specification of a
`second exception is satisfied, as required by claim 13, because sub graph F2
`is a second path specification of a second exception. Id. (citing Ex. 1007
`¶ 192).
`We are not persuaded Petitioner has demonstrated a reasonable
`likelihood of prevailing on this ground for claim 13. Claim 13 requires a
`determination that a “second argument . . . is satisfied with the first label.”
`In Petitioner’s example, Petitioner proposes a first label {1} showing
`propagation through false sub graph F1 and a second argument {1, 2}
`representing propagation through false sub graphs F1 and F2. Petitioner
`does not explain how second argument {1, 2} is satisfied by first label {1},
`where {1} only shows propagation through one of the two false sub graphs
`
`
`
`18
`
`
`
`IPR2014-01145
`Patent 6,237,127 B1
`
`listed in {1, 2}. Similarly, Petitioner describes {1, 2} as a logical
`representation of an “AND” Boolean relationship, but does not explain how
`that AND relationship is satisfied by {1}. Pet. 38–39 (citing Ex. 1007
`¶ 194). Instead, Petitioner asserts that Algorithm 1 determines “that a
`second path specification of a second exception is satisfied” because sub
`graph F2 is a second path specification of a second exception. Id. at 38.
`However, claim 13 requires the “second argument,” not the “second path
`specification,” be satisfied. Moreover, the second argument must be
`satisfied with the first label.
`C. Claim 12 – Obviousness over Belkhale (Ex. 1005)
`
`Claim 12 depends from claim 1, and further recites
`determining that a second path specification of a second
`exception is satisfied with the first label; and
`
`substituting a first special symbol, indicative of a second
`timing alteration of the second exception, for at least the first
`label comprising the tag.
`
`Petitioner asserts that the ’127 patent discloses “a special
`implementation of timing table propagation” where current labels of a
`timing table tag may be replaced with a single FALSE_PATH label to
`specify that it is subject to a false path. Pet. 39 (citing Ex. 1001, 27:23–
`28:3). Petitioner further asserts that the ’127 patent discloses an alternative
`embodiment where “instead of adding the FALSE_PATH label, the timing
`table is . . . discarded.” Id. (citing Ex. 1001, 28:3–23). Petitioner argues that
`Belkhale teaches discarding timing tab
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