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` Paper 16
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` Entered: 22 February 2013
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`Trials@uspto.gov
`Tel: 571-272-7822
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`_______________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_______________
`
`SYNOPSYS, INC.
`Petitioner
`
`v.
`
`MENTOR GRAPHICS CORPORATION
`Patent Owner
`_______________
`
`Case IPR2012-00042
`Patent 6,240,376 B1
`_______________
`
`
`
`Before SALLY C. MEDLEY, HOWARD B. BLANKENSHIP, and
`JENNIFER S. BISK, Administrative Patent Judges.
`
`BISK, Administrative Patent Judge.
`
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`Synopsys, Inc. filed a petition to institute an inter partes review of U.S.
`
`Patent 6,240,376 B1 (Ex. 1001) (the “’376 patent”). 35 U.S.C. § 311. For the
`
`reasons that follow, the Board, acting on behalf of the Director, has determined to
`
`institute an inter partes review. 35 U.S.C. § 314.
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`Universal Electronics Exhibit 2002, Page 1
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`

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`Case IPR2012-00042
`Patent 6,240,376 B1
`
`
`I.
`
`INTRODUCTION
`
`A.
`
` Background
`
`OPINION
`
`Synopsis requests inter partes review of claims 1-15 and 20-33 of the
`
`’376 patent alleging that each of the claims is unpatentable under 35 U.S.C. §§102
`
`and/or 103 based on the following prior art references: Koch, et. al, “Breakpoints
`
`and Breakpoint Detection in Source Level Emulation,” ISSS Proceedings of the 9th
`
`Int’l Symposium on System Synthesis 26-31 (1996) (Ex. 1004) (“Koch”); Koch, et.
`
`al, “Debugging of Behavioral VHDL Specifications by Source Level Emulation,”
`
`Proceedings of the European Design Automation Conference 256-261 (Sept. 1995)
`
`(Ex. 1006) (“1995 Koch”); U.S. 6,132,109 (Ex. 1007) (“Gregory”); HDL-ICETM
`
`ASIC Emulation System, Quickturn Design Systems, Inc. (Ex. 1008) (“HDL-
`
`ICE”); and U.S. 5,960,191 (Ex. 1009) (“Sample”). The specific grounds are
`
`detailed below.
`
`Reference[s]
`
`Basis
`
`Claims challenged
`
`Koch
`
`§§ 102 and 103 1-5, 8-10, 20-24, 28, 32, and 33
`
`Koch and 1995 Koch
`
`§ 103
`
`11 and 25-27
`
`Gregory
`
`§§ 102 and 103 1-9, 11-14, 24, 25, and 28-33
`
`Gregory and 1995 Koch
`
`§ 103
`
`10, 15, 20-23, 26, and 27
`
`HDL-ICE
`
`§§ 102 and 103 1, 2, 5, 10, 11, and 28
`
`
`
`2
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`
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`Sample
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`§§ 102 and 103 1, 2, 5, 10, and 28
`
`Sample and 1995 Koch
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`§ 103
`
`11
`
`The ’376 patent has been and is currently involved in district court litigation.
`
` On March 13, 2006, Mentor Graphics filed a complaint against EVE-USA, Inc.
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`and Emulation and Verification Engineering, S.A. alleging infringement of the ’376
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`patent. Mentor Graphics Corp. v. EVE-USA, Inc., 06-cv-341-AA (D. Or.). Pet. 1.
`
`The case was dismissed with prejudice on November 30, 2006. Id. On September
`
`27, 2012, the day after the Petition in this case was filed, Petitioner filed a
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`complaint for declaratory judgment for invalidity of all claims of the ’376 patent in
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`the Northern District of California. Synopsys, Inc. v. Mentor Graphics Corp., 12-
`
`cv-05025-LB (N.D. Cal.). That case is ongoing. Ex. 2004.
`
`B.
`
` The ’376 patent
`
`The ’376 patent generally relates to the fields of simulation and prototyping
`
`of integrated circuits. ’376 patent col. 1, ll. 10-11. In particular, the patent
`
`describes “debugging synthesizable code at the register transfer level during gate-
`
`level simulation.” Id. col. 1, ll. 11-13.
`
`As described in the Background of the Invention, integrated circuit design
`
`begins with a description of the behavior desired in a high level description
`
`language (“HDL”) such as Very High Speed Integrated Circuit Description
`
`Language (“VHDL”). Id. col. 1, ll. 14-25. A subset of HDL source code is referred
`
`to as Register Transfer Level (“RTL”) source code. Id. col. 1, ll. 28-30. The RTL
`
`description of a circuit can be used by synthesis tools to generate a “gate-level
`
`
`
`3
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`netlist,” which in turn can be converted to a format suitable for programming a
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`hardware emulator. Id. col. 1, ll. 35-42.
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`Gate-level simulation is useful for validation of a circuit design. Id. col. 1, ll.
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`55-67. However, much of the high-level information is lost during synthesis,
`
`resulting in the unavailability of many traditional debugging tools, such as setting
`
`breakpoints and visually tracing source code execution. Id. col. 2, ll. 1-23. The
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`’376 patent describes a method of synthesizing RTL source code such that the
`
`resulting gate-level simulation can support these traditional debugging tools. Id.
`
`col. 2, ll. 26-30.
`
`Claim 1, reproduced below, illustrates the claimed subject matter:
`
`A method comprising the steps of:
`
`a) identifying at least one statement within a register transfer level (RTL)
`synthesizable source code; and
`
`b) synthesizing the source code into a gate-level netlist including at least
`one instrumentation signal, wherein the instrumentation signal is
`indicative of an execution status of the at least one statement.
`
`C.
`
`Claim Construction
`
`As a step in our analysis for determining whether to institute a trial, we
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`determine the meaning of the claims. Consistent with the statute and the legislative
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`history of the AIA, the Board will interpret claims using the broadest reasonable
`
`construction. See Office Patent Trial Practice Guide, 77 Fed. Reg. 48756, 48766
`
`(Aug. 14, 2012); 37 CFR § 100(b). There is a “heavy presumption” that a claim
`
`term carries its ordinary and customary meaning. CCS Fitness, Inc. v. Brunswick
`
`Corp., 288 F.3d 1359, 1366 (Fed. Cir. 2002). By “plain meaning” we refer to the
`
`
`
`4
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`ordinary and customary meaning the term would have to a person of ordinary skill
`
`in the art. Such terms have been held to require no construction. See, e.g., Biotec
`
`Biologische Naturverpackungen GmbH & Co. KG v. Biocorp, Inc., 249 F.3d 1341,
`
`1349 (Fed. Cir. 2001) (finding no error in non-construction of “melting”); Mentor
`
`H/S, Inc. v. Med. Device Alliance, Inc., 244 F.3d 1365, 1380 (Fed. Cir. 2001)
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`(finding no error in court’s refusal to construe “irrigating” and “frictional heat”).
`
`Petitioner submits that for purposes of this review, the claim terms take on
`
`the ordinary and customary meaning that the terms would have to one of ordinary
`
`skill in the art. Pet. 4. Petitioner does not address what this meaning would be for
`
`any specific claim term. In some cases, the ordinary meaning of claim language as
`
`understood by a person of skill in the art may be readily apparent even to lay
`
`judges, and claim construction in such cases involves little more than the
`
`application of the widely accepted meaning of commonly understood words.
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`Phillips v. AWH Corp., 415 F.3d 1303, 1314 (Fed. Cir. 2005) (en banc). In this
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`case, Petitioner does not argue that any term has a different meaning to a lay person
`
`than to a person of ordinary skill in the art. Except for the following terms,
`
`Petitioner’s proposal of plain and ordinary meaning, with no elaboration, does not
`
`appear unreasonable at this stage of the proceeding. Because this position is not
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`challenged by Patent Owner, we adopt it. However, resolving the issues set forth in
`
`the Petition requires a more detailed definition for at least the terms
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`“instrumentation signal,” “gate-level netlist,” “gate-level design,” and “sensitivity
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`list.”
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`5
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`
`1.
`
`Instrumentation Signal
`
`“Instrumentation signal” is not explicitly defined in the written description of
`
`the ’376 patent. However, the specification provides guidance as to its meaning. In
`
`the Summary of the Invention, the instrumentation signal is described as
`
`“indicat[ing] the execution status of the corresponding cross-referenced
`
`synthesizable statement” such that it “can be used to facilitate source code analysis,
`
`breakpoint debugging, and visual tracing of the source code execution path during
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`gate-level simulation.” ’376 patent, col. 2, ll. 50-55. Subsequently, the ’376 patent
`
`describes the process used in creating an instrumentation signal—instrumentation—
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`“the process of preserving high-level information through the synthesis process”
`
`that “provides an output signal indicative of whether the corresponding
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`synthesizable statement is active.” Id. at col. 5, ll. 3-4, ll. 23-25. This output
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`signal, the instrumentation signal, is created by adding additional logic to the gate-
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`level design that is the product of the synthesis. Id. at col. 5, ll. 26-30.
`
`In addition to the above description, the ’376 patent gives several examples
`
`of instrumentation signals. For example, Figure 9 illustrates the instrumentation of
`
`the Verilog (an HDL) source code shown in Figure 8 using the method shown in
`
`Figure 3. Figures 3, 8 and 9 are reproduced below:
`
`
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`6
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`
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`Figure 3, above, illustrates one embodiment of a method for instrumenting
`
`RTL source code. Id. at col. 3, ll. 21-22. The process creates a unique local
`
`variable for adjacent sequential statements in step 310, modifies those variables to
`
`zero in step 320, and inserts an assignment statement corresponding to an
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`executable branch of the source code in step 330. Id. at col. 7, ll. 40-49. Finally,
`
`the variables are assigned to instrumentation signals in step 340. Id. at col. 7, ll. 50-
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`54. The results of instrumentation, are shown using figures that show the code
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`before (for example, Figure 8) and after (for example, Figure 9) a method of
`
`instrumentation, such as that illustrated in Figure 3, is applied to source code.
`
`Figure 8, reproduced below, depicts sample Verilog source code prior to using a
`
`
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`7
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`method for instrumentating the code.
`
`Figure 8, above, illustrates the source code of a Verilog “always” block 800
`
`prior to instrumentation. Id. at col. 8, ll. 65-67. Figure 9, reproduced below,
`
`depicts the sample source code shown in Figure 8 after the method for
`
`
`
`instrumenting has been applied.
`
`
`
`8
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`Figure 9, above, illustrates the results of applying instrumentation to the code
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`depicted in Figure 8. Id. at col. 8, ll. 65-67. The instrumentation signals are
`
`SIG_TRACE1, SIG_TRACE2, SIG_TRACE3, and SIG_TRACE4. Id. at col. 9,
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`
`
`
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`9
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`ll. 10-14.
`
`
`
`Figure 10, above, illustrates the gate-level logic synthesized from the
`
`instrumented source code of Figure 9. Id. at col. 3, ll. 36-37. Other examples
`
`illustrate the same process using VHDL source code in place of the Verilog source
`
`code. See id. at Figures 4-6 and accompanying text.
`
`Based on the disclosure of the ’376 patent, for purposes of this decision, we
`
`conclude that the broadest reasonable interpretation of the claimed instrumentation
`
`signal at least encompasses an output signal created during synthesis of RTL source
`
`code by inserting additional logic, preserved from the source code, that indicates
`
`whether the corresponding RTL source code statement is active.
`
`2.
`
`Gate-Level Netlist
`
` “Gate-level netlist” is not explicitly defined in the written description of the
`
`’376 patent. However, the ’376 patent describes a gate-level netlist as a product of
`
`
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`10
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`synthesizing a high-level description language. Id. at col. 1, ll. 26-27; see also
`
`Abstract “A gate-level netlist is synthesized from the source code.”). In addition,
`
`the ’376 patent makes clear that a gate-level netlist is not itself a circuit or source
`
`code of a format suitable for programming an emulator, but instead is an
`
`intermediate representation of a circuit:
`
`The RTL source code can by synthesized into a gate-level netlist. The gate-
`level netlist can be verified using gate-level simulation. The gate-level
`simulation can be performed using a software gate-level simulator.
`[A]lternatively, the gate-level simulation may be performed by converting the
`gate-level netlist into a format suitable for programming an emulator, a
`hardware accelerator, or a rapid-prototyping system so that the digital circuit
`description can take an actual operating hardware form. ’376 patent, col. 1,
`ll. 35-43.
`
`For purposes of this decision, we interpret the claimed gate-level netlist as an
`
`intermediate representation of a circuit made up of a description or list of the gates
`
`to be used in the actual hardware implementation.
`
`3.
`
`Gate-Level Design
`
`The ’376 patent appears to use the terms “gate-level netlist” and “gate-level
`
`design” interchangeably. For example, the first use of the term “gate-level design”
`
`is in the Abstract, which states that one method of facilitating gate level simulation
`
`“results in a modified gatelevel netlist,” which “may be accomplished by . . .
`
`generating the modified gate-level netlist” or “[a]lternatively, cross-reference
`
`instrumentation data including instrumentation logic can be generated without
`
`modifying the gate-level design.” ’376 patent Abstract. Later in the patent, very
`
`similar language is used substituting “gate-level netlist” for “gate-level design.” Id.
`
`
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`at col. 2, ll. 47-50 (“Alternatively, the gate-level netlist is not modified but the
`
`instrumentation signals implementing the instrumentation logic are contained in a
`
`cross-reference instrumentation database.”).
`
`In addition, as described above, a gate-level netlist is the product of source
`
`code synthesis. This is also true of the gate-level design. See, e.g., id. at col. 4,
`
`ll. 1-4; Fig. 12, element 1260. The ’376 patent describes the gate-level design as
`
`typically comprising “a hierarchical or flattened gate level netlist representing the
`
`circuit to be simulated.” Id. at col. 4, ll. 5-7. Finally, several of the claims use the
`
`two terms to refer to the same thing: “A method of generating a gate-level netlist,
`
`comprising the steps of: a) receiving . . . source code . . . b) inserting a unique local
`
`variable assignment statement into the source code . . . c) inserting a corresponding
`
`instrumentation signal assignment statement into the source code . . .; and d)
`
`synthesizing the source code into a gate-level design including the instrumentation
`
`signals.” Id. at col. 16, ll. 1-17 (emphasis added); see also claim 16.
`
`Thus, for purposes of this decision, we interpret the claimed gate-level design
`
`to be interchangeable with gate-level netlist.
`
`4.
`
`Sensitivity List
`
` The claim term “sensitivity list” is not explicitly defined in the written
`
`description of the ’376 patent. The plain and ordinary meaning of this term in the
`
`VHDL context is “a list of signals a process is sensitive to,” where “process” is a
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`VHDL defined word that represents the behavior of some portion of the circuit
`
`design. VHDL Online Help, http://vhdl.renerta.com/source/vhd00062.htm (last
`
`visited Jan. 9, 2012).
`
`
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`
`Both Petitioner and Patent Owner point to examples consistent with this
`
`definition in lieu of defining the term. Petitioner points to the IEEE Standard
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`VHDL Reference Manual (“IEEE Reference”) published in 1993 and identified in
`
`the ’376 patent. Pet. 40-41 (citing ’376 patent, col. 1, ll. 19-22 (“Further
`
`information regarding VHDL may be found in the IEEE Standard VHDL Language
`
`Reference Manual (IEEE 1076-1987, IEEE 1076-1993).”)). This manual does not
`
`explicitly define the term sensitivity list, but gives an example of the keyword
`
`process with a sensitivity list in parenthesis. IEEE Reference at 126
`
`(“process_statement ::= [process_label : ] [ postponed ] process [ (sensitivity_list)
`
`] . . . “).
`
`Patent Owner points to Figures 17-18 and the associated description (col. 11,
`
`l.44 - col. 12, l. 22) in the ’376 patent. Pet. 35. The description of Figure 18,
`
`reproduced below, states that “[t]he sensitivity list of process P1 includes signals a,
`
`b, and c.” Id. at col. 11, ll. 59-61.
`
`
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`13
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`Figure 18, above, illustrates source with the code added to determine if
`
`
`
`process P1 is active. Id. at col. 11, ll. 59-61.
`
`Thus, for puposes of this decision, we interpret the claim term “sensitivity
`
`list” as a list of signals a process is sensitive to specified in a parenthetical to the
`
`VHDL process statement.
`
`II. DECISION ON PETITION
`
`A. Overview
`
`For the reasons described below, we institute an inter partes review of claims
`
`1-9, 11, 28, and 29 based on anticipation by Gregory, but decline to institute inter
`
`partes review based on any other asserted grounds. We decline to institute inter
`
`partes review on claims 10, 12-15, 20-27, and 30-33.
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`
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`B.
`
`35 U.S.C. § 315(b)
`
`Patent Owner argues that institution of an inter partes review trial is barred
`
`under 35 U.S.C. § 315(b). Section 315(b) states as follows:
`
`An inter partes review may not be instituted if the petition requesting the
`proceeding is filed more than 1 year after the date on which the petitioner,
`real party in interest, or privy of the petitioner is served with a complaint
`alleging infringement of the patent.
`
`Patent Owner asserts that EVE-USA, Inc. (“EVE”) is a privy of Petitioner and
`
`therefore the complaint served on EVE in the May 2006 case should trigger
`
`§ 315(b). Prelim. Resp. 1-2. Patent Owner bases this allegation on the fact that as
`
`of at least October 4, 2012, EVE is a wholly owned subsidiary of Synopsys. Id. at 2
`
`(citing Ex. 2004 at ¶ 13 (Complaint for Declaratory Judgment and Injunctive Relief,
`
`Synopsys, Inc. v. Mentor Graphics Corp., 3:12-cv-050025-LB (N.D. Cal., filed
`
`Sept. 27, 2012)); Ex. 2006 (Synopsys Press Release)). Therefore, according to
`
`Patent Owner, the Petition in this case, filed by Synopsis on September 26, 20121,
`
`is more than one year after service of the complaint on EVE, a privy of Synopsis.
`
`Prelim. Resp. 1-9.
`
`We do not agree with Patent Owner’s analysis. The plain language of
`
`§ 315(b) precludes institution if the petition is filed “more than 1 year after the date
`
`
`1 In a footnote, Patent Owner asserts that the effective filing date of the Petition is
`September 27, 2012, rather than the September 26, 2012, accorded filing date.
`Prelim. Resp. 4 n.2. Patent Owner bases this assertion on the fact that, due to an
`incorrect address, Patent Owner did not receive the Petition until September 27,
`2012. Id. (citing Ex. 2005 (Banner & Witcoff’s “Messenger Log”)). We are not
`persuaded that the accorded filing date of September 26, 2012, is in error.
`15
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`on which . . . privy of the petitioner is served with a complaint.” Patent Owner has
`
`not persuasively shown that Petitioner was a privy of EVE in 2006 when EVE was
`
`served with a complaint alleging infringement of the ’376 patent. In fact, Patent
`
`Owner appears to concede as much. See Prelim. Resp. 2 (“EVE and Synopsys were
`
`separate companies until the autumn of 2012.”); Prelim. Resp. 7-8 (“In 2006, EVE
`
`was the sole owner of all rights in the ZeBu line of products. Any interest
`
`Synopsys holds today is derived from its acquisition of EVE.”).
`
`Furthermore, Patent Owner does not provide persuasive evidence that
`
`Synopsis and EVE were in privity on the filing date of the Petition. Patent Owner
`
`does not direct us to any persuasive evidence that Synopsis and EVE were in privity
`
`prior to October 4, 2012. Although there is evidence that on September 27, 2012,
`
`Synopsis and EVE entered into an “agreement to acquire,” there is no evidence that
`
`such an agreement created privity between the two entities. Prelim. Resp. 3 (citing
`
`Ex. 2004 at ¶ 13 (Complaint)).
`
`Instead of showing that Synopsis and EVE were in privity on the relevant
`
`dates, Patent Owner argues that it is enough that Synopsis and EVE are in privity as
`
`of the date that an inter partes review is instituted. Id. at 4-5 (citing as a relevant
`
`date December 31, 2012, “the earliest possible date on which an inter partes review
`
`could be instituted by the Director”). Patent Owner asserts that because Synopsys
`
`is a successor-in-interest of EVE, the Director is barred from instituting an inter
`
`partes review of the ’376 Patent based on a petition filed by either EVE or
`
`Synopsis. Prelim. Resp. 7 (citing Taylor v. Sturgell, 553 U.S. 880, 894 (2008)
`
`(“Qualifying relationships [for non-party preclusion] include, but are not limited to,
`
`
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`preceding and succeeding owners of property, bailee and bailor, and assignee and
`
`assignor.”)). Patent Owner argues that it is the property interest in EVE’s products,
`
`the ZeBu line of emulators that were accused of infringement in 2006, that leads to
`
`the alleged bar of inter parties review by § 315(b). Prelim. Resp. 6-8. But that
`
`particular property interest is irrelevant here. Patentability, not infringement, is the
`
`issue before the Board in an inter partes review. See 35 U.S.C. § 311(b). Any
`
`potentially infringing products are irrelevant to the issues raised in the Petition, all
`
`of which involve patentability. Id. The only property right at issue in this
`
`proceeding is that of the ’376 patent owned by Patent Owner. Thus, any privity
`
`created by successive interests in EVE’s products, does not apply here. See Int’l
`
`Nutrition Co. v. Horphag Research, Ltd., 220 F.3d 1325, 1329 (Fed. Cir. 2000)
`
`(“[W]hen one party is a successor in interest to another with respect to a particular
`
`property, the parties are in privity only with respect to an adjudication of rights in
`
`the property that was transferred; they are not in privity for other purposes, such as
`
`an adjudication of rights in other property that was never transferred between the
`
`two. Put another way, the transfer of a particular piece of property does not have
`
`the effect of limiting rights of the transferee that are unrelated to the transferred
`
`property.”); see also Shamrock Techs., Inc. v. Medical Sterilization, Inc., 903 F.2d
`
`789, 793 (Fed. Cir. 1990) (“What constitutes ‘privity’ varies, depending on the
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`purpose for which privity is asserted.”).
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`“Whether a party who is not a named participant in a given proceeding
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`nonetheless constitutes a ‘real party-in-interest’ or ‘privy’ to that proceeding is a
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`highly fact-dependent question.” Office Patent Trial Practice Guide, Fed. Reg.
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`48759 (Aug. 14, 2012) (citing Taylor, 553 U.S. 880). “The Office intends to
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`evaluate what parties constitute ‘privies’ in a manner consistent with the flexible
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`and equitable considerations established under federal caselaw.” Id. Petitioner
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`provides no persuasive evidence that at the time of service of the 2006 complaint
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`Synopsis could have exercised control over EVE’s participation in the proceeding,
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`or vice versa. Thus, § 315(b) does not bar institution of inter partes review based
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`on Synopsis’ Petition.
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`C. Koch
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`Koch is an article published in 1996 describing a method of maintaining the
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`correlation between hardware elements and the behavior level source code during
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`hardware emulation of an integrated circuit in order to allow symbolic debugging.
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`Koch at 1. Koch refers to this method as “Source Level Emulation” or “SLE” and
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`presents details of how to relate breakpoints set in the specification to the
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`implemented circuit by “logging the synthesis steps” and “backannotating the
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`values read from the circuit.” Id.
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`1. Anticipation
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`Petitioner asserts that claims 1-5, 8-11, 20-28, 32, and 33 are anticipated by
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`Koch.
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`Claims 1-5, 8, 9, 20-23, 28, 32, and 33
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`We agree with Patent Owner that Koch does not explicitly disclose synthesis
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`of source code into a gate-level netlist as required by independent claim 1, or into a
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`gate-level design as required by independent claims 5, 20, 28, and 32. See Prelim.
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`Resp. 16.
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`Petitioner states that Koch “analyzes gate-level designs through hardware
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`emulation and keeps the correlation between the gate-level design and the VHDL
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`(RTL) design.” Prelim. Resp. 9-10, 14 (citing Koch at 1) (emphasis added). To
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`justify this assertion, Petitioner appears to rely on the fact that Koch describes
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`hardware emulation and discloses that such emulation occurs at the gate level.
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`Prelim. Resp. 15. Petitioner also relies on the ’376 patent’s statement that
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`“[s]ynthesis is the process of generating a gate-level netlist from the high level
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`description languages.” Id. (quoting ’376 patent, col. 1, ll. 26-27).
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`Koch does not explicitly state that it generates, synthesizes, verifies, or
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`analyzes gate-level netlists or designs. In fact, the only reference to “gate level” in
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`Koch is the aforementioned statement that “emulation works at the gate level.”
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`Koch at 1. This particular statement does not, by itself, lead to the conclusion that
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`Koch creates or makes use of a gate-level netlist or design as we interpret that term.
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` Moreover, Koch describes a process called “high level synthesis” which generates
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`a circuit that “contains a data path . . . and a controller . . . a finite state machine that
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`sets control values for the data path and reacts to condition values from the data
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`path.” Koch at 2 (emphasis added). Although it is true that a typical circuit,
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`including the circuit generated by Koch, is made up of gates and therefore could be
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`classified as a gate-level circuit—it is not clear that Koch at any point generates a
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`gate-level design or netlist—an intermediate representation of a circuit. Instead,
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`Koch describes going directly from VHDL to a circuit: “High level synthesis
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`generates a circuit from a software program like specification.”
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`Further, the ’376 patent’s definition of synthesis as creating a gate-level
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`netlist is not useful in the context of Koch. First, Koch uses a different term than
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`the ’376 patent—high level synthesis as opposed to synthesis. Second, Koch
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`explicitly defines that term without any reference to a gate-level netlist.
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`Thus, we decline to institute an inter partes review on the basis that
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`independent claims 1, 5, 20, 28, and 32, or their dependent claims 2-4, 8-10, 21-23,
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`and 33, are anticipated by Koch.
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`Claim 24
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`Claim 24, reproduced below with emphasis added, refers to the limitation
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`“gate-level design” only in its preamble.
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`A method of simulating a gate-level design comprising the steps of:
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`a) identifying a sensitivity list of a process;
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`b) generating logic to identify signal events for any signal in the
`sensitivity list; and
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`c) identifying the process as active during simulation when a signal event
`occurs for any signal in the sensitivity list.
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`“In general, a preamble limits the invention if it recites essential structure or
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`steps, or if it is ‘necessary to give life, meaning, and vitality’ to the claim. Catalina
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`Mktg. Int’l, Inc. v. Coolsavings.com, Inc., 289 F.3d 801 (Fed. Cir. 2002) (quoting
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`Pitney Bowes Inc. v. Hewlett-Packard Co., 182 F.3d 1298, 1305 (Fed. Cir. 1999)).
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`While Petitioner does not explicitly address whether the preamble of claim 24 is
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`limiting (See Pet. 25, 40), Patent Owner appears to concede that the preamble of
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`claim 24 does limit the claimed invention to “a method of simulating a gate-level
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`design.” See Prelim. Resp. 25 (“Claim 24 is thus a method of simulating a gate-
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`level design. The step of ‘generating logic to identify signal events for any signal in
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`the sensitivity list’ will be recognized as a step associated with synthesizing a gate-
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`level design from the source code…”) (emphases in original).
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`“Whether to treat a preamble as a limitation is a determination resolved only
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`on review of the entire patent to gain an understanding of what the inventors
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`actually invented and intended to encompass by the claim.” Catalina Mktg., 289
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`Fed. Cir. at 808. The invention of the ’376 patent relates to methods of enabling
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`debugging support for gate-level simulation. See, e.g., ’376 patent, Abstract; col. 2,
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`ll. 26-29. The specification makes clear that such gate-level simulation involves the
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`use of a gate-level netlist. See, e.g., id. at Abstract; Fig. 1; Fig. 2; Fig. 12; Fig. 21;
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`col. 1, ll. 36-37; col. 2, ll. 18-24, 30-36. In addition, each of the described
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`embodiments uses a gate-level netlist. Id. at col. 2, ll. 40-55; col. 4, ll. 2-4; col. 5,
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`ll. 17-20, 31-33. For these reasons, we conclude that the preamble of claim 24 is a
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`limitation of the claim because it describes an essential element of the invention.
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`Thus, claim 24 also requires a gate-level design, which is not explicitly
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`disclosed by Koch. We therefore decline to institute an inter partes review on the
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`basis that claim 24 is anticipated by Koch.
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`2. Obviousness
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`In the section of the Petition labeled “The specific art and statutory ground(s)
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`on which the challenge is based,” Petitioner asserts, in a single sentence, that Koch,
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`by itself, renders claims 1-5, 8-10, 20-24, 28, 32, and 33 obvious under 35 U.S.C.
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`§ 103. Pet. 4. Petitioner does not explain the reasoning behind this assertion. In
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`fact, Petitioner does not clearly refer to this ground anywhere else in the Petition.
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`In the “Summary of Invalidity Arguments,” Petitioner states only that Koch
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`anticipates the challenged claims and renders obvious claims 11 and 25-27 when
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`combined with 1995 Koch. Pet. 10.
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`The petition must identify with particularity each claim challenged, the
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`grounds on which the challenge to each claim is based, and the evidence that
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`supports the