Blanchard Decl.
`
`Inter Partes Review of U.S. 5,652,084
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`__________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`___________________
`
`TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
`(TSMC),
`Petitioner
`
`v.
`
`DSS TECHNOLOGY MANAGEMENT, INC.
`Patent Owner
`___________________
`
`Patent 5,652,084
`
`Title: METHOD FOR REDUCED PITCH LITHOGRAPHY
`_____________________
`
`DECLARATION OF RICHARD A. BLANCHARD, PH.D.
`UNDER 37 C.F.R. § 1.68
`
`I, Richard Blanchard, do hereby declare:
`
`1.
`
`I am making this declaration at the request of Taiwan Semiconductor
`
`Manufacturing Company, Ltd. (“TSMC”) in the matter of the Inter Partes Review
`
`of U.S. Patent No 5,652,084 (“the ’084 Patent”) to James M. Cleeves.
`
`2.
`
`(1)
`
`(2)
`
`In the preparation of this declaration, I have studied:
`
`The ’084 Patent, TSMC-1001;
`
`The prosecution history of the ’084 Patent, TSMC-1002;
`
`–1–
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`TSMC-1009
`TSMC v. DSS
`Page 1 of 57
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`
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`Inter Partes Review of U.S. 5,652,084
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`__________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`___________________
`
`TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
`(TSMC),
`Petitioner
`
`v.
`
`DSS TECHNOLOGY MANAGEMENT, INC.
`Patent Owner
`___________________
`
`Patent 5,652,084
`
`Title: METHOD FOR REDUCED PITCH LITHOGRAPHY
`_____________________
`
`DECLARATION OF RICHARD A. BLANCHARD, PH.D.
`UNDER 37 C.F.R. § 1.68
`
`I, Richard Blanchard, do hereby declare:
`
`1.
`
`I am making this declaration at the request of Taiwan Semiconductor
`
`Manufacturing Company, Ltd. (“TSMC”) in the matter of the Inter Partes Review
`
`of U.S. Patent No 5,652,084 (“the ’084 Patent”) to James M. Cleeves.
`
`2.
`
`(1)
`
`(2)
`
`In the preparation of this declaration, I have studied:
`
`The ’084 Patent, TSMC-1001;
`
`The prosecution history of the ’084 Patent, TSMC-1002;
`
`–1–
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`TSMC-1009
`TSMC v. DSS
`Page 1 of 57
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`Blanchard Decl.
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`Inter Partes Review of U.S. 5,652,084
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`(3) U.S. Patent No. 5,710,061 (“Cleeves II”), TSMC-1003;
`
`(4)
`
`Japanese Patent App. No. 04-71222 (“Jinbo”), TSMC-1004;
`
`(5) U.S. Patent No. 4,591,547 (“Brownell”), TSMC-1005;
`
`(6) U.S. Patent No. 4,931,351 (“McColgin”), TSMC-1006;
`
`(7) U.S. Patent No. 4,548,688 (“Matthews”), TSMC-1007; and
`
`(8) U.S. Patent No. 5,158,910 (“Cooper”), TSMC-1008.
`
`3.
`
`(1)
`
`In forming the opinions expressed below, I have considered:
`
`The documents listed above, and
`
`(2) My knowledge and experience based upon my work in this area as
`
`described below.
`
`4.
`
`I am familiar with and am a practitioner of the technology at issue and
`
`am aware of the state of the art at the time the application resulting in the ’084
`
`Patent was filed. The earliest priority date is December 22, 1994. Based on the
`
`technologies disclosed in the ’084 Patent, I believe that one of ordinary skill in the
`
`art would include someone who has a B.S. degree in Electrical Engineering,
`
`Material Science, or Physics, or equivalent training, as well as 3-5 years of
`
`experience in the field of integrated circuit (IC) design, IC fabrication, and
`
`lithographic fabrication techniques. Unless otherwise stated, when I give my
`
`understanding and analysis below, it is consistent with the level of one of
`
`ordinary skill in these technologies at and around the filing date of the ’084
`
`–2–
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`TSMC-1009 / Page 2 of 57
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`
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`Blanchard Decl.
`
`patent.
`
`I.
`
`QUALIFICATIONS
`
`Inter Partes Review of U.S. 5,652,084
`
`5.
`
`I am a consultant for Thomson Reuters Expert Witness Services
`
`(formerly known as Silicon Valley Expert Witness Group), a consulting company
`
`specializing in expert witness litigation support and technology consulting. I also
`
`provide technical consulting services to the semiconductor and electronics industry
`
`through Blanchard Associates.
`
`6.
`
`My academic credentials include both a Bachelor of Science
`
`Degree in Electrical Engineering (BSEE) and a Master of Science Degree in
`
`Electrical Engineering (MSEE) from the Massachusetts Institute of
`
`Technology in 1968 and 1970, respectively. I subsequently obtained a Ph.D.
`
`in Electrical Engineering in 1982 from Stanford University.
`
`7.
`
`My professional background and technical qualifications are stated
`
`above and are also reflected in my Curriculum Vitae, which is attached as TSMC-
`
`1010. I am being compensated at a rate of $275.00 per hour, with reimbursement
`
`for actual expenses, for my work related to this Petition for Inter Partes Review.
`
`My compensation is not dependent on and in no way affects the substance of my
`
`statements in this Declaration.
`
`8.
`
`I have worked or consulted for more than 40 years as an
`
`Electrical Engineer. My primary focus has been on the development,
`
`–3–
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`TSMC-1009 / Page 3 of 57
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`Blanchard Decl.
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`Inter Partes Review of U.S. 5,652,084
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`manufacture, operation, and use of devices and integrated circuits, the
`
`assembly of these devices and integrated circuits, products that use them,
`
`and their failures. My employment history following my graduation from
`
`MIT began at Fairchild Semiconductor in 1970. At Fairchild, my
`
`responsibilities included circuit and device design, process development, and
`
`product engineering in the Linear Integrated Circuits Department.
`
`9.
`
`In 1974, I joined Foothill College as an Associate Professor in
`
`the Engineering & Technology Division. My responsibilities included
`
`developing a program in Semiconductor Technology as well as teaching
`
`other courses in the division. While at Foothill College, I co-founded two
`
`companies, Cognition and Supertex, and later joined Supertex as a Vice
`
`President in 1978. At Supertex, I designed and developed discrete DMOS
`
`(double-diffused metal oxide semiconductor) transistors, as well as
`
`integrated circuits that contained DMOS transistors. At Supertex, I also
`
`supervised the in-house assembly area, which included responsibility for the
`
`associated manufacturing processes.
`
`10.
`
`I left Suptertex to join Siliconix in 1982, where I soon became
`
`Vice President of Engineering, with the responsibility for directing all of the
`
`company’s product design and development. At Siliconix, I directed and
`
`contributed to the development of both discrete transistors and integrated
`
`–4–
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`TSMC-1009 / Page 4 of 57
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`Blanchard Decl.
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`Inter Partes Review of U.S. 5,652,084
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`circuits, including aspects of their assembly.
`
`11.
`
`In 1987, I joined IXYS Corporation as a Senior Vice President
`
`with the responsibility for organizing an integrated circuit department. At
`
`IXYS, I developed integrated circuits that contained DMOS devices or that
`
`interfaced to DMOS devices. My responsibilities included the design,
`
`assembly, and testing of these integrated circuits.
`
`12.
`
`These duties continued until 1991, when I left IXYS to set up
`
`Blanchard Associates, a consulting firm specializing in semiconductor
`
`technology, including intellectual property. Soon thereafter, I was invited to
`
`join Failure Analysis Associates, which I did in late 1991. At Failure
`
`Analysis Associates, I investigated failures in electrical and electronic
`
`systems in addition to performing design and development consulting.
`
`13.
`
`I left Failure Analysis in 1998 to join IP Managers, which later
`
`merged with Silicon Valley Expert Witness Group, now known as Thomson
`
`Reuters Expert Witness Services ("Thomson Reuters"). At Thomson
`
`Reuters, I work with companies on patent and trade secret matters. I also
`
`consult for a number of semiconductor companies, working with them to
`
`develop products and intellectual property, or assisting them in other
`
`technical areas through Blanchard Associates. Design and Development
`
`projects that I have worked on range from the design and evaluation of
`
`–5–
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`TSMC-1009 / Page 5 of 57
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`Inter Partes Review of U.S. 5,652,084
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`specific components, to the selection of the technology appropriate for the
`
`fabrication of different subsystems of a system.
`
`14.
`
`I am a member of a number of professional societies, including
`
`the Institute of Electrical and Electronic Engineers, the International
`
`Microelectronics and Packaging Society, the American Vacuum Society, the
`
`Electronic Device Failure Analysis Society, and the Electrostatic Discharge
`
`Society.
`
`15. A copy of my curriculum vitae is attached as TSMC-1010.
`
`Additional information regarding my education, technical experience and
`
`publications, including a list of the US patents of which I am an inventor, is
`
`included therein.
`
`II. MY UNDERSTANDING OF THE RELEVANT LEGAL STANDARDS
`
`16.
`
`I have been asked to provide my opinions regarding whether the
`
`claims of the ’084 Patent are anticipated or would have been obvious to a person
`
`having ordinary skill in the art at the time of the alleged invention of the patent, in
`
`light of the prior art.
`
`Anticipation
`
`17.
`
`It is my understanding that, to anticipate a claim under 35 U.S.C. §
`
`102, a reference must teach every element of the claim.
`
`–6–
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`TSMC-1009 / Page 6 of 57
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`
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`Blanchard Decl.
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`Obviousness
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`Inter Partes Review of U.S. 5,652,084
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`18.
`
`It is my understanding that a claimed invention is unpatentable under
`
`35 U.S.C. § 103 if the differences between the invention and the prior art are such
`
`that the subject matter as a whole would have been obvious at the time the
`
`invention was made to a person having ordinary skill in the art to which the subject
`
`matter pertains. I also understand that the obviousness analysis takes into account
`
`factual inquiries including the level of ordinary skill in the art, the scope and
`
`content of the prior art, and the differences between the prior art and the claimed
`
`subject matter.
`
`19.
`
`I have been informed that the Supreme Court has recognized several
`
`rationales for combining references or modifying a reference to show obviousness
`
`of claimed subject matter. I understand some of these rationales include the
`
`following: combining prior art elements according to known methods to yield
`
`predictable results; simple substitution of one known element for another to obtain
`
`predictable results; use of a known technique to improve a similar device (method,
`
`or product) in the same way; applying a known technique to a known device
`
`(method, or product) ready for improvement to yield predictable results; choosing
`
`from a finite number of identified, predictable solutions, with a reasonable
`
`expectation of success; and some teaching, suggestion, or motivation in the prior
`
`art that would have led one of ordinary skill to modify the prior art reference or to
`
`–7–
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`TSMC-1009 / Page 7 of 57
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`Blanchard Decl.
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`Inter Partes Review of U.S. 5,652,084
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`combine prior art reference teachings to arrive at the claimed invention.
`
`III. FINDINGS
`
`20.
`
`The findings below are based on my understandings of the art related
`
`to the ’084 Patent, as well as what I think one of ordinary skill in the art would
`
`understand, at the time period at and prior to December 22, 1994.
`
`Background Of ’084 Patent
`
`21.
`
`The ‘084 patent is directed to “lithography processing for
`
`semiconductor fabrication”. TSMC-1001, Cleeves at 1:10-12. In an exemplary
`
`lithography (short for “photolithography”) process, “photoresist is deposited over
`
`the layer to be patterned and is exposed to ultraviolet radiation through a mask that
`
`defines the pattern to be formed in the photoresist.” TSMC-1001, Cleeves at 1:19-
`
`22. “The photoresist is then developed to form a patterned photoresist layer over
`
`the underlying layer to be patterned.” TSMC-1001, Cleeves at 1:22-24. The
`
`patterned photoresist may then be used to selectively process exposed portions of
`
`the underlying layer. TSMC-1001, Cleeves at 1:24-27.
`
`22.
`
`The ’084 patent recognizes that the lithography process often “limit[s]
`
`the size and density with which semiconductor devices may be fabricated.”
`
`TSMC-1001, Cleeves at 1:28-30. The patent is concerned with improvements to
`
`the lithography process that allow the photoresist features to be formed more
`
`closely because “[a]s these features may be formed relatively closer to one another,
`
`–8–
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`TSMC-1009 / Page 8 of 57
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`the density with which semiconductor devices may be fabricated may be increased,
`
`allowing semiconductor devices to be fabricated with relatively smaller sizes.”
`
`TSMC-1001, Cleeves at 12:28-38.
`
`23.
`
`The ’084 Patent describes a technique for reducing the minimum
`
`spacing between adjacent features by using two different photoresists in a double-
`
`patterning lithography process. A first set of features is formed by exposing and
`
`patterning a first photoresist. TSMC-1001, Cleeves at 3:29-4:29. The first
`
`photoresist is “stabilized to withstand subsequent lithographic processing steps”
`
`and a second photoresist is formed over the first set of features. TSMC-1001,
`
`Cleeves at 4:30-5:55. The second photoresist is exposed and patterned to form a
`
`second set of features interleaved with the first set. TSMC-1001, Cleeves at 5:56-
`
`7:35. Exposed portions of the underlying layers can then be selectively processed.
`
`Because adjacent features are formed by two different resist layers, the spacing
`
`between the features may be reduced, which may in turn, increase the density of
`
`the semiconductor devices.
`
`24.
`
`These practices were well-known in the art prior to the date of the
`
`’084 Patent. In particular, references teaching the described double-patterning
`
`lithography were available in the literature to one having ordinary skill in the art at
`
`or around the priority date of the ’084 Patent.
`
`–9–
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`TSMC-1009 / Page 9 of 57
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`Inter Partes Review of U.S. 5,652,084
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`Meaning of Certain Terms of the ’084 Patent
`
`25.
`
`It is my understanding that in order to properly evaluate the ’084 Patent,
`
`the terms of the claims must be defined. It is my understanding that the claims are to be
`
`given their broadest reasonable interpretation in light of the specification. It is my
`
`further understanding that claim terms are given their ordinary and accustomed
`
`meaning as would be understood by one of ordinary skill in the art, unless the inventor,
`
`as a lexicographer, has set forth a special meaning for a term. The discussion of the
`
`claim terms below is my conclusion regarding each of the referenced terms, as defined
`
`in accordance with the broadest reasonable construction standard, and based on the
`
`understanding of a person of ordinary skill in the art.
`
`26.
`
`The ’084 Patent uses the term “imaging layer” in the claims, abstract,
`
`and detailed description. The specification of the ’084 Patent explains that an
`
`imaging layer may include “a suitable positive photoresist”, “a suitable negative
`
`photoresist”, “a suitable radiation-sensitive polyimide”, or “other suitable
`
`radiation-sensitive materials.” TSMC-1001, Cleeves at 3:34-42. Thus, a person of
`
`ordinary skill in the art would understand that the term “imaging layer” means a
`
`photoresist or other radiation-sensitive material.
`
`27.
`
`The ’084 Patent refers to “stabilizing” the patterned imaging layer.
`
`According to the specification, a patterned layer is “stabilized to withstand subsequent
`
`lithographic steps.” TSMC-1001, Cleeves at 4:34-35. Three examples of
`
`–10–
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`TSMC-1009 / Page 10 of 57
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`subsequent lithographic steps are provided. First, a patterned layer may be
`
`“stabilized to withstand chemical transformation as a result of any subsequent
`
`exposure to radiation, for example.” TSMC-1001, Cleeves at 4:35-38. Second, a
`
`patterned layer may be “stabilized to withstand dissolution by solvents during a
`
`subsequent spin-on of photoresist, for example.” TSMC-1001, Cleeves at 4:38-40.
`
`Third, a patterned layer may be “stabilized to withstand dissolution by a
`
`subsequent developer, for example”. TSMC-1001, Cleeves at 4:40-42. One of
`
`ordinary skill in the art would understand the term “stabilize” to mean rendering a
`
`material able to withstand one or more of the exemplary subsequent processing
`
`steps: exposure to radiation, exposure to a solvent, and/or exposure to a developer.
`
`28.
`
`The ’084 Patent claims recite that “the second patterned layer and the
`
`first patterned layer form a single patterned layer.” The specification shows that
`
`the single patterned layer includes features of the first patterned layer positioned
`
`between features of the second patterned layer. TSMC-1001, Cleeves at FIG. 5.
`
`Thus, one of ordinary skill in the art would understand the term “single patterned
`
`layer” to mean a single layer of patterned features, which may be formed from one
`
`or more imaging layers.
`
`29.
`
`The ’084 Patent refers to using a photoresist feature as a “disposable
`
`post”. According to the’084 Patent, “disposable posts are removed to form
`
`openings for a subsequent layer, such as a contact, via, or interconnect layer for
`
`–11–
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`TSMC-1009 / Page 11 of 57
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`Blanchard Decl.
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`Inter Partes Review of U.S. 5,652,084
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`example”. TSMC-1001, Cleeves at 12:53-62. The ’084 Patent refers to U.S.
`
`Application No. 08/179,615 for more details. U.S. Application No. 08/179,615
`
`became (through a continuation) U.S. Patent No. 5,710,061 (“the ‘061 patent”),
`
`which provides an example where “photosensitive material 220 has been patterned
`
`to form post 221 over diffusion region 201 so as to later form a contact opening in
`
`an insulative layer to be formed over the surface of the wafer.” TSMC-1003, ’061
`
`Patent at 5:39-42. Thus, one of ordinary skill in the art would understand the term
`
`disposable post to mean a patterned feature disposed within another layer of
`
`material that may be removed to define an opening such as a contact, via, or
`
`interconnect layer opening.
`
`Summary of the State of the Prior Art
`
`30.
`
`I have reviewed the reference referred to as Jinbo. Jinbo describes a
`
`lithographic process for use in manufacturing semiconductor devices. TSMC-
`
`1004, Jinbo at p. 2. Just like the ’084 Patent, Jinbo recognizes that single exposure
`
`patterning techniques have been limited by the minimum resolvable distance, an
`
`optical property of a photolithographic system. TSMC-1004, Jinbo at p. 3. Jinbo
`
`teaches that a multiple exposure process can overcome this limitation and further
`
`reduce semiconductor device spacing. TSMC-1004, Jinbo at pp. 6-7.
`
`31.
`
`The technique in Jinbo exposes and patterns a first resist to form a
`
`first resist pattern. TSMC-1004, Jinbo at pp. 4-5. The patterned first resist is then
`
`–12–
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`TSMC-1009 / Page 12 of 57
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`exposed to a plasma of oxygen and CF4 to make the resist “insoluble” to the
`
`solvents and developers used in forming subsequent resists “so that even though
`
`first resist pattern 13b is covered by second resist 15, no destruction of the first
`
`resist pattern itself occurs, and no mixing with the second resist occurs either.”
`
`TSMC-1004, Jinbo at p. 5. Once the first resist is made insoluble, a second resist
`
`is formed on the first. TSMC-1004, Jinbo at p. 5. The second resist is exposed and
`
`developed to form a second resist pattern interleaved with the first resist pattern.
`
`TSMC-1004, Jinbo at p. 5. The resulting resist shapes are spaced more closely
`
`than can be achieved with a comparable single resist technique. TSMC-1004,
`
`Jinbo at pp. 5-6.
`
`32.
`
`Jinbo teaches that exposing the patterned resist to the plasma of
`
`oxygen and CF4 makes the resist “insoluble” to two of the three exemplary
`
`processing steps disclosed in the ’084 Patent, namely the resist becomes insoluble
`
`to solvents and developers used for the second resist. In addition, it was known at
`
`the time of the invention of the ’084 Patent that exposure to a plasma of oxygen
`
`and CF4 makes a resist “insoluble” to subsequent radiation, the third and final
`
`exemplary processing step. For example, Brownell teaches how this plasma
`
`stabilizes against subsequent radiation exposure.
`
`33.
`
`I have reviewed the reference referred to as Brownell. Brownell is
`
`also directed to a photolithographic technique using more than one photoresist
`
`–13–
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`TSMC-1009 / Page 13 of 57
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`material. TSMC-1005, Brownell at 1:10-15. Brownell teaches that after
`
`patterning a first photoresist, a fluorine-containing plasma “makes the fixed
`
`photoresist neither photosensitive to further light, nor dissolvable by the usual
`
`solvents which are used in the subsequent steps. TSMC-1005, Brownell at 4:11-
`
`14. Thus, Brownell provides further explanation of how a fluorine-containing
`
`plasma, as described in Jinbo, stabilizes the first patterned layer. One of ordinary
`
`skill in the art would have recognized that Brownell’s stabilization method directly
`
`addresses the need of Jinbo that “no destruction of the first resist pattern itself
`
`occurs, and no mixing with the second resist occurs either” (TSMC-1004, Jinbo at
`
`p. 5) by making the first resist “neither photosensitive to further light, nor
`
`dissolvable by the usual solvents.” TSMC-1005, Brownell at 4:11-14. Thus, one
`
`of ordinary skill in the art would have been motivated to use the technique of
`
`Brownell in combination with the technique of Jinbo. Furthermore, Brownell
`
`teaches the known functionality of stabilizing resist, to produce a known and
`
`predictable result.
`
`34.
`
`I have reviewed the reference referred to as McColgin. McColgin
`
`teaches an alternative technique for stabilizing a resist referred to as silylation.
`
`The technique includes “contacting the developed resist with a vapor comprising a
`
`silicon-containing compound to effect silylation thereof and thereby impart etch
`
`resistance” to a resist. TSMC-1006, McColgin at 2:9-46. Jinbo teaches that the
`
`–14–
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`TSMC-1009 / Page 14 of 57
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`Inter Partes Review of U.S. 5,652,084
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`“first resist insolubilizing treatment method is also not limited to the method in the
`
`application example, and could be another method.” TSMC-1004, Jinbo at p. 6.
`
`McColgin teaches a known alternative insolubilizing treatment that produces a
`
`known and predictable result. Accordingly, it would have been obvious to one of
`
`ordinary skill in the art to use the silylation technique of McColgin to stabilize the
`
`first resist.
`
`35.
`
`I have reviewed the reference referred to as Matthews. Matthews
`
`teaches another technique for stabilizing a photoresist by exposing it to radiation.
`
`TSMC-1007, Matthews at 2:53-58. The exposure may be accompanied by
`
`gradually heating the photoresist. TSMC-1007, Matthews at 4:52-59. As
`
`discussed above, Jinbo recognizes that any suitable “insolubilizing treatment” may
`
`be used in the method, and Matthews teaches another known alternative treatment
`
`that produces a known and predictable result. Accordingly, it would have been
`
`obvious to one of ordinary skill in the art to use the technique of Matthews to
`
`stabilize the first resist.
`
`36.
`
`I have reviewed the reference referred to as Cooper. While Jinbo is
`
`concerned with forming resist patterns generally, Cooper expands on the concept
`
`and teaches using a resist pattern, such as those formed by Jinbo, to form sacrificial
`
`plugs used to define opening for contacts and other structures. A first exemplary
`
`photoresist plug “defines an area where a self-aligned contact will be formed
`
`–15–
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`TSMC-1009 / Page 15 of 57
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`Blanchard Decl.
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`between conductive members” and a second exemplary photoresist plug “defines
`
`an area where an isolated contact will be formed”. TSMC-1008, Cooper at 3:52-
`
`56. “[R]emoving the plugs defines a self-aligned contact opening … and an
`
`isolated contact opening”. TSMC-1008, Cooper at 4:26-30. Cooper teaches that
`
`photoresist shapes are desirable structures to use as sacrificial plugs because of the
`
`“high resolution capabilities of most imagable materials.” TSMC-1008, Cooper at
`
`4:49-56. Jinbo provides an improved technique for forming resist features “below
`
`the resolution limit of the projection exposure apparatus”. TSMC-1004, Jinbo at p.
`
`3. Accordingly, one of ordinary skill in the art would have been motivated to use
`
`the resist patterning technique of Jinbo to form sacrificial plugs because the
`
`technique of Jinbo further improves the resolution capabilities of the imagable
`
`material (i.e., the resist).
`
`Comparison of the claims of the ’084 Patent to the prior art
`
`37.
`
`I believe that the elements of claims 1-16 of the ’084 Patent are taught
`
`by the prior art. I have included claim charts that map the prior art to claims 1-16
`
`in the pages that follow. These charts support my finding that the differences
`
`between the claims of the ’084 Patent and the prior art discussed herein are such
`
`that the subject matter as a whole would have been anticipated or obvious at the
`
`time the invention was made to a person having ordinary skill in the art to which
`
`the subject matter pertains. Reasons to combine are also provided in the charts.
`
`–16–
`
`TSMC-1009 / Page 16 of 57
`
`
`
`Blanchard Decl.
`
`Inter Partes Review of U.S. 5,652,084
`
`The prior art elements combined as detailed in the accompanying charts yield
`
`predictable results in support of the improvement in lithographic resolution.
`
`–17–
`
`TSMC-1009 / Page 17 of 57
`
`
`
`
`
`Blanchard Decl. Inter Partes Review of U.S. 5 652 084
`
`IV. CONCLUSION
`
`38.
`
`I declare that all statements made herein on my own knowledge are
`
`true and that all statements made on information and belief are believed to be true,
`
`and further, that these statements were made with the knowledge that willful false
`
`statements and the like so made are punishable by fine or imprisonment, or both,
`
`under Section 1001 or Title 18 of the United States Code.
`
`JW. 2% ram
`
`(Ltd 943%?H;
`
`Date
`
`Richard A. Blanchard
`
`_1g_
`
`TSMC-1009 I Page 18 of 57
`
`TSMC-1009 / Page 18 of 57
`
`
`
`Blanchard Decl.
`
`Inter Partes Review of U.S. 5,652,084
`
`U.S. Patent No. 5,652,084
`
`References
`Jinbo (Japanese Patent Application No. JP 04-71222)
`Publication Date: March 5, 1992
`Brownell (U.S. Patent No. 4,591,547)
`Patent Date: May 27, 1986
`McColgin (U.S. Patent No. 4,931,351)
`Patent Date: June 5, 1990
`Matthews (U.S. Patent No. 4,548,688)
`Patent Date: October 22, 1985
`Cooper (U.S. Patent No. 5,158,910)
`Patent Date: October 27, 1992
`
`Challenges:
`
`Challenge #1:
`
`Claims 1-8, 12, 15, and 16 are anticipated under 35 U.S.C. §102(b) by Jinbo.
`
`Challenge #2:
`
`Claims 1-8, 12, 15, and 16 are obvious under 35 U.S.C. §103(a) over Jinbo
`
`in view of Brownell.
`
`Challenge #3:
`
`Claim 9 is obvious under 35 U.S.C. §103(a) over Jinbo in view of
`
`McColgin.
`
`Challenge #4:
`
`Claims 10 and 11 are obvious under 35 U.S.C. §103(a) over Jinbo in view of
`
`Matthews.
`
`–19–
`
`TSMC-1009 / Page 19 of 57
`
`
`
`Blanchard Decl.
`
`Challenge #5:
`
`Inter Partes Review of U.S. 5,652,084
`
`Claims 13 and 14 are obvious under 35 U.S.C. §103(a) over Jinbo in view of
`
`Brownell and Cooper.
`
`–20–
`
`TSMC-1009 / Page 20 of 57
`
`
`
`Blanchard Decl.
`
`Inter Partes Review of U.S. 5,652,084
`
`Challenge #1: Claims 1-8, 12, 15, and 16 are anticipated under
`35 U.S.C. §102(b) by Jinbo.
`
`US 5,652,084 (Cleeves)
`Priority Date: Dec. 22, 1994
`
`[1.0] 1. A lithography method
`for semiconductor fabrication
`using a semiconductor wafer,
`comprising the steps of:
`
`Claims 1-8, 12, 15, and 16 are anticipated
`under 35 U.S.C. §102(b) by Jinbo.
`[1.0] Jinbo teaches a “pattern forming method
`used
`in
`the
`process
`of manufacturing
`semiconductor devices or the like.”
`(TSMC-
`1004, Jinbo at p. 2, emphasis added).
`The
`technique includes forming a first resist on a
`substrate,
`lithographically patterning the first
`resist,
`applying
`a
`second
`resist,
`and
`lithographically patterning the second resist.
`
`i rays
`for
`TSMR-365iR (positive resist
`made by Tokyo Ohka Kogyo Co. (Ltd.)) is
`formed,
`in this application example to a
`thickness of 1 µm, as first resist 13 on
`substrate 11 using spin coating (Figure 1
`(B)).
`. . . .
`[F]irst resist 13 is exposed with exposure
`light of 300 mJ/cm2.
`Next, the exposed first resist 13 is puddle-
`developed. . . .
`Next, substrate 11 … is spin-coated to a
`thickness of 1.0 µm with TSMR-365iR, used
`as the first resist in this case, as second resist
`15 (Figure 1 (D)).
`. . . .
`[S]econd resist 15 is
`exposure light of 300 mJ/cm2.
`Next, the second resist which has been
`exposed is developed . . . .
`(TSMC-1004,
`Jinbo at pp. 4-5, emphasis added).
`
`exposed with
`
`Jinbo also teaches that the substrate on which the
`resists are formed may include a semiconductor
`
`–21–
`
`TSMC-1009 / Page 21 of 57
`
`
`
`Blanchard Decl.
`
`Inter Partes Review of U.S. 5,652,084
`
`US 5,652,084 (Cleeves)
`Priority Date: Dec. 22, 1994
`
`Claims 1-8, 12, 15, and 16 are anticipated
`under 35 U.S.C. §102(b) by Jinbo.
`
`[1.1] (a) forming a first
`imaging layer over the
`semiconductor wafer;
`
`substrate.
`
`Note that the substrate referred to here is,
`for example, a glass substrate, a silicon
`substrate, a GaAs substrate or other type of
`substrate, or an insulating film on the
`substrate, a metal film or other thin film,
`and/or
`an intermediate body in which
`elements are constructed.
`(TSMC-1004,
`Jinbo at p. 3, emphasis added).
`
`Thus, Jinbo teaches a lithography method for
`semiconductor fabrication using a semiconductor
`wafer as recited by claim 1.
`[1.1] The term imaging layer should be construed
`to include a photoresist or other
`radiation-
`sensitive material. See TSMC-1009, Blanchard
`Decl. at p. 10, ¶ 26.
`
`Jinbo teaches forming a first photoresist over the
`semiconductor substrate.
`
`(TSMC-1004, Jinbo, FIG. 1A)
`
`i rays
`for
`TSMR-365iR (positive resist
`made by Tokyo Ohka Kogyo Co. (Ltd.)) is
`formed,
`in this application example to a
`thickness of 1 µm, as first
`resist 13 on
`substrate 11 using spin coating. (TSMC-
`1004, Jinbo at p. 4).
`
`–22–
`
`TSMC-1009 / Page 22 of 57
`
`
`
`Blanchard Decl.
`
`Inter Partes Review of U.S. 5,652,084
`
`US 5,652,084 (Cleeves)
`Priority Date: Dec. 22, 1994
`
`Claims 1-8, 12, 15, and 16 are anticipated
`under 35 U.S.C. §102(b) by Jinbo.
`
`[1.2a] Jinbo discloses patterning the first resist to
`form a patterned first resist.
`
`[1.2a] (b) patterning the first
`imaging layer in accordance
`with a first pattern to form a
`first patterned layer
`
`[1.2b] having a first feature;
`
`(TSMC-1004, Jinbo, FIG. 1B)
`
`Next, using an i ray projection exposure
`apparatus RA-101VLII (NA = 0.42: made by
`Hitachi (Ltd.)) on which is mounted a mask
`having a line and space pattern with which
`spaces 0.4 µm wide can be formed at a pitch
`of 1.2 µm on a resist, the mask alignment
`marks and the substrate alignment marks are
`positioned, and then first resist 13 is exposed
`with exposure light of 300 mJ/cm2.
`Next, the exposed first resist 13 is puddle-
`developed for 60 sec using a developer called
`NMD-W (2.38% tetramethylammonium
`hydroxide aqueous solution: made by Tokyo
`Ohka Kogyo Co.
`(Ltd.)), and first
`resist
`pattern 13a is obtained (Figure 1 (B)).
`(TSMC-1004, Jinbo at p. 4).
`
`[1.2b] Jinbo shows in FIG. 1B that the patterned
`resist 13a has a number of features including a
`first feature as recited.
`
`–23–
`
`TSMC-1009 / Page 23 of 57
`
`
`
`Blanchard Decl.
`
`Inter Partes Review of U.S. 5,652,084
`
`US 5,652,084 (Cleeves)
`Priority Date: Dec. 22, 1994
`
`Claims 1-8, 12, 15, and 16 are anticipated
`under 35 U.S.C. §102(b) by Jinbo.
`
`[1.3] (c) stabilizing the first
`patterned layer;
`
`(TSMC-1004, Jinbo, FIG. 1B, annotated)
`
`[1.3] The specification of the ’084 Patent defines
`a stabilized patterned layer as one capable of
`withstanding “subsequent lithographic processing
`steps”
`and gives
`three
`examples of
`such
`processing steps. In this way, ’084 Patent defines
`a stabilized pattern layer as one that withstands:
`
`1) “chemical transformation as a result of any
`subsequent exposure to radiation”,
`2) “dissolution
`by
`solvents
`during
`subsequent spin-on of photoresist”, or
`3) “dissolution by a subsequent developer”.
`
`a
`
`(TSMC-1001, Cleeves at 4:34-42).
`
`Jinbo teaches exposing to patterned first resist to
`a fluorine-containing plasma in order to make it
`insoluble with respect
`to a solvent and a
`developer as disclosed in examples 2 and 3 of the
`’084 Patent, respectively.
`
`Next, oxygen gas and CF4 gas, as a fluorine
`compound gas in which in this case the
`hydrogen in an alkane has been replaced with
`fluorine, are each supplied at a rate of 10
`sccm into the reaction furnace [sic], and a
`
`–24–
`
`TSMC-1009 / Page 24 of 57
`
`
`
`Blanchard Decl.
`
`Inter Partes Review of U.S. 5,652,084
`
`US 5,652,084 (Cleeves)
`Priority Date: Dec. 22, 1994
`
`Claims 1-8, 12, 15, and 16 are anticipated
`under 35 U.S.C. §102(b) by Jinbo.
`
`[1.4] (d) forming a second
`imaging layer over the first
`pattern layer; and
`
`plasma of the aforementioned mixed gas is
`generated in the reaction furnace with the
`pressure of the mixed gas at 50 mTorr and RF
`power at 0.01 W/cm2. By leaving first resist
`pattern 13a in such a gas plasma, first resist
`pattern 13a will demonstrate insolubility
`relative to the solvent and developer for the
`second resist, discussed below, and a first
`resist pattern 13b that has been insolubilized
`is obtained.
`(TSMC-1004, Jinbo at p. 5,
`emphasis added).
`
`Thus, Jinbo teaches stabilizing the first patterned
`layer in the manner recited by claim 1.
`
`[1.4] Jinbo teaches forming a second resist over
`the patterned first resist.
`
`(TSMC-1004, Jinbo, FIG. 1D)
`
`Next, substrate 11 having first resist pattern
`13b which has been insolubilized is spin-
`coated to a thickness of 1.0 µm with TSMR-
`365iR, used as the first resist in this case, as
`second resist 15 (Figure 1 (D)).
`First resist pattern 13b which has been
`insolubilized has been treated as described
`above to be insoluble relative to a solvent for
`second resist 15, so that even though first
`resist pattern 13b is covered by second
`
`–25–
`
`TSMC-1009 / Page 25 of 57
`
`
`
`Blanchard Decl.
`
`Inter Partes Review of U.S. 5,652,084
`
`US 5,652,084 (Cleeves)
`Priority Date: Dec. 22, 1994
`
`Claims 1-8, 12, 15, and 16 are anticipated
`under 35 U.S.C. §102(b) by Jinbo.
`
`resist 15, no destruction
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