Curriculum Vitae
`
`Robert W. Horst, Ph.D.
`
`Expertise
`
`¯ Computer design and architecture
`¯ Fault tolerant computing
`¯ CPU, cache and memory design
`¯
`I/O and storage subsystems
`
`¯ High speed networks
`¯ Performance evaluation
`¯ Hardware testing
`¯ Patents and intellectual property
`
`Professional Summary
`
`From: 2001
`To:
`Present
`Position:
`
`HT Consulting
`San Jose, CA
`Independent consultant
`¯ Work with startups, VC firms, established companies and law
`firms on architectural definition of new products, design reviews,
`technical due diligence on potential investments, identification
`and protection of intellectual property and litigation support.
`¯ Expert witness in patent and technology litigation
`
`From: 2013
`To:
`Present
`Position:
`
`AlterG
`Fremont, CA
`Chief Technology Officer, Robotics
`¯ Tibion was acquired by AlterG in April, 2013.
`¯ Leading development of AlterG Bionic Leg and future products
`
`From: 2001
`To:
`2013
`Position:
`
`Tibion Corporation
`Sunnyvale, CA
`Founder / VP of R&D / CTO
`¯ Inventor of the Tibion Bionic Leg, the first wearable robotic
`device for assistance and rehabilitation of those with impaired
`mobility.
`¯
`Investigate product and technology options
`¯ Develop electronics, software and mechanics for several
`generations of prototypes and products
`¯ Design and test production electronics and control algorithms
`¯ Formulate and execute IP strategy
`
`Resume of Robert W. Horst, Ph.D.
`Printed: 03/03/14
`
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`Curriculum Vitae
`
`From: 2002
`To:
`2003
`Position:
`
`Network Appliance, Inc.
`Sunnyvale, CA
`Technical Director
`¯ Investigate processor and interconnect options for future
`generations of network-attached storage subsystems.
`¯ Represent Network Appliance in the PCI Express Advanced
`Switching working group.
`
`From: 1999
`To:
`2001
`Position:
`
`From: 1980
`To:
`1999
`Position:
`
`3ware, Inc.
`Mountain View, CA
`Vice President, Research & Technology
`¯ Initiate and lead project that resulting in industry’s first Ethernet
`Storage Area Network storage subsystem. Enhance the
`company’s patent position with 10 new patent applications.
`¯ Develop novel disk mirroring architecture and help the company
`to grow from 15 to over 100 people. Participate in fund raising
`activities and prototype development.
`
`Tandem Computers / Compaq Computers
`Cupertino, CA
`Technical Director
`¯ Designer and architect of several generations of fault-tolerant
`mainframes used in banking, stock exchanges, and commerce.
`¯ Co-founder of Tandem Labs. Initiated internal projects and
`started several joint research projects with universities,
`¯ Lead architect of the ServerNet System Area Network. Internal
`and external champion of ServerNet. Wrote technical papers
`and made numerous presentations to technical audiences and
`customers
`¯ Principal architect of the NonStop Cyclone superscalar
`processor. Listed inventor on the industry’s first superscalar
`patents.
`¯ Project leader of NonStop TXP fault-tolerant CPU.
`
`From: 1976
`To:
`1980
`Position:
`
`Hewlett-Packard Co.
`Cupertino, CA
`Development Engineer
`¯ Designed the micro-sequencer and cache of the HP3000 Series
`64 processor.
`¯ Designed a test system for the processor cards using pseudo-
`random scan and signature analysis.
`
`Resume of Robert W. Horst, Ph.D.
`Printed: 03/03/14
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`Curriculum Vitae
`
`Litigation Support Experience
`
`Served as a testifying and consulting expert witness on patent cases related to systems,
`processors and storage. Served as a consulting expert on class-action and defective
`product cases. Further details furnished on request.
`
`Patents
`
`#
`77
`76
`75
`
`74
`
`73
`72
`71
`70
`69
`
`68
`
`67
`66
`65
`
`64
`
`63
`62
`61
`
`60
`
`59
`58
`57
`
`56
`
`55
`54
`
`53
`
`52
`
`51
`
`50
`
`PAT. NO.
`8,639,455
`8,353,854
`8,274,244
`
`8,058,823
`
`7,811,189
`7,648,436
`7,537,573
`7,521,836
`7,484,038
`
`7,468,982
`
`7,365,463
`7,239,065
`6,966,882
`
`6,950,428
`
`6,924,780
`6,775,794
`6,753,878
`
`6,751,757
`
`6,650,533
`6,646,984
`6,631,131
`
`6,591,339
`
`6,591,338
`6,567,892
`
`6,549,977
`
`6,516,032
`
`6,496,940
`
`6,487,633
`
`TITLE
`Foot pad device and method of obtaining weight data
`Methods and devices for moving a body joint
`Actuator system and method for extending a joint
`Actuator system with a multi-motor assembly for extending and
`flexing a joint
`Deflector Assembly
`Rotary Actuator
`Active muscle assistance device and method
`Electrostatic actuator with fault tolerant electrode structure
`Method and apparatus to manage storage devices
`Method and apparatus for cluster interconnection using multi-port
`nodes and multiple routing fabrics
`High torque motor
`Electrostatic actuator with fault tolerant electrode structure
`Active muscle assistance device and method
`System and method for configuring adaptive sets of links between
`routers in a system area network (SAN)
`Spatial display of disk drive activity data
`Use of activity bins to increase the performance of disk arrays
`Parallel pipelined merge engines
`Disk drive data protection using clusters containing error detection
`sectors
`Pluggable drive carrier assembly
`Network topology with asymmetric fabrics
`Transpose table biased arbitration scheme
`Methods and systems for selecting block sizes for use with disk
`arrays
`Methods and systems for mirrored disk arrays
`Use of activity bins to increase the performance of disk arrays
`Use of deferred write completion interrupts to increase the
`performance of disk operations
`First-order difference compression for interleaved image data in a
`high-speed image compositor
`Multiple processor system with standby sparing
`Methods and systems for accessing disks using forward and reverse
`seeks
`
`Resume of Robert W. Horst, Ph.D.
`Printed: 03/03/14
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`Curriculum Vitae
`
`49
`
`48
`47
`
`46
`
`45
`
`44
`
`6,484,235
`
`6,424,655
`6,424,523
`
`6,266,765
`
`6,233,702
`
`6,157,967
`
`43 6,092,177
`
`42 6,009,506
`
`41 5,964,835
`
`40
`
`39
`
`5,930,275
`
`5,918,032
`
`38 5,914,953
`
`37
`
`36
`
`35
`
`34
`
`33
`
`32
`
`31
`
`30
`
`29
`
`28
`
`27
`
`26
`
`25
`
`24
`
`23
`
`5,890,003
`
`5,867,501
`
`5,838,894
`
`5,765,007
`
`5,758,113
`
`5,752,064
`
`5,751,932
`
`5,742,135
`
`5,710,549
`
`5,694,121
`
`5,675,579
`
`5,628,024
`
`5,574,941
`
`5,574,933
`
`5,404,550
`
`Methods and systems for dynamically distributing disk array data
`accesses
`Transpose table-biased arbitration
`Pluggable drive carrier assembly
`Computer architecture capable of execution of general purpose
`multiple instructions
`Self-checked, lock step processor pairs
`Method of data communication flow control in a data processing
`system using busy/ready commands
`Computer architecture capable of execution of general purpose
`multiple instructions
`Computer architecture capable of concurrent issuance and execution
`of general purpose multiple instructions
`Storage access validation to data messages using partial storage
`address data indexed entries containing permissible address range
`validation for message source
`Clock error detection circuit
`Computer architecture capable of concurrent issuance and execution
`of general purpose multiple instructions
`Network message routing using routing table information and
`supplemental enable information for deadlock prevention
`Interrupts between asynchronously operating CPUs in fault tolerant
`computer system
`Encoding for communicating data and commands
`Logical, fail-functional, dual central processor units formed from
`three processor units
`Microinstruction sequencer having multiple control stores for
`loading different rank registers in parallel
`Refresh control for dynamic memory in multiple processor system
`Computer architecture capable of concurrent issuance and execution
`of general purpose multiple instructions
`Fail-fast, fail-functional, fault-tolerant multiprocessor system
`System for maintaining polarity synchronization during AMI data
`transfer
`Routing arbitration for shared resources
`Latency reduction and routing arbitration for network message
`routers
`Method for verifying responses to messages using a barrier message
`Computer architecture capable of concurrent issuance and execution
`of general purpose multiple instructions
`Computer architecture capable of concurrent issuance and execution
`of general purpose multiple instruction
`Task flow computer architecture
`Method and apparatus for executing tasks by following a linked list
`of memory packets
`
`Resume of Robert W. Horst, Ph.D.
`Printed: 03/03/14
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`Curriculum Vitae
`
`22
`
`21
`20
`
`19
`
`5,390,355
`
`5,384,906
`5,353,436
`
`5,329,629
`
`18 5,317,726
`
`17
`
`16
`
`5,287,472
`
`5,239,641
`
`15 5,203,005
`
`14 5,193,175
`
`13
`12
`
`5,146,589
`5,075,844
`
`11 5,072,364
`
`10
`9
`8
`7
`6
`5
`4
`3
`2
`1
`
`5,034,964
`5,016,208
`4,872,109
`4,823,252
`4,800,486
`4,754,396
`4,636,943
`4,618,956
`4,574,344
`4,571,673
`
`Computer architecture capable of concurrent issuance and execution
`of general purpose multiple instructions
`Method and apparatus for synchronizing a plurality of processors
`Method and apparatus for synchronizing a plurality of processors
`Apparatus and method for reading, writing, and refreshing memory
`with direct virtual or physical access
`Multiple-processor computer system with asynchronous execution
`of identical code streams
`Memory system using linear array wafer scale integration
`architecture
`Method and apparatus for synchronizing a plurality of processors
`Cell structure for linear array wafer scale integration architecture
`with capability to open boundary I/O bus without neighbor
`acknowledgement
`Fault-tolerant computer with three independently clocked processors
`asynchronously executing identical code that are synchronized upon
`each voted access to two memory modules
`Refresh control for dynamic memory in multiple processor system
`Paired instruction processor precise exception handling mechanism
`Method and apparatus for recovering from an incorrect branch
`prediction in a processor that executes a family of instructions in
`parallel
`N: 1 time-voltage matrix encoded I/O transmission system
`Deferred comparison multiplier checker
`Enhanced CPU return address stack
`Overlapped control store
`Multiple data patch CPU architecture
`Overlapped control store
`Enhanced CPU microbranching architecture
`Method of operating enhanced alu test hardware
`Entry control store for enhanced CPU pipeline performance
`Enhanced CPU microbranching architecture
`
`Education
`
`1991 University of
`Illinois
`
`Ph.D., Computer Science. Design and simulation of a massively
`parallel, multi-threaded task flow computer.
`
`1978 University of
`Illinois
`
`M.S., Electrical Engineering. Design, construction and debugging
`of a shared memory parallel microprocessor system.
`
`1975 Bradley University B.S., Electrical Engineering. Summa Cure Laude.
`
`Resume of Robert W. Horst, Ph.D.
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`Curriculum Vitae
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`Publications
`
`Bionics
`
`R. Horst, "FlexCVA: A Continuously Variable Actuator for Active Orthotics," Proc.
`28th Annual International Conf. of the IEEE Engineering in Medicine and Biology
`Society, Aug., 2006.
`
`R. Horst, "A Bio-Robotic Leg Orthosis for Rehabilitation and Mobility
`Enhancement," Proc. 31 st Annual International Conf. of the IEEE Engineering in
`Medicine and Biology Society, Sept, 2009.
`
`J. Vose,; A. McCarthy, E. Tacdol, R. Horst., "Optimization of Lower Extremity
`Kinetics During Transfers Using a Wearable, Portable Robotic Lower Extremity
`Orthosis: a Case Study," Int’l Conf. NeuroRehabilitation, Toledo, Spain, Nov. 14-16,
`2012.
`
`J. Vose,; A. McCarthy, E. Tacdol, R. Horst., "Modification of Lower Extremity
`Kinetic Symmetry During Sit-to-Stand Transfers Using a Robotic Leg Orthosis with
`Individuals Post-Stroke," Int’l Conf. NeuroRehabilitation, Toledo, Spain, Nov. 14-16,
`2012.
`
`Fault Tolerance
`
`R. Horst, "Reliable Design of High-speed Cache and Control Store Memories," Proc.
`19th Int. Symp. Fault-Tolerant Computing, June 1989.
`
`J. Bartlett, W. Bartlett, R. Carr, D. Garcia, J. Gray, R. Horst, R. Jardine, et al., "Fault
`Tolerance in Tandem Computer Systems," in Reliable Computer Systems, D. P.
`Siewiorek and R. S. Swarz, Eds., Bedford, MA: Digital Press, 1992.
`
`R. Horst, D. Jewett, D. Lenoski, "The Risk of Data Corruption in Microprocessor-based
`Systems," Proc. 23rd International Symposium on Fault-tolerant Computing, June 1993.
`
`R. Horst, "Massively Parallel Systems You Can Trust," COMPCON Digest of Papers,
`San Francisco, CA, Feb. 28-March 4, 1994.
`
`W. E. Baker, et al., "A Flexible ServerNet-based Fault-Tolerant Architecture," in Proc.
`25th Int. Symp. Fault-Tolerant Computing, Pasadena, CA, June 27-30 1995.
`
`CPU Architecture
`
`R. Horst, "A Linear-Array WSI Architecture for Improved Yield and Performance," in
`Proc. Int. Conf. WSI, San Francisco, CA, pp. 85-91, Jan. 1990.
`
`Resume of Robert W. Horst, Ph.D.
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`Curriculum Vitae
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`R. Horst, "Task Flow Computer Architecture," in Proc. Int. Conf. Parallel Processing,
`Vol. I, pp. 533-540, Aug. 1990.
`
`R. Horst, "Task Flow: A Novel Approach to Fine-grain Wafer-scale Parallel Computing,"
`Coordinated Science Lab. Report CRHC-91-15, University of Illinois, April 1991.
`
`R. Horst, R. Harris, and R. Jardine, "Multiple Instruction Issue in the NonStop Cyclone
`Processor," in Proc. 17th Int. Symp. Computer Architecture, May 1990.
`
`R. W. Horst, "Task-Flow Architecture for WSI Parallel Processing," Computer, vol. 25,
`no. 4, pp. 10-18, April 1992.
`
`Storage
`
`J. Gray, B. Horst, and M. Walker, "Parity striping of disk arrays: Low cost reliable
`storage with acceptable throughput," in Proc. 16th Int. Conf. on Very Large Databases,
`Brisbane, Australia, pp. 148-161, Aug. 1990.
`
`R. Horst, J. McDonald, B. Alessi, "Beyond RAID: An Architecture for Improving PC
`Fault Tolerance and Performance, Digest of Fast Abstracts, 29th Int. Symp. Fault-
`Tolerant Computing, June 1999.
`
`R. Horst, "TwinStor Technology: A Compelling Case for Multiple Drives in PCs, Servers
`and Workstations," 3ware Technical Report TR-1999-2, 3ware, Inc., August 1999.
`
`L. Chung, J. Gray, B. Worthington, R. Horst, "Study of Random and Sequential IO on
`Windows 2000TM’’, http://research.microsoft.corn!BARC/Sequential_IO/.
`
`R. Horst, "Storage Networking: The Killer Application for Gigabit Ethernet," dmDirect
`Business Intelligence Newsletter, http://www.dmreview.com. April 20, 2001.
`
`R. Horst, "IP Storage and the CPU Consumption Myth," proc. IEEE International
`Symposium on Network Computing and Applications (NCA2001), October 2001.
`
`Networks
`
`R. Horst, "TNet: A Reliable System Area Network," IEEE Micro, vol. 15, no. 1, pp. 37-
`45, February 1994.
`
`R. Horst, "ServerNet Deadlock Avoidance and Fractahedral Topologies," in Proc. 10th
`Int’l Parallel Processing Symposium, Honolulu, Hawaii, pp. 274-280, 1995.
`
`R. Horst and D. Garcia, "ServerNet SAN I/O Architecture," Proc. Hot Interconnects V,
`August 1997.
`
`Resume of Robert W. Horst, Ph.D.
`Printed: 03/03/14
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`Curriculum Vitae
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`R. Horst, "A Fault Model for System Area Networks," FTCS-28 Fast Abstract, June
`1998.
`
`D.R Avresky, V. Shurbanov, R. Horst, "The effect of router arbitration policy on
`scalability of ServerNet Topologies," Microprocessors and Microsystems 21, pp 545-561,
`1998.
`
`D.R Avresky, V. Shurbanov, R. Horst, W. Watson, L. Young, D. Jewett. "Performance
`Modeling of ServerNet SAN Topologies," Journal of Supercomputing, V. 14, pp. 19-37,
`1999.
`
`D.R Avresky, V. Shurbanov, R. Horst, "Optimizing router arbitration in point-to-point
`networks," Computer Communications, 22, pp 608-620, 1999.
`
`D.R Avresky, V. Shurbanov, R. Wilkinson, R. Horst, W. Watson, L. Young, "Maximum
`delivery time and hot spots in ServerNet topologies, Computer Networks 31, pp. 1891-
`1910, 1999.
`
`A. Hossain, S. Kang, R. Horst, "ServerNet and ATM Interconnects: Comparison for
`Compressed Video Transmission," Journal of Communications and Networks, V. 1 No.
`2, June 1999.
`
`Professional Associations and Achievements
`
`IEEE Fellow. Elected "for contributions to the architecture and design of fault tolerant
`systems and networks," 2001
`
`Compaq Key Patent Award for patent 5,751,932 - Fail-fast, fail-functional, fault-tolerant
`multiprocessor system, 2002.
`
`Distinguished Alumni Award for "Pioneering Contributions to Fault-tolerant Computer
`Architecture," University of Illinois department of Electrical and Computer Engineering,
`1998.
`
`2013 IEEE/IFR Invention & Entrepreneurship Award. Cited for "A breakthrough
`product for rehabilitation of stroke patients at an affordable price, and offering a
`compelling story of an entrepreneurial journey with typical ups-and-downs culminating
`in a successful business"
`
`Daniel A. Slotnick Award for Most Original Paper, ICPP, 1990
`
`Program Committees: Int. Symposium on Fault Tolerant Computing (FTCS) 1991, 1997,
`1999. Dependable Systems and Networks (DSN 2002). Int. Symposium on Network
`Computing and Applications (NCA) 2001, 2003, IEEE Workshop on Fault-Tolerant
`
`Resume of Robert W. Horst, Ph.D.
`Printed: 03/03/14
`
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`Curriculum Vitae
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`Parallel, Distributed and Network-Centric Systems 2004, Workshop on System Area
`Networks 2004.
`
`Tibion Awards:
`2005 Grand Prize Winner, Boomer Business Plan Competition.
`2008 Silicon Valley Emerging Technology Award (ETA) for Medical Devices
`2010 Medical Design Excellence Award (MDEA)
`
`Resume of Robert W. Horst, Ph.D.
`Printed: 03/03/14
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`Page 9
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