Trials@uspto.gov
`571-272-7822
`
`Paper 60
`Entered: February 19, 2014
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________
`
`SYNOPSYS, INC.
`Petitioner
`v.
`MENTOR GRAPHICS CORPORATION
`Patent Owner
`____________________
`
`Case IPR2012-00042
`Patent 6,240,376 B1
`___________________
`
`Before HOWARD B. BLANKENSHIP, SALLY C. MEDLEY, and
`JENNIFER S. BISK, Administrative Patent Judges.
`
`BISK, Administrative Patent Judge.
`
`CFK>I SNFPPBK AB@FOFLK
`
`.0 J)H)7) h .,3%N& N[Q .2 7);)G) h /-)2.
`
`m m f RRRX q R
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`
`571-272-7822
`
`Paper 60
`Entered: February 19, 2014
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________
`
`SYNOPSYS, INC.
`Petitioner
`v.
`MENTOR GRAPHICS CORPORATION
`Patent Owner
`____________________
`
`Case IPR2012-00042
`Patent 6,240,376 B1
`___________________
`
`Before HOWARD B. BLANKENSHIP, SALLY C. MEDLEY, and
`JENNIFER S. BISK, Administrative Patent Judges.
`
`BISK, Administrative Patent Judge.
`
`CFK>I SNFPPBK AB@FOFLK
`
`.0 J)H)7) h .,3%N& N[Q .2 7);)G) h /-)2.
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`Case IPR2012-00042
`Patent 6,240,376 B1
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`I.
`
`INTRODUCTION
`A. Background
`Petitioner, Synopsys) Fg\+ ’xSynopsysy() _be^] Z i^mbmbhg hg
`September 26, 2012, for inter partes review of claims 1-15 and 20-33 of
`Q+O+ MZm^gm Kh+ 3)/1-)043 ?. ’xma^ {043 MZm^gmy( pursuant to 35 U.S.C. §§
`311-319+ MZi^k . ’xM^m+y(+ MZm^gm Lpg^k) J^gmhk DkZiab\l @hkihkZmbhg
`’xJ^gmhk DkZiab\ly(, filed a preliminary response on December 28, 2012.
`
`MZi^k .2 ’xMk^ebf+ N^li+y(+ Lg C^[knZkr //) /-.0) ma^ ?hZk] ]^gb^] ma^
`petition as to claims 10, 12-15, 20-27, and 30-33, and instituted trial for
`claims 1-9, 11, 28, and 29, on one ground of unpatentability, anticipation by
`
`Q+O+ MZm^gm Kh+ 3).0/).-6 ’xDk^‘hkry( ’Bq+ .--4(+ MZi^k .3 ’xA^\blbhg mh
`
`Fglmbmnm^y(+
`After institution of trial, Mentor Graphics filed a patent owner
`
`k^lihgl^+ MZi^k /5 ’xML N^li+y(+ J^gmhk DkZiab\l Zelh _be^] Z ln[lmbmnm^
`motion to amend claims by submitting proposed new claims 34-43 for
`claims 1, 5, 28, 2, 3, 6, 8, 6) ..) Zg] /6) k^li^\mbo^er+ MZi^k 0. ’xJhm+ mh
`>f^g]y(+ Synopsys filed a reply to the patent owner response (Paper 36;
`xN^iery() Zg] Zelh Zg hiihlbmbhg mh Mentor Graphb\l{l motion to amend
`
`’MZi^k 028 xLii+y(+ J^gmhk DkZiab\l ma^g _be^] Z k^ier bg lniihkm h_ bml
`
`fhmbhg mh Zf^g]+ MZi^k 06 ’xN^ier Jhm+ mh >f^g]y(+
`In preparation for oral hearing, both parties filed and fully briefed
`motions to exclude. MZi^k 1/ ’xMentor Graphb\l{l Motion to Eq\en]^y(8
`MZi^k 11 ’xOrghilrl{l Motion to Eq\en]^y(+ LkZe a^Zkbg‘ pZl a^e]
`
`Kho^f[^k .1) /-.0+ MZi^k 26 ’xPkZgl\kbimy(+
`The Board has jurisdiction under 35 U.S.C. § 6(c). This final written
`decision is issued pursuant to 35 U.S.C. § 318(a) and 37 C.F.R. § 42.73.
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`Synopsys has shown that claims 5, 8, and 9 are unpatentable.
`Synopsys, however, has not met its burden to show by a preponderance of
`the evidence that claims 1-4, 6, 7, 11, 28, and 29 are unpatentable.
`Mentor Graphb\l{s motion to amend claims is denied.
`B. IUR l376 Patent
`
`Pa^ {043 iZm^gm ‘^g^kZeer k^eZm^l mh ma^ _b^e]l h_ lbfneZmbhg Zg]
`prototyping of integrated circuits. Ex. 1001, col. 1, ll. 10-11. In particular,
`
`ma^ iZm^gm ]^l\kb[^l x]^[n‘‘bg‘ lrgma^lbsZ[e^ \h]^ Zm ma^ k^‘blm^k mkZgl_^k
`level during gate-level simulatihg+y Id. at ll. 11-13.
`As described in the Background of the Invention, integrated circuit
`design begins with a description of the behavior desired in a hardware
`
`]^l\kbimbhg eZg‘nZ‘^ ’xEAIy( ln\a Zl R^kr Eb‘a Oi^^] Fgm^‘kZm^] @bk\nbm
`Description Languag^ ’xREAIy(+ Id. at ll. 14-25. A subset of HDL source
`\h]^ bl k^_^kk^] mh Zl N^‘blm^k PkZgl_^k I^o^e ’xNPIy( lhnk\^ \h]^+ Id. at
`ll. 28-30. This RTL source code can be simulated using software, which
`typically offers robust debugging functionality for analyzing and verifying
`the design, including navigating the design hierarchy, viewing the RTL
`source code, setting breakpoints on a statement of RTL source code to stop
`the simulation, and viewing and tracing variables and signal values. Id. at
`ll. 44-54. However, although flexible, software RTL simulators are slow
`compared with hardware emulation. Id. at ll. 55-63. Thus, it often is
`desirable to use gate-level simulation to verify complex designs. Id.
`The RTL description of a circuit can be used by synthesis tools to
`‘^g^kZm^ Z x‘Zm^-e^o^e g^meblm)y pab\a, in turn, can be converted to a format
`suitable for programming a hardware emulator. Id. at ll. 35-42. A gate-level
`netlist represents the circuit to be simulated and ultimately is comprised of
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`combinatorial or sequential logic gates (e.g. AND, NAND, and NOR gates,
`or flip-flops and latches) and a description of their interconnections using
`signals (signals are also referred to as nets). Id. at col. 4, ll. 5-17. As
`discussed, gate-level simulation is useful for validation of a circuit design.
`Id. at col. 1, ll. 55-67. However, one disadvantage of gate-level simulation
`is that much of the high-level information from the RTL source code is lost
`during synthesis, resulting in debugging functionality that is limited severely
`in comparison with that available in software RTL simulation. Id. at col. 2,
`ll. 1-23.
`
`Pa^ {043 iZm^gm ]^l\kb[^l Z f^mah] h_ lrgma^lbsbg‘ NPI lhnk\^ \h]^
`such that the resulting gate-level simulation can support the traditional
`debugging tools of setting breakpoints, mapping signal values to particular
`source code lines, and stepping through the source code to trace variable
`values. Id. at ll. 1-30. The Summary of the Invention describes facilitating
`debugging during gate-e^o^e lbfneZmbhg [r7 ’.( ‘^g^kZmbg‘ xbglmknf^gmZmbhg
`logic indicative of the execution status of at least one synthesizable
`lmZm^f^gm pbmabg ma^ NPI lhnk\^ \h]^y8 ’/( ‘^g^kZmbg‘ Z ‘Zm^-level netlist
`from the RTL source code; and (3) during simulation, evaluating the
`instrumentation logic of the gate-level netlist to enable RTL debugging. Id.
`at ll. 26-39.
`Pa^ {043 iZm^gm ]^l\kb[^l mwo main embodiments for implementing
`this method. The first embodiment modifies the gate-level netlist to provide
`
`bglmknf^gmZmbhg lb‘gZel xbfie^f^gmbg‘ ma^ bglmknf^gmZmbhg eh‘b\ Zg]
`\hkk^lihg]bg‘ mh lrgma^lbsZ[e^ lmZm^f^gml pbmabg ma^ NPI lhnk\^ \h]^+y Id.
`at ll. 40-43. This modification of the gate-level netlist can be done either by
`modifying the RTL source code directly or by generating the modified gate-
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`level netlist during synthesis. Id. at ll. 43-46. The second embodiment ’xma^
`cross-k^_^k^g\^ ^f[h]bf^gmy( describes storing the instrumentation signals
`in a cross-reference database instead of modifying the gate-level netlist. Id.
`at ll. 47-52.
`
`Cb‘nk^ / h_ ma^ {043 iZm^gm) k^ikh]n\^] [^ehp) beenlmkZm^l xhg^
`embodiment of the instrumentation process in which instrumentation is
`bgm^‘kZm^] pbma ma^ lrgma^lbl ikh\^ll+y Id. at col. 5, ll. 9-11.
`
`Figure 2, above, shows that RTL source code 210 is provided to synthesis
`process 220, which includes instrumentation step 234 followed by synthesis
`step 240. Id. at ll. 11-16. In the first embodiment, in which the gate level
`netlist is modified to include instrumentation signals, the resulting gate-level
`
`]^lb‘g /2- x\hgmZbgl Z]]bmbhgZe eh‘b\ mh \k^Zm^ ma^ Z]]bmbhgZe bglmknf^gmZmbhg
`output signals referenced in instrumentation data 238+y Id. at ll. 17-30.
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`Instrumentation data 238 is implemented as gates that can then be simulated.
`Id. at col. 6, ll. 32-37.
`In the cross-reference ^f[h]bf^gm) xma^ NPI lhnk\^ \h]^ bl ZgZers^]
`to generate a cross-reference database as instrumentation data 238 without
`modifying the gate-e^o^e ]^lb‘g+y Id. at col. 5, ll. 31-33. In this
`^f[h]bf^gm) x[t]he instrumentation data 238 is likely to contain
`\hglb]^kZ[er fhk^ \hfie^q eh‘b\ mh ^oZenZm^ ]nkbg‘ lbfneZmbhg+y Id. at
`ll. 42-45.
`Pa^ {076 patent describes tradeoffs between the two main
`embodiments. Id. at l. 45. For example, the first embodiment reduces the
`complexity of the logic to be evaluated during simulation, resulting in faster
`simulation time. Id. at ll. 46-64. However, because the gate-level design
`used during simulation is modified to accommodate the debugging logic, the
`design actually used for production will differ from that used during
`simulation, and, thus, the simulation may not reproduce accurately the
`production behavior of the circuit. Id. On the other hand, the cross-
`reference embodiment typically results in greater complexity of
`instrumentation logic to evaluate during simulation, resulting in longer
`simulation time. Id. at ll. 65-67. In addition, some of the evaluation may be
`performed by software, instead of hardware, eliminating direct verification
`of the target system through in-situ verification. Id. at col. 5, l. 65 v col. 6,
`l. 11. However, the technique does not affect the original gate-level design,
`and the instrumentation data can be eliminated after testing without
`disrupting the gate-level design. Id. Because of these various tradeoffs, the
`{076 patent mentions generally, but does not describe in detail, alternate
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`embodiments that combine the two main ^f[h]bf^gml xbg hk]^k mh mkZ]^ h__
`lbfneZmbhg li^^]) ]^glbmr) Zg] o^kb_b\Zmbhg Z\\nkZ\r+y Id. at col. 6, ll. 17-22.
`Pa^ {043 iZm^gm ln[l^jn^gmer ]^l\kb[^l (in Figures 3, 12, and 17 and
`the related text) three methods of modifying the gate-level netlist. Id. at
`col. 13, ll. 38-40. As described when discussing the first embodiment above,
`ma^ {043 iZm^gm ]bl\ehl^l maZm ma^l^ three methods can be applied either by
`modifying the RTL source code directly by applying the method to the
`source code before it is synthesized independently of the synthesis process
`(id. at ll. 55-59), as shown in Figures 3, 12, and 17, or they can be integrated
`into the synthesis tool so that actual modification of the RTL source code is
`not required (id. at ll. 60-67).
`Figure 3, reproduced below, illustrates a method of modifying RTL
`source code for sequential statements that depend only on the value of the
`inputs and can be synthesized to logic networks of combinatorial gates and
`eZm\a^l ’xe^o^e-sensitive RTL source cod^y(+ Id. at col. 7, ll. 13-22, 40-43.
`
`Figure 3, above, shows a method in which a unique local variable is
`created for each list of adjacent sequential statements in step 310, each of
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`these variables is initialized to zero in step 320, and one unique variable
`assignment statement is inserted into each list of adjacent sequential
`statements corresponding to an executable branch in step 330. Id. at ll. 40-
`50. At the end of the process, all the unique local variables are assigned to
`global signals in step 340. Id. at ll. 50-54.
`Figure 12, reproduced below, illustrates a method of modifying RTL
`source code having references to signal events, typically used to describe
`edge-sensitive devices such as flip-flops. Id. at col. 9, ll. 27-32, 63-64.
`
`The method shown in Figure 12, above, begins with step 1210, in
`which every signal whose state transition serves as the basis for the
`determination of another signal is sampled. Id. at ll. 63-67. An
`instrumentation signal event is generated in step 1220, and every process
`that references a signal event is duplicated in step 1230. Id. at col. 9, l. 67 v
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`col. 10, l. 7. In step 1240 each list of sequential statements within the
`duplicate version of the code is replaced by a unique local variable
`assignment. In step 1250, each time a signal event is referenced in the
`duplicated version of the code, it is replaced by the sampled signal event
`computed in step 1210. Id. at col. 10, ll. 7-12. Finally, the RTL source code
`is synthesized, in step 1260, to generate gate-level logic, including the
`instrumentation signals. Id. at ll. 12-14.
`Figure 17, reproduced below, illustrates a method of modifying RTL
`source code for processes themselves for subsequent determination of
`whether the process is active during gate-level simulation. Id. at col. 11,
`ll. 43-46.
`
`Figure 17, above, shows a method in which the sensitivity list of a
`process is identified in step 1710, logic is generated to compare the signals
`in the sensitivity list between consecutive simulation cycles in step 1720,
`and during gate-level simulation in step 1730, a determination is made as to
`whether an event has occurred on any of the sensitivity list signals. Id. at
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`ll. 48-53. If the signal indicates a difference during a simulation cycle, as
`indicated by step 1740, the process is active; otherwise, the process is
`inactive, as indicated by step 1750. Id. at ll. 53-58.
`C. Illustrative Claims
`Three of the claims involved in this proceeding, claims 1, 5, and 28,
`are independent. All three are reproduced below:
`1. A method comprising the steps of:
`a) identifying at least one statement within a register
`transfer level (RTL) synthesizable source code; and
`b) synthesizing the source code into a gate-level netlist
`including at least one instrumentation signal, wherein the
`instrumentation signal is indicative of an execution status
`of the at least one statement.
`
`5. A method of generating a gate level design, comprising the
`steps of:
`a) creating an instrumentation signal associated with at least
`one synthesizable statement contained in a register
`transfer level (RTL) synthesizable source code; and
`b) synthesizing the source code into a gate-level design
`having the instrumentation signal.
`
`28. A storage medium having stored therein processor
`executable instructions for generating a gate-level design from a
`register transfer level (RTL) synthesizable source code, wherein
`when executed the instructions enable the processor to
`synthesize the source code into a gate-level netlist including at
`least one instrumentation signal, wherein the instrumentation
`signal is indicative of an execution status of at least one
`synthesizable statement of the source code.
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`II. ANALYSIS
`A. 35 U.S.C. § 315(b)
`As a threshold issue, Mentor Graphics argues that this proceeding is
`barred by virtue of the relationship between Synopsys and the companies of
`Synopsys Emulation and Verification, S.A. and EVE-USA, Inc. (collectively
`xBRBy(+ ML N^li+ /-22. Mentor Graphics bases these arguments on the
`following facts.
`In\ ?nk‘ng) Z gZf^] bgo^gmhk h_ ma^ {076 patent, was, at one time, a
`Mentor Graphics employee. PO Resp. 3 (citing Ex. 2028: Ex. 5 at 1-4.1
`
`?nk‘ng Zllb‘g^] Zee kb‘aml bg ma^ bgo^gmbhg \eZbf^] bg ma^ {043 iZm^gm mh
`Mentor Graphics. Id. (citing Ex. 2029: Ex. 2 at 3). Subsequently, Burgun
`left Mentor Graphics and went to work for EVE. Id. In 2006, Mentor
`Graphics filed suit against EVE in the United States District Court for the
`District of Oregon, Zee^‘bg‘ maZm BRB{l V^?n ^fneZmhkl bg_kbg‘^] ma^ {043
`patent. Id. at 4 (citing Ex. 2001); Mentor Graphics Corp. v. EVE-USA, Inc.,
`06-341-AA (D. Or. 2006). That case was dismissed with prejudice pursuant
`to a settlement agreement. Ex. 2003. Shortly after filing the petition in the
`present case, EVE and Synopsys jointly filed a declaratory judgment action
`in the United States District Court for the Northern District of California,
`seeking a ruling of non-bg_kbg‘^f^gm Zg] bgoZeb]bmr h_ ma^ {043 iZm^gm. Ex.
`2004. The complaint states that x[o]n September 27, 2012, Synopsys, Inc.
`entered into an agreement mh Z\jnbk^ ma^ [nlbg^ll h_ BRB)y which
`acquisition xis expected to close in the immediate future.y Id. at ¶ 13.
`
`1 Exhibits 2028 and 2029 are large exhibits, not paginated consecutively,
`including many non-sequentially numbered Exhibits. Throughout this
`A^\blbhg) \bmZmbhgl mh ma^l^ ^qab[bml pbee [^ h_ ma^ _hkf xBq+ /-/W5 hk 6X7
`WBq+ $ pbmabg Bq+ /-/T Zm iZ‘^ gnf[^k h_ maZm Bq+ $X+y
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`Mentor Graphics contends that the acquisition took place on October 4,
`2012. PO Resp. 4-5 (citing Ex. 2029: Ex. 34 at 20).
`1. Privity
`Mentor Graphics argues that this inter partes review is barred because
`Synopsys and EVE were in privity at the time of the Decision to Institute.
`Id. at 6-7. Mentor Graphics asserts that based on this relationship the
`complaint served on EVE in the May 2006 case should trigger § 315(b). Id.
`at 6. We disagree with Mentor Graphb\l{s contentions.
`35 U.S.C. § 315(b) states as follows:
`An inter partes review may not be instituted if the
`petition requesting the proceeding is filed more than 1 year after
`the date on which the petitioner, real party in interest, or privy
`of the petitioner is served with a complaint alleging
`infringement of the patent. The time limitation set forth in the
`preceding sentence shall not apply to a request for joinder under
`subsection (c).
`
`The Office promulgated a rule interpreting § 315(b), 37 C.F.R.
`§ 42.101(b), which states that:
`A person who is not the owner of a patent may file with the
`Office a petition to institute an inter partes review of the patent
`unless:
`. . .
`(b) The petition requesting the proceeding is filed more than
`one year after the date on which the petitioner, the petitioner{s
`real party-in-interest, or a privy of the petitioner is served with a
`complaint alleging infringement of the patent.
`
`This rule makes clear that it is only privity relationships up until the time a
`petition is filed that matter; any later-acquired privies are irrelevant.
`
`Cnkma^kfhk^) ikbobmr bl Z x_e^qb[e^ Zg] ^jnbmZ[e^y ]h\mkbg^ khhm^] bg
`common law. Office Patent Trial Practice Guide, 77 Fed. Reg. 48,756,
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`48,759 (Aug. 14, 2012). Consistent with this doctrine, we also take into
`consideration the nature of the relationship between the parties at the time
`that the statutorily-referenced complaint was served. See, e.g., Taylor v.
`Sturgell) 220 Q+O+ 55-) 56/ ’/--5( ’x> i^klhg pah pZl ghm a party to a suit
`
`‘^g^kZeer aZl ghm aZ] Z z_nee Zg] _Zbk hiihkmngbmr mh ebmb‘Zm^{ ma^ \eZbfl Zg]
`blln^l l^mme^] bg maZm lnbm+y(8 Mars Inc. v. Nippon Conlux Kabushiki-Kaisha,
`58 F.3d 616, 619 (Fed. Cir. 1995) (applying res judicata to parent
`corporation because it controlled wholly-owned subsidiary during prior
`litigation). Mentor Graphics has not alleged that Synopsys was a privy of
`EVE in 2006 when EVE was served with a complaint alleging infringement
`
`h_ ma^ {043 iZm^gm+ Panl) ma^k^ bl gh \hgm^gmbhg maZm Orghilrl aZ] Zgr
`control of this previous suit or even had notice of it, along with an
`opportunity to participate while it was still pending. See Richards v.
`Jefferson Cnty., Ala., 517 U.S. 793 (1996) (holding no estoppel where
`subsequent plaintiffs were not provided notice of first suit nor adequately
`represented in it). Thus, this lack of relationship between Synopsys and
`EVE in the 2006 litigation is another reason to conclude that there was no
`privity relationship between Synopsys and EVE sufficient to trigger
`§ 0.2’[({l ikhab[bmbhgl+
`
`Jhk^ho^k) gh k^\hk] ^ob]^g\^ ln‘‘^lml maZm Orghilrl{l i^mbmbhg _hk
`review was timed to inject delay into an already-pending litigation and, thus,
`this case does not implicate the concerns that this statute appears designed to
`address. H.R. REP. NO. 112-65) Zm 12 ’/-..( ’^qieZbgbg‘ t 0.2’[( Zl xTime
`limits during litigation. Parties who want to use inter partes review during
`litigation are required to seek a proceeding within 12 months of being served
`with a complaint alleging infringement of the patent.y(8 .24 CONG. REC.
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`S1326 (daily ed. Mar. 7, /-..( ’lmZm^f^gm h_ O^g+ O^llbhgl( ’xPa^ [bee Zelh
`includes many protections that were long sought by inventors and patent
`owners . . . . It imposes time limits on starting an inter partes or post-grant
`review when litigation is pending . . . . All of these reforms will help to
`ensure that post-grant review operates fairly and is not used for purposes of
`
`aZkZllf^gm hk ]^eZr+y ’^fiaZlbl Z]]^]((+
`Thus, we conclude that there was no privity relationship between
`Orghilrl Zg] BRB ln__b\b^gm mh mkb‘‘^k t 0.2’[({l ikhab[bmbhgl, and we
`decline to dismiss the inter partes review on this basis.
`2. Real Party-in-interest
`Mentor Graphics argues that this inter partes review is barred because
`EVE is a real party-in-interest to this inter partes review. PO Resp. 7-14.
`Mentor Graphics asserts that, therefore, the complaint served on EVE in the
`May 2006 case should trigger § 315(b). Id. at 6. Mentor Graphics admits
`maZm xhg ma^ ]Zm^ ma^ i^mbmbhg _hk mabl Winter partes review] was filed,
`Synopsys had not yet acquired EVE and therefore had at best merely a
`ikhli^\mbo^ bgm^k^lm bg ma^ V^?n ikh]n\ml+y Id. at 9. Mentor Graphics,
`however, asserts that because Synopsys had a prospective interest in
`
`bgoZeb]Zmbg‘ ma^ {043 iZm^gm pa^g ma^ i^mbmbhg pZl _be^]) xOrghilrl pZl
`acting as Zg Z‘^gm _hk ma^ [^g^_bm h_ BRB+y Id. at 10. Thus, according to
`Mentor Graphics, at the time of filing, Synopsys was a third-party
`beneficiary for whose benefit the action was brought and, therefore, a real
`party-in-interest. Id. at 7-10.
`Mentor Graphics also contends that Synopsys allowed EVE to direct
`or control content of the petition for this inter partes review because
`Synopsys (1) specifically acquired EVE because of its expertise in the
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`m^\agheh‘r _b^e] mh pab\a ma^ {043 iZm^gm bl ]bk^\m^]8 ’/( chbgmer Zll^km^]
`with EVE the same non-infringement and invalidity claims and defenses
`pbma k^li^\m mh ma^ {043 iZm^gm) nlbg‘ ma^ lZf^ \hngl^e) bg ma^ chbgmer-filed
`declaratory judgment litigation; and (3) planned and coordinated the timing
`of the filing of the petition in this case and the declaratory judgment
`complaint with EVE. PO Resp. 12-13. Based on these contentions, Mentor
`
`DkZiab\l Zll^kml maZm Orghilrl Zg] BRB x\hglibk^] mh‘^ma^k mh \hg\^Ze
`BRB{l lmZmnl Zl Z zk^Ze iZkmr-in-bgm^k^lm{ mh \bk\nfo^gm Zg] mapZkm ma^
`statutory estoppel provisions+y Id. at 14.
`As discussed above, 37 C.F.R. § 42.101(b) makes clear that it is only
`relationships up until the time a petition is filed that matter. Mentor
`Graphics does not point to persuasive evidence to support its assertions that
`Synopsys allowed EVE to direct or control content of the petition filed in
`this case or any other evidence that EVE was a real party-in-interest prior to
`the filing of the petition. Although Mentor Graphics filed a Motion for
`Additional Discovery on the topic of real party-in-interest (Paper 21), this
`motion was denied because it did not articulate clearly why such discovery
`pZl xnecessary bg ma^ bgm^k^lm h_ cnlmb\^y Zl k^jnbk^] [r 02 Q+O+@+
`§ 316(a)(5) (Paper 24). In fact, the entirety of Mentor Graphb\l{l
`explanation of why it needed additional discovery on the subject of real
`party-in-interest was the following:
`Thus, while the request interest of justice, [sic] as required by
`37 C.F.R. § 42.51(b)(2), in order to allow the Patent Owner an
`opportunity to show the applicability of a § 315(b) bar under
`the legal standard adopted by the Board. This includes the
`opportunity to show further (1) . . . (4) the status of EVE as a
`real party-in-interest to this IPR.
`
`Paper 21 at 2-3.
`
`15
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`Case IPR2012-00042
`Patent 6,240,376 B1
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`Thus, because Mentor Graphics has not supported sufficiently its
`assertions that EVE was a real party-in-interest at the time the petition in this
`case was filed, we decline to dismiss the inter partes review on this basis.
`B. Assignor Estoppel
`Mentor Graphics argues that Synopsys is barred from challenging the
`oZeb]bmr h_ ma^ {043 iZm^gm [r Zllb‘ghk ^lmhii^e+ ML N^li+ .1-22. The
`Board has determined previously, and we agree, that assignor estoppel is not
`a basis for denying a petition requesting inter partes review:
`Qg]^k ma^ >F>) xZ i^klhg who is not the owner of a
`patent may file with the Office a petition to institute an inter
`iZkm^l k^ob^p h_ ma^ iZm^gm+y 35 U.S.C. § 311(a) (emphasis
`added). Consequently, under the statute, an assignor of a
`patent, who is no longer an owner of the patent at the time of
`filing, may file a petition requesting inter partes review. This
`lmZmnm^ ik^l^gml Z \e^Zk ^qik^llbhg h_ @hg‘k^ll{l [khZ] ‘kZgm h_
`the ability to challenge the patentability of patents through inter
`partes review.
`
`Athena Automation Ltd. v. Husky Injection Molding Sys. Ltd., IPR2013-
`00290, slip op. at 12-13 (PTAB Oct. 25, 2013), Paper No. 18; see also Palo
`Alto Networks, Inc. v. Juniper Networks, Inc., IPR2013-00369, slip op. at
`11-14 (PTAB Dec. 19, 2013), Paper No. 16.
`Mentor Graphics further asserts that even if Synopsys is not barred
`from requesting inter partes review, the Board should exercise its discretion
`to dismiss this inter partes review because of the relationship between Mr.
`Burgun and Synopsys.2 PO Resp. 16-19. Mentor Graphics further argues,
`
`2 This case does not require us to reach the issue of whether Mr. Burgun is in
`privity with Synopsys, as asserted by Mentor Graphics (PO Resp. 16-19),
`because we conclude that even if Mentor Graphics established such a
`relationship, Mentor Graphics has not shown a sufficient basis to bar
`
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`Case IPR2012-00042
`Patent 6,240,376 B1
`
`more generally, that equitable considerations weigh against granting the
`petition, including that Synopsys is in privity with EVE and shares personnel
`with EVE, including Mr. Burgun. Id. at 19. Moreover, according to Mentor
`
`DkZiab\l) xWbXm phne] [^ paheer Z‘Zbglm ma^ ikbg\bie^l h_ Zllb‘ghk ^lmhii^e mh
`allow Synopsys to receive the benefit of the acquisition of EVE, but avoid
`BRB{l ^jnbmZ[e^ h[eb‘Zmbhgl+y Id. at 22.
`We are not persuaded, however, that the equitable doctrine of assignor
`estoppel provides an exception to the statutory mandate that any person who
`is not the owner of a patent may file a petition for inter partes review.
`Accordingly, we decline to dismiss the inter partes review based on Mentor
`Graphb\l{s estoppel arguments.
`C. Claim Construction
`In an inter partes review, claim terms in an unexpired patent are
`interpreted according to their broadest reasonable construction in light of the
`specification of the patent in which they appear. 37 C.F.R. § 100(b); Office
`Patent Trial Practice Guide, 77 Fed. Reg. 48,756, 48,766 (Aug. 14, 2012).
`Claim terms are also given their ordinary and customary meaning, as would
`be understood by one of ordinary skill in the art in the context of the entire
`disclosure. In re Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir.
`2007).
`If an inventor acts as his or her own lexicographer, the definition must
`be set forth in the specification with reasonable clarity, deliberateness, and
`precision. RenV‘UNd EA7 c) BN_]\‘‘ H\PVRaNl ]R_ 5gV\[V, 158 F.3d 1243,
`1249 (Fed. Cir. 1998). The construction that stays true to the claim language
`
`Synopsys from further participation in, or dismissal of, this inter partes
`review.
`
`17
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`m m f RRRX q RX
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`Zg] fhlm gZmnkZeer Zeb‘gl pbma ma^ bgo^gmhk{l ]^l\kbimbhg bl ebd^er ma^ \hkk^\m
`interpretation. Id. at 1250.
`1. jInstrumentation Signalk
`@hglmkn\mbhg h_ ma^ m^kf xbglmknf^gmZmbhg lb‘gZe)y k^quired by each of
`the claims at issue in this proceeding, is central to the patentability
`determination. See PO Resp. 29-37; Reply 2-8. For example, claims 1 and
`/5 k^\bm^ xbg\euding at least one instrumentation signal, wherein the
`bglmknf^gmZmbhg lb‘gZe bl bg]b\Zmbo^ h_ Zg ^q^\nmbhg lmZmnl+y @eZbf 5, the
`third, and final, \aZee^g‘^] bg]^i^g]^gm \eZbf) k^\bm^l x\k^Zmbg‘ Zg
`instrumentation signal associated with at least one synthesizable statement
`
`\hgmZbg^] bg Z k^‘blm^k mkZgl_^k e^o^e ’NPI( lrgma^lbsZ[e^ lhnk\^ \h]^+y
`a. Construction Adopted in the Decision to Institute
`Although neither the petition nor the preliminary response set forth a
`specific construction for xbglmknf^gmZmbon signal,y the Board adopted, for
`
`inkihl^l h_ ma^ A^\blbhg mh Fglmbmnm^) Zg bgm^kik^mZmbhg maZm xma^ \eZbf^]
`instrumentation signal at least encompasses an output signal created during
`synthesis of RTL source code by inserting additional logic, preserved from
`the source code, that indicates whether the corresponding RTL source code
`
`lmZm^f^gm bl Z\mbo^+y A^\blbhg mh Fglmbmnm^ .-+
`Mentor Graphics argues that this construction is only partially correct.
`PO Resp. 30. Specifically, Mentor Graphics agrees taZm xbglmknf^gmZmbhg
`lb‘gZely ^g\hfiZll xbgl^kmbg‘ Z]]bmbhgZe eh‘b\+y Id. According to Mentor
`
`DkZiab\l) ahp^o^k) ma^ k^jnbk^f^gm maZm ma^ xZ]]bmbhgZe eh‘b\ bl ik^l^ko^]
`
`_khf ma^ lhnk\^ \h]^y bl \hgmkZkr mh ahp hg^ h_ hk]bgZkr ldbee bg ma^ Zkm
`would understand the term in light of the specification. Id. at 35 (citing Ex.
`2027 ¶¶ 38-06(+ J^gmhk DkZiab\l ihbgml mh eZg‘nZ‘^ bg ma^ {043 iZm^gm
`
`18
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`m m f RRRX q RY
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`Case IPR2012-00042
`Patent 6,240,376 B1
`
`li^\b_b\Zmbhg lmZmbg‘ maZm xWbXglmknf^gmZmbhg bl ma^ ikh\^ll h_ ik^l^kobg‘
`high-level information through the synthelbl ikh\^ll+y ML N^li+ 02-36
`(quoting Ex. 1001, col. 5, ll. 3-4(+ J^gmhk DkZiab\l{l ^qi^km) Ak+ Majid
`Sarrafzadeh, states that preserving information here refers to permitting
`relation back from the execution of the gate level netlist to the corresponding
`statements in the RTL source code, not the preservation of logic itself from
`the source code. Ex. 2027 ¶ 40.
`We find this argument, along with the supporting evidence,
`
`i^klnZlbo^+ Pa^ eZg‘nZ‘^ h_ ma^ {043 iZm^gm Zelh lniihkml mabl \hg\enlbhg+
`
`Chk ^qZfie^) bff^]bZm^er _heehpbg‘ ma^ eZg‘nZ‘^ jnhm^] Z[ho^) ma^ {043
`li^\b_b\Zmbhg lmZm^l maZm xWbXglmknf^gmZmbhg i^kfbml lbfneZmbhg h_ Z gatelevel
`netlist at the level of abstraction of RTL simulation by preserving some of
`the information available at the source code level through the synthesis
`process.y Ex. 1001, col. 5, ll. 4-8 (emphasis added).
`b. 8RSV[VaV\[ \S j>[‘a_bZR[aNaV\[k
`
`Fg ikhihlbg‘ Zg Zem^kgZmbo^ \hglmkn\mbhg _hk xbglmknf^gmZmbhg lb‘gZe)y
`Mentor Graphics initially asserts that the customary meaning of the term
`xbglmknf^gmZmbhgy mh mahl^ h_ ldbee bg ma^ Zkm is xZ]]bmbhgZe \h]^ bgl^km^] bgmh
`a program to monitor and/or collect information about the program behavior
`or hi^kZmbhg ]nkbg‘ ikh‘kZf ^q^\nmbhg+y ML N^li+ 0.+ Dr. Sarrafzadeh
`
`m^lmb_b^l maZm mabl bl ahp ma^ m^kf bl x‘^g^kZeer k^\h‘gbs^] Zg] ng]^klmhh] bg
`the programming language Zkml+y Bq+ /-/4 u 30 (citing IEEE Standard
`Glossary of Software Engineering Terminology, IEEE Std 610.12-1990 at
`
`1. ’xA^ob\^l hk bglmkn\mbhgl bglmZee^] hk bgl^km^] bgmh aZk]pZk^ hk lh_mpZk^
`to monitor the operation of a system or component.y(8 KZmbhgZe ?nk^Zn h_
`Standards [NBS] Special Publication 500-75 Validation, Verification, and
`
`19
`
`m m f RRRX q RZ
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`Case IPR2012-00042
`Patent 6,240,376 B1
`
`Tesmbg‘ h_ @hfinm^k Oh_mpZk^ Zm 15 ’.65.( ’xPa^ bgl^kmbhg h_ Z]]bmbhgZe
`code into the program in order to collect information about program
`
`[^aZobhk ]nkbg‘ ikh‘kZf ^q^\nmbhg+y((+ S^ Z‘k^^ maZm mabl bl ma^ hk]bgZkr
`and customary meaning of the first wordwxbglmknf^gmZmbhgywof the term
`
`xbglmknf^gmZmbhg lb‘gZe+y
`c. Specification
`
`J^gmhk DkZiab\l _nkma^k Zll^kml maZm ma^ m^kf xbglmknf^gmZmbhg lb‘gZey
`k^jnbk^l maZm xma^ lb‘gZe [^ ikhob]^] [r eh‘b\ maZm bl additional to the design
`logic resulting from the synthesis of the RTL source code.y PO Resp. 30. In
`other words, the instrumentation signal cannot be created solely by
`preserving circuit components.
`
`Orghilrl Zk‘n^l maZm J^gmhk DkZiab\l{l \hglmkn\mbhg bl mhh gZkkhp
`and that the broadest reasonable construction of xbglmknf^gmZmbhg lb‘gZey bl
`broad enough to include creation solely using preservation of circuit
`components. Reply 4-8.
`According to Mentor Graphics, one of ordinary skill would
`
`ng]^klmZg] ma^ _heehpbg‘ ^q\^kiml h_ ma^ li^\b_b\Zmbhg xmh ^__^\mbo^er ]^_bg^y
`
`xbglmknf^gmZmbhg lb‘gZey mh k^jnbk^ maZm bglmknf^gmZmbhg eh‘b\ [^ Z]]^] mh ma^
`gate-level netlist (PO Resp. 31-32):
`Generally instrumentation logic is created for a synthesizable
`statement in the RTL source code either by modifying the RTL
`source code or by analyzing the RTL source code during the
`synthesis process. The instrumentation logic provides an
`output signal indicative of whether the corresponding
`synthesizable statement is active. A gate-level design including
`the instrumentation output signal is then synthesized. Referring
`to FIG. 2, the resulting gate-level design 250 contains
`additional logic to create the additional instrumentation output
`signals referenced in instrumentation data 238.
`
`20
`
`m
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