US0072650l4Bl
`
`(12) Ulllted States Patent
`Hui et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 7,265,014 B1
`Sep. 4, 2007
`
`(54) AVOIDING FIELD OXIDE GOUGING IN
`SHALLOW TRENCH ISOLATION (STI)
`REGIONS
`
`(75)
`
`Inventors: Angela T. Hui, Fremont, CA (US);
`J“s“k° Ogmai Cupemnoi CA (US)9
`Yider W“= CamPbe”= CA (US)
`
`(73) Assignee: Spansion LLC, Sunnyvale, CA (US)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. l54(b) by 279 days.
`
`6,197,637 B1*
`6,218,265 B1
`6,309,926 131*
`6,410,405 B2
`
`................. .. 438/257
`3/2001 Hsu et al.
`
`4/2001 Colpani
`. . . . . .
`. . . . .. 438/424
`................. .. 438/257
`10/2001 Bell et al.
`6/2002 Park ......................... .. 438/431
`
`6’468’853 B1
`6 509 232 B1*
`6:548:374 B2
`6,613,649 B2
`
`/
`10/2002 Ballllsubmmaman
`1/2003 glfrlieluéil...................ii 438/264
`
`................
`4/2003 Chung
`438/424
`9/2003 Lim et al.
`................. .. 438/435
`
`OTHER PUBLICATIONS
`
`S. Wolf, Silicon Processing for the VLSI Era, Lattice Press, vol. 2,
`1990, pp. 45-47.*
`
`* cited by examiner
`.
`.
`.
`Prtmary Exammer—Anh Duy Mai
`(74) Attorney, Agent, or Ft'rm—Winstead PC
`
`(57)
`
`ABSTRACT
`
`A method and device for avoiding oxide gouging in shallow
`tioiiohisoiatioii (ST1)iogioiiS ofa Soiiiiooiidiiotoi doVioo;A
`trench may be embed in an STI region and fined with
`insulating material. An anti-reflective coating (ARC) layer
`may be deposited over the STI region and extend beyond the
`boundaries of the STI region. A portion of the ARC layer
`may be etched leaving a remaining portion of the ARC layer
`over the STI region and extending beyond the boundaries of
`the STI region. A protective cap may be deposited to cover
`the remaining portion of the ARC layer as well as the
`insulating material. The protective cap may be etched back
`to expose the ARC layer. However, the protective cap still
`covers and protects the insulating material. By providing a
`protective cap that covers the insulating material, gouging of
`the insulating material in STI regions may be avoided
`'
`
`9 Claims, 3 Drawing Sheets
`
`(21) Appl. No.: 10/799,413
`
`(22)
`
`Filed;
`
`Mar, 12, 2004
`
`(51)
`
`1nt_c1_
`(2006.01)
`H01L 21/764
`(2005.01)
`H011, 29/00
`(52) U.s. Cl.
`.............. .. 438/257; 438/296; 257/E21.546
`(58) Field of Classification Search .............. .. 438/257,
`438/266, 424, 296; 257/E21546
`See application file for complete search history.
`
`(56)
`
`References Cited
`US. PATENT DOCUMENTS
`
`5/1998 Wu .......................... .. 438/444
`2/2000 Early et al.
`438/257
`- - - - -
`3/2000 Y00 of 31-
`- - - -- 438/425
`3/2000 Trips” ct a1~
`257/316
`3/2000 Early et 31'
`438/257
`4/2000 He et a1’
`’ ’ ’ ’ ’ ’
`’ ’ ’ " 438/142
`6/2000 Kepler et al.
`438/400
`.
`8/2000 Yang et al.
`............... .. 438/257
`11/2000 Kuehne et al.
`........... .. 438/437
`
`
`
`5,747,377 A
`6,030,868 A *
`6,033,969 A
`65034395 A
`6’043’120 A
`6’051’451 A
`6,074,927 A
`6,110,779 A *
`6,146,975 A
`
`50
`
`
`
` E
`
`6/A
`MX027II-1 01 4
`
`EXHIBIT
`MACRONIX
`MACRONIX
`IPR2014-00898
`IPR201 4-00898
`MX027II-1014
`
`(cid:44)(cid:51)(cid:53)(cid:21)(cid:19)(cid:20)(cid:23)(cid:16)(cid:19)(cid:19)(cid:27)(cid:28)(cid:27)(cid:3)
`(cid:40)(cid:91)(cid:75)(cid:76)(cid:69)(cid:76)(cid:87)(cid:3)(cid:48)(cid:59)(cid:19)(cid:21)(cid:26)(cid:44)(cid:44)(cid:16)(cid:20)(cid:19)(cid:20)(cid:23)(cid:15)(cid:3)(cid:83)(cid:17)(cid:3)(cid:20)
`
`

`
`U.S. Patent
`
`Sep. 4, 2007
`
`Sheet 1 of 3
`
`US 7,265,014 B1
`
`56
`54
`52 :‘ '-— 50
`
`12
`
`:1 x.._ 54
`52 ~: 50
`
`FIG. 5C
`
`FIG. 5D
`
`IPRZO14-00898
`(cid:44)(cid:51)(cid:53)(cid:21)(cid:19)(cid:20)(cid:23)(cid:16)(cid:19)(cid:19)(cid:27)(cid:28)(cid:27)(cid:3)
`Exhibit MX027||-1014, p. 2
`(cid:40)(cid:91)(cid:75)(cid:76)(cid:69)(cid:76)(cid:87)(cid:3)(cid:48)(cid:59)(cid:19)(cid:21)(cid:26)(cid:44)(cid:44)(cid:16)(cid:20)(cid:19)(cid:20)(cid:23)(cid:15)(cid:3)(cid:83)(cid:17)(cid:3)(cid:21)
`
`

`
`U.S. Patent
`
`Sep. 4, 2007
`
`Sheet 2 of 3
`
`US 7,265,014 B1
`
`ETCH TRENCH IN STI REGION
`
`20‘
`
`FILL TRENCH WITH INSULATION MATERIAL
`
`202
`
`FORM GATE OXIDE LAYER OVER STI
`REGION AND EXTENDING BEYOND
`BOUNDARIES OF STI REGION
`
`2
`
`05
`
`DEPOSIT POLYSILICON LAYER OVER
`GATE OXIDE LAYER
`
`204
`
`DEPOSIT ARC EAVER ovER
`po|_YsI|_IcoN EAVER
`
`205
`
`DEPOSIT MASK LAYER OVER ARC LAYER
`
`205
`
`PATTERN AND ETCH MASK AND ARC LAYER
`OVER A PORTION OF STI REGION
`
`207
`
`ETCH POLYSILICON AND GATE OXIDE LAYER
`OVER THE PORTION OF STI REGION
`
`205
`
`200
`/V
`
`REMOVE MASK
`
`209
`
`DEPOSIT A PROTECTIVE CAP OVER STI
`REGION AND EXTENDING BEYOND THE
`
`AS WELL AS THE INSULATING MATERIAL
`
`BOUNDARIES OF STI REGION WHERE THE
`PROTECTIVE CAP COVERS BOTH THE
`REMAINING PORTION OF THE ARC LAYER
`
`210
`
`ETCH PORTION OF PROTECTIVE PLUG TO
`EXPOSE ARC LAYER BUT MAINTAIN
`PROTECTION OF INSULATING MATERIAL
`
`11
`
`2
`
`ETCH ARC LAYER
`
`212
`
`FIG. 2
`
`IPRZO14-00898
`(cid:44)(cid:51)(cid:53)(cid:21)(cid:19)(cid:20)(cid:23)(cid:16)(cid:19)(cid:19)(cid:27)(cid:28)(cid:27)(cid:3)
`Exhibit MX027||-1014, p. 3
`(cid:40)(cid:91)(cid:75)(cid:76)(cid:69)(cid:76)(cid:87)(cid:3)(cid:48)(cid:59)(cid:19)(cid:21)(cid:26)(cid:44)(cid:44)(cid:16)(cid:20)(cid:19)(cid:20)(cid:23)(cid:15)(cid:3)(cid:83)(cid:17)(cid:3)(cid:22)
`
`

`
`U.S. Patent
`
`Sep. 4, 2007
`
`Sheet 3 of 3
`
`US 7,265,014 B1
`
`5554
`$4 *1
`
`2 %_’;““‘% 54
`
`55
`
`FIG. 5E
`
`FIG. 5F
`
`55
`
`.\\\\V
`
`A7:
`
`50
`
`FIG. 56
`
`IPRZO14-00898
`(cid:44)(cid:51)(cid:53)(cid:21)(cid:19)(cid:20)(cid:23)(cid:16)(cid:19)(cid:19)(cid:27)(cid:28)(cid:27)(cid:3)
`Exhibit MX027||-1014, p. 4
`(cid:40)(cid:91)(cid:75)(cid:76)(cid:69)(cid:76)(cid:87)(cid:3)(cid:48)(cid:59)(cid:19)(cid:21)(cid:26)(cid:44)(cid:44)(cid:16)(cid:20)(cid:19)(cid:20)(cid:23)(cid:15)(cid:3)(cid:83)(cid:17)(cid:3)(cid:23)
`
`

`
`US 7,265,014 B1
`
`1
`AVOIDING FIELD OXIDE GOUGING IN
`SHALLOW TRENCH ISOLATION (STI)
`REGIONS
`
`TECHNICAL FIELD
`
`The present invention is related to the use of shallow
`trench isolation (STI)
`in the design and fabrication of
`integrated circuits, and, more specifically, avoiding damage
`to the field oxide in STI regions during subsequent process-
`ing steps in the fabrication of an integrated circuit device.
`
`BACKGROUND INFORMATION
`
`In the design and fabrication of integrated circuits, it is
`necessary to isolate adjacent active devices from one another
`so that leakage currents between devices do not cause the
`integrated circuits to fail or malfunction. As dimensions of
`semiconductor devices have shrunk, shallow trench isolation
`(STI) techniques have largely replaced other isolation tech-
`niques such as LOCOS.
`In fabricating an STI region,
`conventional photolithography and etching techniques may
`be used to create trenches in the integrated circuit substrate.
`The trenches may then be filled with one or more insulating
`materials, such as thermal silicon oxide. The wafer may then
`be planarized using chemical-mechanical polishing (CMP).
`Additional processing steps form the active devices on the
`substrate which are interconnected to create the circuitry in
`the integrated circuit.
`As stated above, conventional photolithography tech-
`niques may be used to create trenches in the integrated
`circuit substrate. In photolithography, light may be used to
`expose a photolithography mask overlying the trench where
`the light may be reflected off of the integrated circuit layers
`undcrncath the mask. The rcflcctions may have dctrimcntal
`effects on the quality and accuracy of the resulting mask. To
`improve the results of photolithography at
`these small
`scales, SiN (SiON, SiRN) may be used as an anti-reflective
`coating or hard mask layer. The anti-reflective coating layer
`may reduce or substantially eliminate these reflections
`thereby resulting in improved masks for creating small
`features and structures in an integrated device.
`After the formation of the gate,
`the hard mask’anti-
`reflective coating layer may need to be removed prior to
`subsequent device processing. The hard mask/anti-reflective
`coating layer may be removed using either a conventional
`wet strip process or a conventional plasma etching process.
`A conventional wet strip process may use hot phosphoric
`acid which may damage the polysilicon layer underlying the
`anti-reflective coating layer; whereas, a conventional plasma
`etching process may cause extensive gouging in any
`exposed field oxide, including in the thermal oxide in an STI
`region. Gouges in STI regions may alter the isolation
`properties of the STI region. Further, gouges in STI regions
`may create an uneven surface causing gap-fill problems for
`subsequent processing of the device wafer.
`Therefore,
`there is a need in the art to strip a hard
`mask/anti-reflective coating layer that avoids damage to
`exposed polysilicon surfaces as well as avoids gouging
`exposed field oxide such as in STI regions.
`
`SUMMARY OF INVENTION
`
`The problems outlined above may at least in part be
`solved by depositing a protective cap or plug over the hard
`mask/anti-reflective coating layer. The protective cap may
`be etched back to expose the hard mask/anti-reflective
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`2
`
`coating layer. However, the protective cap still covers and
`protects the thermal oxide in the trench. By providing a
`protective cap that covers the thermal oxide in the trench,
`gouging of thc cxposcd ficld oxide in STI rcgions may be
`avoided.
`
`In one embodiment of the present invention, a method for
`avoiding oxide gouging in shallow trench isolation (STI)
`regions of a semiconductor device may comprise the step of
`etching a trench in an STI region. The method may further
`comprise depositing insulating material
`in the formed
`trench. The method may further comprise depositing an
`anti-reflective coating layer overlying the STI region and
`extending beyond the boundaries of the STI region. The
`method may further comprise etching a portion of the
`anti-reflective coating layer over the STI region leaving a
`remaining portion of the anti-reflective coating layer over
`the STI region and extending beyond the boundaries of the
`STI region. The method may further comprise depositing a
`protective cap covering the STI
`region and extending
`beyond the boundaries of the STI region. The deposited
`protective cap covers the remaining portion of the anti-
`reflective coating layer as well as the insulating material in
`the trench.
`
`In another embodiment of the present invention, a device
`may comprise a trench in a shallow trench isolation (STI)
`region. The device may further comprise insulating material
`filled in the trench. The device may further comprise a gate
`oxide layer covering a portion of the STI region and extend-
`ing beyond the boundaries of the STI region. The device
`may further comprise a polysilicon layer overlying the gate
`oxide layer where the polysilicon layer covers the portion of
`the STI region and extends beyond the boundaries of the STI
`region. The device may further comprise an anti-reflective
`coating layer overlying the polysilicon layer where the
`a11ti-reflective coating layer covers the portion of the STI
`region and extends beyond the boundaries of the STI region.
`The device may further comprise a protective cap overlying
`the anti-reflective coating layer where the protective cap
`covers the entire STI region and extends beyond the bound-
`aries of the STI region. Specifically,
`the protective cap
`covers the anti-reflective coating layer covering the portion
`of the STI region and covers the insulating material filled in
`the trench over the STI region.
`The foregoing has outlined rather broadly the features and
`technical advantages of one or more embodiments of the
`present invention in order that the detailed description of the
`present invention that follows may be better understood.
`Additional features and advantages of the present invention
`will be described hereinafter which form the subject of the
`claims of the invention.
`
`BRIEF DESCRIPTION OF DRAWINGS
`
`A better understanding of the present invention can be
`obtained when the following detailed description is consid-
`ered in conjunction with the following drawings, in which:
`FIG. 1 illustrates an embodiment of the present invention
`of a partial cross-section of a semiconductor wafer including
`a number of shallow trench isolation structures;
`FIG. 2 illustrates a flowchart of a method for avoiding
`field oxide gouging in shallow trench isolation (STI) regions
`of a semiconductor device in accordance with the present
`invention; and
`FIGS. 3A through 3G illustrate various stages in the
`fabrication of an integrated circuit in an STI region of a
`wafer in accordance with an embodiment of the present
`invention.
`
`IPRZO14-00898
`(cid:44)(cid:51)(cid:53)(cid:21)(cid:19)(cid:20)(cid:23)(cid:16)(cid:19)(cid:19)(cid:27)(cid:28)(cid:27)(cid:3)
`Exhibit MX027||-1014, p. 5
`(cid:40)(cid:91)(cid:75)(cid:76)(cid:69)(cid:76)(cid:87)(cid:3)(cid:48)(cid:59)(cid:19)(cid:21)(cid:26)(cid:44)(cid:44)(cid:16)(cid:20)(cid:19)(cid:20)(cid:23)(cid:15)(cid:3)(cid:83)(cid:17)(cid:3)(cid:24)
`
`

`
`3
`DETAILED DESCRIPTION
`
`US 7,265,014 B1
`
`4
`
`In the following description, numerous specific details are
`set forth to provide a thorough understanding of the present
`invention. However, it will be obvious to those skilled in the
`art that the present invention may be practiced without such
`specific details. In other instances, well-known processes
`have been shown in block diagram form in order not to
`obscure the present invention in urmecessary detail. For the
`most part, some details and considerations have been omit-
`ted inasmuch as such details and considerations are not
`
`necessary to obtain a complete understanding of the present
`invention and are within the skills of persons of ordinary
`skill in the relevant art.
`
`FIG. 1 illustrates an embodiment of the present invention
`of a cross-section of a portion of a wafer 10 comprising
`shallow trench isolation (STI) structures 14-16. Wafer 10
`may include a substrate 12. Substrate 12 may be made of
`doped silicon, although gallium arsinide or other suitable
`semiconductor substrate material may also be used. Using
`conventional well-known techniques and processes, sub-
`strate 12 may include a well 13, which may be a p-well or
`an n-well depending on the structure being fabricated and
`the process technology being used, e.g. CMOS, MOS,
`BiCMOS, or bipolar process technologies. As illustrated in
`FIG. 1, the isolation structures may be formed in an area of
`a single dopant type or concentration, or at a boundary
`between areas that have been doped differently. For instance,
`trench 14 is formed directly in substrate 12; whereas, trench
`16 is formed in doped well 13 and trench 15 is formed at the
`boundary between substrate 12 and well 13.
`As stated in the Background Information section, in the
`fabrication of a semiconductor device using STI techniques,
`the hard mask/anti-reflective coating layer may need to be
`removed prior to subsequent device processing. The hard
`mask/anti-reflective coating layer may be removed using
`either a conventional wet strip process or a conventional
`plasma etching process. A conventional wet strip process
`may use hot phosphoric acid which may damage the poly-
`silicon layer underlying the anti-reflective coating layer;
`whereas, a conventional plasma etching process may cause
`extensive gouging in any exposed field oxide, including in
`the thermal oxide in an STI region. Gouges in STI regions
`may alter the isolation properties of the STI region. Further,
`gouges in STI regions may create an uneven surface causing
`gap-fill problems for subsequent processing of the device
`wafer. Therefore, there is a need in the art to strip a hard
`mask/anti-reflective coating layer that avoids damage to
`exposed polysilicon surfaces and avoids gauging exposed
`field oxide such as in STI regions. The hard mask’anti-
`reflective coating layer may be stripped while avoiding
`gouging the exposed field oxide in the STI regions using the
`method described below in association with FIGS. 2 and
`
`3A-F. FIG. 2 is a flowchart of a method for avoiding field
`oxide gouging in shallow trench isolation (STI) regions of a
`semiconductor device in accordance with an embodiment of
`
`the present invention. FIGS. 3A-F illustrate an embodiment
`of the present invention of the various stages in the fabri-
`cation of an integrated circuit in an STI region of a wafer
`using the method described in FIG. 2. FIGS. 2 and 3A-F will
`be discussed in conjunction with one another.
`Referring to FIG. 2, in conjunction with FIGS. 3A-F, in
`step 201, a trench, e.g., trench 14, is etched in an STI region
`in a wafer 10 (FIG. 1) as illustrated in FIG. 3A. In step 202,
`the formed trench, e.g., trench 14, is filled with an insulating
`material 18, e.g., thermal oxide, as illustrated in FIG. 3A.
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`In step 203, a gate oxide layer 30 is formed over the STI
`region, e.g., STI region 14, and extends beyond the bound-
`aries of the STI region, e.g., STI region 14, as illustrated in
`FIG. 3A. In stcp 204, a polysilicon layer 32 is dcpositcd ovcr
`gate oxide layer 30 as illustrated in FIG. 3A. In step 205, an
`anti-reflective coating layer 34 is deposited over polysilicon
`layer 32 as illustrated in FIG. 3A. In step 206, a mask layer
`36 is deposited over anti-reflective coating layer 34 as
`illustrated in FIG. 3A.
`
`In step 207, mask layer 36 and anti-reflective coating
`layer 34 are patterned and etched over a portion of the STI
`region, e.g., STI region 14, to expose selected portions of
`polysilicon layer 32 as illustrated in FIG. 3B.
`In step 208, polysilicon layer 32 and gate oxide layer 30
`are etched over the same portion of the STI region, e.g., STI
`region 14, to form interconnects on wafer 10 as illustrated in
`FIG. 3C.
`
`In step 209, mask 36 is removed from wafer 10 as
`illustrated in FIG. 3D.
`
`The remaining ARC layer 34 over the STI region and
`extending beyond the boundaries of the STI region, e.g., STI
`region 14, needs to be stripped. As stated above, anti-
`reflective coating layer 34 needs to be stripped in such a
`manner as to avoid field oxide gouging. Gouging of the field
`oxide may be avoided by depositing a protective cap or plug
`38, e.g., thin layer of photoresist, in step 210, over the STI
`region, e.g., STI region 14, and extending beyond the
`boundaries of the STI region, e.g., STI region 14, as illus-
`trated in FIG. 3E. In this manner, the remaining portion of
`anti-reflective coating layer 34 as well as insulating material
`18 is covered by protective cap 38 as illustrated in FIG. 3E.
`In step 211, protective cap 38 is etched back to expose
`anti-reflective coating layer 34 but maintains protection of
`insulating material 18 as illustrated in FIG. 3F. That is,
`protective cap 38 is etched back to expose anti-reflective
`coating layer 34 but remains covering insulating material 18
`to protect
`insulating material 18 from etching.
`In one
`embodiment, protective cap 38 is a photoresist
`that
`is
`relatively resistant to the types of etching used to remove
`anti-reflective coating layer 34 from wafer 10. For example,
`protective cap 38 may be a layer of photoresist with a
`thickness of about 800 to 1200 A (Angstroms). In one
`embodiment, protective cap 38 may be a layer of photoresist
`with a thickness of about 1000 A.
`In step 212, anti-reflective coating layer 34 is etched using
`plasma etching while avoiding gouging of insulating mate-
`rial 18 due to protective cap 38 covering insulating material
`18 as illustrated in FIG. 3G. It is noted that other etching
`techniques besides plasma etching may be used to remove
`anti-reflective coating layer 34 that is highly selective for
`removing anti-reflective coating layer 34 and not reactive
`with the material of protective cap 38. For example, a
`plasma etching process using CF4, CHF3 and CH3F as the
`active species may be sufficiently selective to remove anti-
`reflective coating layer 34 without removing the photoresist
`used as protective cap 38.
`It is further noted that method 200 may include other
`and/or additional steps that, for clarity, are not depicted. It is
`further noted that method 200 may be executed in a different
`order than presented and that the order presented in the
`discussion of FIG. 2 is illustrative. It is further noted that
`
`certain steps in method 200 may be executed in a substan-
`tially simultaneous manner.
`The present invention has been described with reference
`to various embodiments, which are provide for purposes of
`illustration, so as to enable one of ordinary skill in the art to
`make and use the invention and is provided in the context of
`IPRZO14-00898
`(cid:44)(cid:51)(cid:53)(cid:21)(cid:19)(cid:20)(cid:23)(cid:16)(cid:19)(cid:19)(cid:27)(cid:28)(cid:27)(cid:3)
`Exhibit MX027||-1014, p. 6
`(cid:40)(cid:91)(cid:75)(cid:76)(cid:69)(cid:76)(cid:87)(cid:3)(cid:48)(cid:59)(cid:19)(cid:21)(cid:26)(cid:44)(cid:44)(cid:16)(cid:20)(cid:19)(cid:20)(cid:23)(cid:15)(cid:3)(cid:83)(cid:17)(cid:3)(cid:25)
`
`

`
`US 7,265,014 B1
`
`5
`a patent application and its requirements. One of ordinary
`skill in the art will readily recognize that various modifica-
`tions to the embodiment may be made with out departing
`from thc gcncric principles and features dcscribcd hcrcin.
`Accordingly, the present invention is not intended to be
`limited to the disclosed embodiment but is to be accorded
`
`the widest scope consistent with the principles and features
`described herein subject to the appended claims.
`What is claimed is:
`
`1. A method for avoiding oxide gouging in shallow trench
`isolation (STI) regions of a semiconductor device compris-
`ing the steps of:
`etching a trench in an STI region;
`filling said trench with an insulating material;
`depositing an anti-reflective coating layer over said STI
`region and extending beyond the boundaries of said
`STI region;
`etching a portion of said anti-reflective coating layer over
`said STI region leaving a remaining portion of said
`anti-reflective coating layer over said STI region and
`extending beyond the boundaries of said STI region;
`and
`depositing a protective cap covering said STI region and
`extending beyond the boundaries of said STI region,
`wherein said protective cap covers said remaining
`portion of said anti-reflective coating layer and said
`insulating material over said STI region;
`wherein said protective cap comprises photoresist mate-
`rial.
`
`2. The method as recited in claim 1, wherein said photo-
`resist material has a thickness of about 800 A to 1200 A.
`3. A method for avoiding oxide gouging in shallow trench
`isolation (STI) regions of a semiconductor device compris-
`ing the steps of:
`etching a tre11cl1 in mi STI region;
`filling said trench with an insulating material;
`depositing an anti-reflective coating layer over said STI
`region and extending beyond the boundaries of said
`STI region;
`etching a portion of said anti-reflective coating layer over
`said STI region leaving a remaining portion of said
`anti-reflective coating layer over said STI region and
`extending beyond the boundaries of said STI region;
`depositing a protective cap covering said STI region and
`extending beyond the boundaries of said STI region,
`wherein said protective cap covers said remaining
`portion of said anti-reflective coating layer and said
`insulating material over said STI region;
`etching a portion of said protective cap to expose said
`remaining portion of said anti-reflective coating layer
`while maintaining protection of said insulating mate-
`rial; and
`etching said remaining portion of said anti-reflective
`coating layer;
`
`6
`wherein said insulating material is protected during etch-
`ing of said remaining portion of said anti-reflective
`coating layer by said protective cap.
`4. The method as recited in claim 3, wherein said remain-
`ing portion of said anti-reflective coating layer is etched
`using a plasma etch process.
`5. A method for avoiding oxide gouging in shallow trench
`isolation (STI) regions of a semiconductor device compris-
`ing the steps of:
`etching a trench in an STI region;
`filling said trench with an insulating material;
`forming a gate oxide layer overlying said STI region and
`extending beyond the boundaries of said STI region;
`depositing a polysilicon layer over said gate oxide layer;
`depositing an anti-reflective coating layer over said poly-
`silicon layer;
`etching a portion of said anti-reflective coating layer over
`said STI region leaving a remaining portion of said
`anti-reflective coating layer over said STI region and
`extending beyond the boundaries of said STI region;
`etching an exposed portion of said polysilicon layer and
`said gate oxide layer over said STI region leaving a
`remaining portion of said polysilicon layer and said
`gate oxide layer over said STI region and extending
`beyond the boundaries of said STI region;
`depositing a protective cap over said STI region and
`extending beyond the boundaries of said STI region,
`w1erein said protective cap covers said remaining
`portion of said anti-reflective coating layer over said
`S"l region and covers said insulating material over said
`S"l region;
`etch'ng a portion of said protective cap to expose said
`remaining portion of said anti-reflective coating layer
`w1ile maintaining protection of said insulating mate-
`rial; and
`etch'ng said remaining portion of said anti-reflective
`coating layer;
`wherein said insulating material is protected during etch-
`ing of said remaining portion of said anti-reflective
`coating layer by said protective cap.
`6. The method as recited in claim 1, wherein said pro-
`tective cap comprises photoresist material.
`7. The method as recited in claim 6, wherein said photo-
`resist material has a thickness of about 800 A to 1200 A.
`8. The method as recited in claim 1, wherein said remain-
`ing portion of said anti-reflective coating layer is etched
`using a plasma etch process.
`9. The method as recited in claim 1, wherein said insu-
`lating material comprises thermal oxide.
`
`5
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`IPRZO14-00898
`(cid:44)(cid:51)(cid:53)(cid:21)(cid:19)(cid:20)(cid:23)(cid:16)(cid:19)(cid:19)(cid:27)(cid:28)(cid:27)(cid:3)
`Exhibit MX027||-1014, p. 7
`(cid:40)(cid:91)(cid:75)(cid:76)(cid:69)(cid:76)(cid:87)(cid:3)(cid:48)(cid:59)(cid:19)(cid:21)(cid:26)(cid:44)(cid:44)(cid:16)(cid:20)(cid:19)(cid:20)(cid:23)(cid:15)(cid:3)(cid:83)(cid:17)(cid:3)(cid:26)