UNITED STATES PATENT AND TRADEMARK OFFICE
`
`___________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`___________________________________
`
`MACRONIX INTERNATIONAL CO., LTD., MACRONIX ASIA LIMITED,
`MACRONIX (HONG KONG) CO., LTD. and MACRONIX AMERICA, INC.
`Petitioners
`
`v.
`
`SPANSION LLC
`Patent Owner
`
`___________________________________
`
`Case No. IPR2014-00898
`Patent Number 7,151,027
`
`Before the Honorable DEBRA K. STEPHENS, JUSTIN T. ARBES, and
`RICHARD E. RICE, Administrative Patent Judges.
`
`DECLARATION OF SHUKRI SOURI, Ph.D.
`
`
`
`
`
`
`
`
`
`Spansion Exhibit 2007
`Macronix et al v. Spansion
`IPR2014-00898
`Page 00001
`
`
`
`___________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`___________________________________
`
`MACRONIX INTERNATIONAL CO., LTD., MACRONIX ASIA LIMITED,
`MACRONIX (HONG KONG) CO., LTD. and MACRONIX AMERICA, INC.
`Petitioners
`
`v.
`
`SPANSION LLC
`Patent Owner
`
`___________________________________
`
`Case No. IPR2014-00898
`Patent Number 7,151,027
`
`Before the Honorable DEBRA K. STEPHENS, JUSTIN T. ARBES, and
`RICHARD E. RICE, Administrative Patent Judges.
`
`DECLARATION OF SHUKRI SOURI, Ph.D.
`
`
`
`
`
`
`
`
`
`Spansion Exhibit 2007
`Macronix et al v. Spansion
`IPR2014-00898
`Page 00001
`
`
`
`
`
`I, Shukuri Souri, hereby declare under penalty of perjury under the laws of the United
`
`States of America:
`
`I.
`
`Qualifications
`
`1.
`
`I am currently a Corporate Vice President at Exponent, Inc.
`
`(“Exponent”), an engineering and scientific consulting firm, headquartered at 149
`
`Commonwealth Drive, Menlo Park, California 94025. I am based in, and the Director
`
`of, Exponent’s New York office. I am also the Director of Exponent’s Electrical
`
`Engineering and Computer Science practice.
`
`2.
`
`I received a Master’s Degree in Electrical Engineering from Stanford
`
`University in 1994, and a Ph.D. in Electrical Engineering, also from Stanford
`
`University, in 2003. I have extensive experience with semiconductor devices,
`
`including the design, fabrication, modeling, measurement, and testing of integrated
`
`circuits. While at Stanford University, I taught several courses on integrated circuit
`
`fabrication, optical fiber communications, and networking. Before joining Stanford, I
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`was a member of the staff at Raychem Corporate Research and Development
`
`Laboratories, where I worked on semiconductor materials and electrical circuit
`
`protection devices. I am a named inventor on four U.S. patents related to
`
`semiconductor processes, devices, and integrated circuits.
`
`3. My education, experience, and qualifications, including a list of my
`
`publications and a list of matters in which I have testified as an expert, are set forth in
`
`my curriculum vitae, attached hereto as EX2006. My opinions, as expressed in this
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`1
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`Page 00002
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`report, are based on my education, career, and relevant experience, as well as the
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`materials reviewed.
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`4.
`
`I have been retained on behalf of Patent Owner Spansion LLC to offer
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`statements and opinions regarding the understanding of a person of ordinary skill in
`
`the art (discussed below) as it relates to U.S. Patent No. 7,151,027 (the ’027 Patent)
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`assigned to Patent Owner, as well as other references presented to me by counsel for
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`Patent Owner.
`
`5.
`
`I am a salaried employee of Exponent. Exponent charges an hourly rate
`
`of $495 plus expenses for my work performed in connection with this Inter Partes
`
`Review. I have received no additional compensation for my work in this Inter Partes
`
`Review, and my compensation does not depend on the contents of this report, any
`
`testimony I provide, or the ultimate outcome of this Inter Partes Review.
`
`II. Materials Considered
`
`6.
`
`In developing my opinions below relating to the ’027 Patent, I have
`
`considered the following materials:
`
` U.S. Patent No. 7,151,027 (Exhibit MX027II-1001);
`
` Corrected Petition for Inter Partes Review of U.S. Patent No.
`7,151,027 (“Petition” or “Pet.”) (Paper No. 6);
`
` Patent Owner’s Preliminary Response (Paper No. 12);
`
` Decision – Institution of Inter Partes Review (Paper No. 13) (“ID”);
`
` Declaration of Dhaval J. Brahmbhatt (Exhibit MX027II-1002);
`
`
`
`2
`
`Page 00003
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`
`
`
`
` U.S. Patent No. 6,458,655 to Yuzuriha, et al. (“Yuzuriha”) (Exhibit
`MX027II-1003);
`
` U.S. Patent Application Publication No. 2003/0042520 to
`Tsukamoto (Exhibit MX027II-1004);
`
` C.-F. Lin et al., A ULSI shallow trench isolation process through the
`integration of multilayered dielectric process and chemical-mechanical
`planarization, THIN SOLID FILMS 248-52 (1999) (Exhibit MX027II-
`1007);
`
` S. Wolf & R.N. Tauber, Silicon Processing for the VLSI Era: Vol. 1 –
`Process Technology 2d Ed. (Lattice Press 2000) (Exhibit MX027II-1008);
` CV of Dhaval J. Brahmbhatt (Exhibit MX027II-1009);
` U.S. Patent No. 5,371,030 to Bergemont (“Bergemont”) (Exhibit
`MX027II-1010);
` U.S. Patent No. 4,571,819 to Rogers et al. (“Rogers”) (Exhibit
`MX027II-1011);
` Excerpts of Transcript of Videotaped Deposition of Dr. Dhaval
`Brahmbhatt (July 2, 2014) (EX2005);
`
` Transcript of Videotaped Deposition of Dr. Dhaval Brahmbhatt (July
`3, 2014) (EX2004);
` Transcript of Videotaped Deposition of Mr. Dhaval Brahmbhatt
`(September 24, 2014) (EX2008) and Deposition Exhibits (EX2000 –
`EX2003);
`
` Yuzuriha et al., A 14-ns 1-Mbit CMOS SRAM with Variable Bit
`Organization, IEEE Journal of Solid-State Circuits, Vol. 23, No. 5,
`October 1988 (EX2009);
`
` Certified Translation of Excerpts of JP 2003-078040 and
`Accompanying Appendices (EX2010);
`
` All other materials referenced herein.
`III. Level of Ordinary Skill for the ’027 Patent
`
`7.
`
`I understand that the factors that may be considered in determining the
`
`ordinary level of skill in the art include: (1) the levels of education and experience of
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`3
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`Page 00004
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`persons working in the field; (2) the types of problems encountered in the field; and (3)
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`the sophistication of the technology. I understand that a person of ordinary skill in the
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`art is not a specific real individual, but rather a hypothetical individual having the
`
`qualities reflected by the factors above.
`
`8.
`
`It is my opinion that at least as of June 1, 2004, the filing date of the ’027
`
`Patent, a person of ordinary skill in the art would have had a Bachelor’s of Science
`
`degree in materials science, electrical engineering, physics or the equivalent and about
`
`two years of processing experience related to memory device fabrication.
`
`9.
`
`I note that Mr. Brahmbhatt has opined that “a person of ordinary skill in
`
`the art would have a bachelor’s degree in Electrical Engineering and 2-3 years of
`
`experience in design or fabrication of semiconductor memories. An individual with
`
`additional education or industry experience could also be one of ordinary skill in the
`
`art if that additional experience compensated for a deficit in the other aspect stated
`
`above.” MX027II-1002 at ¶ 28.
`
`10. Unless otherwise stated, when I state that something would be known or
`
`understood by a person of ordinary skill in the art, I am referring to a person with the
`
`level of education and experience expressed in ¶¶ 8-9 above, as of June 1, 2004. As
`
`described above and in my CV (EX2006), I have decades of experience with
`
`semiconductor devices, including the design and fabrication of memory devices. As
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`of June 1, 2004, I would have qualified as one of ordinary skill in the art according to
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`4
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`Page 00005
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`either of the above definitions. Therefore, I am qualified to testify about what a
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`person of ordinary skill in the art would have known and understood at that time.
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`IV. Relevant Legal Standards
`
`11.
`
`I have been informed that if an independent claim is found to be valid,
`
`every claim that depends from it is also valid. I have also been informed that if an
`
`independent claim is found to be invalid, the claims which depend from it may be
`
`found to be valid.
`
`12.
`
`I understand that to be valid, a patent claim must be non-obvious and
`
`novel. I also understand that a patent claim is not novel if is anticipated by a single
`
`prior art reference – that is, a single prior art reference discloses each and every
`
`element of the claim either expressly or inherently. I also understand that a single
`
`reference cannot merely disclose each element. Rather, it must disclose all of the
`
`elements as arranged in the claim. I further understand that for a reference to
`
`“inherently” disclose something, the missing descriptive matter must necessarily be
`
`present in the reference, not merely probably or possibly present, and that it would be
`
`so recognized by a person of ordinary skill. I understand that if an element of the
`
`claim is not disclosed by one prior art reference, then the claim is not anticipated.
`
`13.
`
`I understand that a patent claim is deemed obvious if the differences
`
`between it and the prior art are such that the subject matter as a whole would have
`
`been obvious at the time the invention was made to a person having ordinary skill in
`
`the art. That is, a person of ordinary skill must have had a reasonable expectation of
`5
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`Page 00006
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`success in making or practicing the claimed invention, based on the prior art. I also
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`understand that the obviousness analysis does not permit the use of hindsight. One
`
`way of avoiding a hindsight analysis is to point to a suggestion or a motivation in the
`
`prior art to make or practice the claimed invention.
`
`14.
`
`I have been informed that to render a claim obvious, a combination of
`
`prior art references must disclose each and every claim element of that claim, and that
`
`obviousness is a question of law (i.e., for the Board to determine) based on the
`
`underlying facts. I understand that the underlying factual inquiries are: (1) the scope
`
`and content of the prior art, (2) the differences between the prior art and the claims at
`
`issue, (3) the level of ordinary skill in the pertinent art, and (4) secondary
`
`considerations of nonobviousness. I also understand that a patent composed of
`
`several elements is not proven to be obvious by simply demonstrating that each of its
`
`elements was, independently, known in the prior art. Instead, I understand that there
`
`must be some rationale given to support the conclusion.
`
`15.
`
`I further understand that, in making a determination as to whether or
`
`not the claimed invention would have been obvious to a person of ordinary skill, the
`
`Board must consider certain objective factors, such as commercial success, long-felt,
`
`but unsolved need, unexpected results, copying, and praise by others in the field. The
`
`presence of such factors is evidence of non-obviousness. I also understand that a
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`connection, or nexus, must exist between the objective category and the claimed
`
`invention.
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`6
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`Page 00007
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`16.
`
`I understand that the Board has instituted an inter partes review of claims
`
`7 and 14 of the ’027 Patent. I understand that trial is limited to the following ground:
`
`whether claims 7 and 14 are are rendered obvious by Yuzuriha, Tsukamoto, and Lin.
`
`(ID at 19). I understand that the Board “has not made a final determination under 35
`
`U.S.C. § 318(a) with respect to the patentability of the challenged claims.” Id.
`
`V.
`
`Background of the ’027 Patent
`17. U.S. Patent 7,151,027 (the “’027 Patent”), entitled “Method and Device
`
`for Reducing Interface Area of a Memory Device” was filed on June 1, 2004, and
`
`issued on December 19, 2006. The patent names inventors Hiroyuki Ogawa, Yider
`
`Wu, Kuo-Tung Chang, and Yu Sun.
`
`18. As discussed in the ’027 Patent, “[o]ne important goal of the
`
`semiconductor industry is to reduce the size of memory devices. In reducing the size
`
`of operational components (e.g., a memory array) and periphery components, an
`
`important consideration is the interface between the operational components and
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`periphery components.” MX027II-1001 at 1:18-23. This arrangement is illustrated in
`
`Figure 2 of the ’027 patent, where a memory device 200 includes the periphery
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`components, labeled 210, the memory array, labeled 220, and a portion of the
`
`interface, labeled 230. MX027II-1001 at FIG 2.
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`7
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`Page 00008
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`19. Memory devices contain millions of components made up of complex
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`structures fabricated by the repeated deposition of layers on a silicon substrate, or
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`wafer. MX027II-1001 at 1:13-18. Typical fabrication methods common in
`
`semiconductor fabrication prior to the invention of the ’027 Patent for forming
`
`memory devices typically formed the operational components and periphery
`
`components separately. Id. at 1:25-26. In other words, when the periphery
`
`components were formed, only the periphery was etched (i.e., the memory was
`
`masked, or protected from being etched), and when the memory array was formed,
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`only the memory array was etched (i.e., the periphery was masked, or protected from
`
`being etched). For various reasons, by using these different processes, a number of
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`steps having different heights at the interface were created. Id. at 1:24-31. Figure 1 in
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`8
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`Page 00009
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`
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`the ’027 Patent depicts what a step adjacent to the interface may look like using these
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`prior art methods. Id. at FIG 1.
`
`20.
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`Figure 1 shows interface 100 and substrate 110 etched leaving structures
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`115 and 120. Notably, structure 120 is higher than structure 115—a difference that is
`
`difficult to control because of the different processes being used. MX027II-1001 at
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`
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`1:34-42.
`
`21. As the ’027 Patent further describes, a common occurrence during the
`
`formation of sidewall spacers was the formation of potentially damaging stringer
`
`spacers at these steps. Id. at 1:47-51. These stringer spacers 130 may be easily peeled
`
`from the device and displaced to other locations on the device, resulting in yield loss
`
`of performance by the memory array. Id. at 1:45-53; FIG 1.
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`22. The invention described and claimed in the ’027 Patent provides a
`
`solution to this problem by providing methods for forming a polysilicon structure at
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`9
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`the interface between the memory array and the periphery where steps with different
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`heights may be formed. See id. at 2:57-3:2. In so doing, the methods of the ’027
`
`Patent reduce the formation of stringer spacers and allow for a reduction in the
`
`number of processing steps, cycle time, cost and yield loss. See id. In particular, the
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`interface structure is the same height as the memory array proximate to the memory
`
`array and the same height as the periphery proximate to the periphery, such that step
`
`size at these locations is smoothed out, reducing the occurrence of stringers from
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`spacer etching. See id. at 5:30-35.
`
`VI. Claim Construction
`23.
`I have been informed that for purposes of inter partes review a claim in an
`
`unexpired patent shall be given its broadest reasonable construction in light of the
`
`specification of the patent in which it appears. While claim terms are generally given
`
`their ordinary and customary meaning, which is the meaning that the term would have
`
`to a person of ordinary skill in the art in question at the time of the invention, the
`
`construction must also be consistent with the specification, and the claim language
`
`should be read in light of the specification as it would be interpreted by one of
`
`ordinary skill in the art.
`
`24.
`
`I understand that the Board has construed certain terms of the ’027
`
`Patent in its Institution Decision. Below is a list of the Board’s constructions that I
`
`have applied when rendering the opinions set forth herein:
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`10
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`Page 00011
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` “poly-2 layer” (claims 1, 7 and 8): “a polysilicon layer deposited later in
`time than a first polysilicon layer.” (ID at 7).
`
` “poly-1 layer” (claim 8): “a first polysilicon layer.” (ID at 7).
`
`25.
`
`I understand that the Board, based on the record then before it and
`
`without the benefit of expert testimony about how these terms would be understood
`
`by a person of ordinary skill in the art, did not agree with the Patent Owner that
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`“etching said poly-1 layer and said poly-2 layer proximate to said memory array”
`
`recited in claim 8 requires a single etching step.
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`26. As explained in detail below, it is my opinion that the “etching”
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`limitations in claim 8, as understood by a person of ordinary skill in the art in view of
`
`the ’027 Patent’s specification, requires etching the recited structures in a single
`
`etching step.
`
`27.
`
`First, the plain language of claim 8 requires that both the “said poly-1
`
`layer and said poly-2 layer” 1 are etched as a single “etching” step of the claimed
`
`method.
`
`28.
`
`Second, claim 8’s explicit recitation of “etching said poly-1 layer and said
`
`poly-2 layer proximate to said memory array” as a single “etching” step of the claimed
`
`method stands in contrast to the ’027 Patent’s separate recitation, including in other
`
`claims, of multiple distinct “etching” steps, such as claims 1, 2 and 8. For example,
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`claim 1 does not recite “etching said poly-2 layer proximate to said memory array and
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`1 All emphasis herein is added unless otherwise stated.
`11
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`Page 00012
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`proximate to said periphery...,” but instead recites two distinct “etching” steps”:
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`“etching said poly-2 layer proximate to said memory array; and etching said poly-2 layer
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`proximate to said periphery...” Moreover, claim 8’s recitation of a single “etching”
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`step for both “said poly-1 layer and said poly-2 layer proximate to said memory array”
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`stands in direct contrast to claims 1 and 2 that recite the etching of poly-1 layer and
`
`poly-2 layer as two separate steps: “etching said poly-2 layer proximate to said
`
`memory array” in claim 1 and, subsequently, in claim 2, “etching said poly-1 layer
`
`proximate to said memory array.”
`
`29. Third, the ’027 Patent explicitly describes the etching of the poly-1 layer
`
`and poly-2 layer proximate to the memory array as a single etching “step” (“step 440”)
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`in the embodiment illustrated in, for example, the ’027 Patent’s Figure 4, reproduced
`
`below with highlights in orange:
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`
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`12
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`Page 00013
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`See also MX027II-1001 at 5:5-7 (“Fig. 4 is a flowchart illustrating steps in a process 400 for
`
`fabricating a memory device, in accordance with an embodiment of the present invention.”).
`
`30. This is also confirmed in the corresponding text of the ’027 Patent,
`
`which states that this occurs in a single step: “At step 440, the poly-1 layer and the
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`poly-2 layer are etched proximate to the memory array. In one embodiment, the
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`etching is accomplished by performing a stacked gate etch.” MX027II-1001 at 5:21-
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`24.
`
`31. The ’027 Patent further states: “With reference next to FIG. 3E, in the
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`present embodiment, a known process (such as a stacked gate etch) is used to etch
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`13
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`Page 00014
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`a portion of poly-1 310 a, dielectric material 315, and poly-2 320 proximate to the
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`memory array.” Id at 4:27-30, Fig. 3D & 3E:
`
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`32. The ’027 Patent further describes that “[t]his etch is used to form
`
`individual transistors of [sic] from the polysilicon layers… The etch creates a distinct
`
`boundary between the memory array and the interface region.” Id. at 4:30-35.
`
`33.
`
`In sum, in my opinion a person of ordinary skill in the art would have
`
`understood the ‘027 Patent to disclose an embodiment in which the poly-1 layer and
`
`poly-2 layer proximate to the memory array are etched in a single etching step, and
`
`would have understood this disclosed etching of poly-1 and poly-2 in a single step to
`
`be claimed in claim 8 of the ‘027 Patent.
`
`34. The Board noted in its Institution Decision the specification’s reference
`
`to “other steps.” ID at 9 (citing MX027II-1001 at 5:7-10). However, a person of
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`14
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`Page 00015
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`ordinary skill would not understand this reference to be describing the “etch” at step
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`440 and illustrated in Fig. 3D and 3E as a multi-etch process. Instead, in my opinion,
`
`a person of ordinary skill, in view of the entire specification, would understand that
`
`the specification’s reference to these “other steps” refers to those process steps
`
`occurring before and after the steps described in the ’027 Patent to complete the
`
`formation of the interface structure. Indeed, a person of skill in the art would have
`
`understood that the portion of the specification cited by the Board refers to the
`
`“other steps” described earlier in the specification at 3:34-43, which states:
`
`Furthermore, although the device being formed is referred to as an
`interface structure, it is appreciated that FIGS. 3A-3G only show an
`interface structure in the process of being formed, and not necessarily
`a completely formed interface structure. It is appreciated that other
`processes and steps associated with the fabrication of an interface
`structure may be performed along with the process illustrated by FIGS.
`3A through 3G; that is, there may be a number of process steps
`before and after the steps shown and described by FIGS. 3A
`through 3G.
`
`MX027II-1001 at 3:34-43
`
`35. Therefore, it is my opinion that a person of ordinary skill would have
`
`understood from the ’027 Patent, including in particular it’s express disclosure of this
`
`embodiment employing a single etching step, that the claim term “etching said poly-1
`
`layer and poly 2 layer proximate to said memory array” in claim 8 means what it says:
`
`these two layers are etched in a single etching step.
`
`VII. Yuzuriha
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`
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`15
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`Page 00016
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`36.
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`Independent claim 8 recites, inter alia, “etching said poly-1 layer and said
`
`poly-2 layer proximate to said memory array.” As discussed above, the plain language
`
`of the claim limitation, as understood by a person of ordinary skill in the art in view of
`
`the express disclosure in the ’027 Patent, requires that both the “poly-1 layer and []
`
`poly-2 layer” are etched in a single etching step.
`
`37.
`
`In my opinion, Yuzuriha fails to disclose a process that etches the poly-1
`
`layer and poly-2 layer in a single etching step. Petitioner and Mr. Brahmbhatt, who
`
`have added numerous annotations to the figures from Yuzuriha shown below,
`
`acknowledge that Yuzuriha discloses between Figures 8 and 9 one step where poly-2
`
`is first etched (both proximate to the memory array and proximate to the periphery),
`
`and subsequently and separately between Figures 9 and 10 “another etching step is
`
`performed to etch the poly-1 layer (10) (shown in green) proximate to the memory
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`array.” Pet. 12; MX027II-1002 at ¶¶ 52-54. As can be seen in Petitioner’s heavily
`
`annotated Figures 8-10, Yuzuriha first performs what Petitioner has annotated as the
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`steps of “etching poly-2 proximate to the memory array” and “etching poly-2
`
`proximate to periphery.” See annotated Figs. 8-9:
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`16
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`Then, in what Petitioner itself says is a subsequent “etching step” (Pet. 12; MX027II-
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`1002 at ¶¶ 53), Yuzuriha performs what Petitioner has annotated as the step of
`
`“etching poly-1 proximate to the memory array.” See annotated Fig. 10 :
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`17
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`Page 00018
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`38.
`
`Importantly, the process that etches the alleged poly-2 layer (colored
`
`yellow by Petitioner) does not etch the alleged poly-1 layer (colored green by
`
`Petitioner). The alleged poly-1 layer is not etched until “another etching step is
`
`performed” (Pet. 12), as shown in Figure 10.
`
`39. Moreover, in my opinion, this “[]other etching step” to etch poly-1 (Pet.
`
`12), as shown between Figures 9 and 10 in Yuzuriha, also etches other portions of the
`
`structure proximate to both the memory (e.g., tunnel oxide film 9) and to the
`
`periphery (e.g., gate oxide 12), in ways that, as even Mr. Brahmbhatt concedes, are not
`
`actually disclosed in Yuzuriha but in his experience, would require additional re-
`
`masking to accomplish – confirming again that they are not part of a single etch step
`
`with the etching of poly-2 as claim 8 (and thus claim 14) requires. See, e.g., Ex. 2004 at
`
`40:16-41:3, 59:13-61:12 (“there are a whole bunch of things that get[] etched”; “it’s
`
`not one etching step”), 62:21-66:18; id. 82:2-5, 83:14-25 (Yuzuriha doesn’t “show all
`
`the steps involved”), 71:25-72:16, 73:20-75:11 (responding to question regarding
`18
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`Page 00019
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`“using the remaining oxide Film 16 as an etching mask and etching the poly-poly
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`insulation mask 11 and the Poly-1” between figures 9 and 10: “like I mentioned
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`before and I will mention this again, I do not have Yuzuriha’s complete process
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`manual in front of me. I don’t know how he did it. All I can tell you is, if it is in my
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`fab, while you’re doing that, you will have to protect the periphery; otherwise, you’re going to
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`cause damage. I mean, that’s physics, I mean, chemistry. I mean, that is going to
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`happen. So my thinking would be that – and I don’t know this how Yuzuriha does it,
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`because there is no description on that.”), 85:18-87:12 (“Q: So you don’t know
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`whether he uses the same mask to etch poly-poly or Poly-1 as to etch Layer 9? A: I
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`would be guessing. I don’t know what he does.”; “I mean, there’s a whole bunch things we
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`know that would happen in between, but we just don’t have those details”), 87:25-
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`88:13 (“Q: . . .And between Figures 9 and 10 you’ll agree that two portions of gate
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`oxide 12 are etched, as well; right? A: That’s what I see in the diagram. Q: And so
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`you don't know one way or the other whether Yuzuriha masks the periphery area
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`between 9 and 10; right? A. Well, all he says is – it’s important to read 63, line 63,
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`column 12. Actually, 62 and 63. Poly-to-poly insulation Film 11 and Floating Gate
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`10 are etched only in the memory cell region. That’s what he says.”), 95:18-96:2 (“Q:
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`Focusing now on Gate Oxide 12, which is etched between Figures 9 and 10, is there a
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`disclosure in Yuzuriha about how that etching is done? . . . A: Okay. Let me read.
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`Just a second. (Document Review.) I’m sorry, there’s no disclosure.”). And, in my
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`19
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`Page 00020
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`opinion, Yuzuriha involves separate etching steps, in part because it requires re-
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`masking to perform the disclosed steps.
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`40. Therefore, in my opinion, Yuzuriha does not disclose at least “etching
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`said poly-1 layer and said poly-2 layer proximate to said memory array,” as required in
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`independent claim 8 and, accordingly, in challenged claim 14.
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`41.
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`Petitioner and Mr. Brahmbhatt next contend that Yuzuriha, in view of
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`additional prior art references urged by Petitioner, render obvious claims 7 and 14. I
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`disagree. As discussed below, in my opinion, a person of ordinary skill in the art
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`would not have found it obvious, or been motivated, to look to the teachings of
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`Yuzuriha to begin with at least because (1) Yuzuriha is directed to step variations
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`occurring entirely within the alleged interface, whereas the challenged claims of
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`the ’027 Patent are directed to smoothing out steps between the interface and the
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`adjacent periphery and memory array; and (2) Yuzuriha discloses using isolation that
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`actually increases the alleged interface area, whereas an explicit goal of the ’027 Patent is
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`to reduce the interface area.
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`42.
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`First, claims 7 and 14 recite that the “poly-2 layer” remaining at the
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`interface (claim 7) or the “interface structure” (claim 14) is the same height as “said
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`memory array proximate to said memory array” and the same height as “said
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`periphery proximate to said periphery” such that “step size is smoothed out reducing
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`an occurrence of stringers from spacer etching.” I note that the challenged claims are
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`directed to an analysis of the heights of the interface structure and of the structures
`20
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`
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`Page 00021
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`
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`adjacent to the interface structure, namely: (1) examining the height at (a) the interface
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`structure “proximate to [the] memory array” and at (b) the memory array, and (2)
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`examining the height at (c) the interface structure “proximate to [the] periphery” and
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`at (d) the periphery. The challenged claims require (a) and (b) to have the “same height,”
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`and (c) and (d) to have the “same height.” Notably, the claims do not recite a height
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`requirement within the interface structure – they do not require, for example, that (a) the
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`interface structure “proximate to said memory array” and (c) the interface structure
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`“proximate to said periphery” must be of the “same height.” Yuzuriha, on the other
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`hand, is not concerned with the heights of an interface and the adjacent periphery, or
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`with the heights of an interface and the adjacent memory. Instead, Yuzuriha discloses
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`reducing “abrupt” step variations occurring entirely within the alleged interface area.
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`The “Tenth Embodiment” of Yuzuriha relied upon by Petitioner describes that the
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`“process performed to prevent removal of the altered surface layer of the resist”
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`allows a poly-poly insulation film (11) to recede “closer to the memory cell region”
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`than a conventional process. MX027II-1003 at 12:30-37, Figs. 7-8:
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`21
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`Page 00022
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`43. Yuzuriha further describes as its goal the creation of a “gentle slope”
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`(rather than an “abrupt” step) across points C, B, and A shown in Figure 8 above by
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`adjusting layer 11:
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`In the present embodiment, the process performed to prevent removal
`of the altered surface layer of the resist allows patterned resist 15 to
`recede due to O2 plasma or O2 mixed during the etching sequence. As
`such, when tunnel oxide film 9 is etched and thus removed, poly-poly
`insulation film 11 is finished, receding closer to the memory cell
`region than that according to a conventional process flow…. More
`specifically, isolating oxide film 8+the second polysilicon layer 13 (the
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`22
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`Page 00023
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`
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`portion indicated by arrow A) does not continue directly to isolating
`oxide film 8+the first polysilicon layer 10+poly-poly insulation layer
`11+the second polysilicon layer 13 (the portion indicated by arrow C),
`which would otherwise result in an abrupt step variation. Rather,
`isolating oxide film 8+the second polysilicon layer 13 (the portion
`indicated by arrow A) can continue to isolating oxide film 8+the second
`polysilicon layer 13+the first polysilicon layer 10 (the portion indicated
`by arrow B) and then to isolating oxide film 8+the second polysilicon
`layer 13+poly-poly insulation film 11+the first polysilicon layer 10 (the
`portion indicated by arrow C) successively, resulting in a gentle step.
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`MX027II-1003 at 12:30-52.
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`44. As a result of adjusting layer 11, a “gentle” step is introduced between
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`the portions of what will become Yuzuriha’s dummy gate indicated by arrows A and
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`C in Fig. 8. See id., Figs. 7-8. Thus, according to Yuzuriha, “any abrupt step variation
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`would not result when in a subsequent process step a dummy gate 14 is formed in
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`such region,” and “subsequent photolithography, processing and the like can be
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`advantageously facilitated.” Id. at 37-52, Fig. 9:
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`23
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`Page 00024
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`
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`45. The “abrupt step variation” Yuzuriha seeks to address (i.e., between A
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`and C in Fig. 8) occurs entirely within the alleged interface (i.e., the “dummy gate
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`region” (Pet. 17)). As noted by the Board, the “height of dummy gate 14 varies smoothly
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`from one side to the other, such that the change in height is ‘gentle,’ i.e., not ‘abrupt.’” ID
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`at 12 (emphasis added). That is, Yuzuriha is directed to introducing a “gentle step”
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`between different portions of the alleged interface. See, e.g., EX2008 at 191:8-19, 214:22-215:18,
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`215:19-216:7 (“The discussion of gentle slope in Yuzuriha in column 12 also is not
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`concerning a slope between what's marked as point A in figure 8 and the region to the
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`right of point A where you've marked structure N in figure 5 as eventually being
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`formed; correct? A. The whole discussion in the paragraph column 12 starting with
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`line 28 is talking about A, B and C with the arrows. But if you think of it, when you
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`look at figure 9 and then compare it to figure 8, just past that point the slope seems to
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`be over.”). Yuzuriha is not directed to smoothing out steps between the interface
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`structure and the memory array or between the interface structure and the periphery.
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`Indeed, quite to the contrary, Yuzuriha affirmatively includes a step between its
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`dummy gate region closest to memory cell region and the nearest memory cell. Mr.
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`Brahmbhatt in fact acknowledges that the “dummy gate region” is “elevated”
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`compared to the nearest memory cell. See, e.g., MX027II-1002 at ¶ 58 (“Yuzuriha’s
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`FIG. 5 shows the dummy gate region on the thick isolation oxide based on the then
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`prevalent LOCOS technology while the regions on either side are on the thin gate
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`oxide. This may then result in a higher elevation of the middle ‘DUMMY GATE
`24
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`Page 00025
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`REGION.’”); EX2008 (Brahmbhatt Dep. Tr.) (Sept. 24, 2014) at 247:4-9, 206:20-
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`207:5 (“Q. Okay. Looking at figure 8, would you agree that the top of layer 16 at what
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`you've marked M prime…is lower than the top of layer 16 at what is marked as C in
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`the figure? A. …I wi
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