UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`MACRONIX INTERNATIONAL CO., LTD., MACRONIX ASIA LIMITED,
`MACRONIX (HONG KONG) CO., LTD. and MACRONIX AMERICA, INC.
`Petitioners
`
`v.
`
`SPANSION LLC
`Patent Owner
`
`
`
`Case: IPR2014-00898
`
`
`
`PETITION FOR INTER PARTES REVIEW OF
`U.S. PATENT NO. 7,151,027
`
`
`
`
`
`Mail Stop PATENT BOARD
`Patent Trial and Appeal Board
`United States Patent and Trademark Office
`PO Box 1450
`Alexandria, Virginia 22313–1450
`Submitted Electronically via the Patent Review Processing System
`
`
`
`
`
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`MACRONIX INTERNATIONAL CO., LTD., MACRONIX ASIA LIMITED,
`MACRONIX (HONG KONG) CO., LTD. and MACRONIX AMERICA, INC.
`Petitioners
`
`v.
`
`SPANSION LLC
`Patent Owner
`
`
`
`Case: IPR2014-00898
`
`
`
`PETITION FOR INTER PARTES REVIEW OF
`U.S. PATENT NO. 7,151,027
`
`
`
`
`
`Mail Stop PATENT BOARD
`Patent Trial and Appeal Board
`United States Patent and Trademark Office
`PO Box 1450
`Alexandria, Virginia 22313–1450
`Submitted Electronically via the Patent Review Processing System
`
`
`
`
`
`
`Petition for Inter Partes Review of U.S. Patent No. 7,151,027
`(IPR2014-00898)
`
`TABLE OF CONTENTS
`
`I. MANDATORY NOTICES UNDER 37 C.F.R. § 42.8 ........................................................... 1
`
`II. PAYMENT OF FEES – 37 C.F.R. § 42.103 ........................................................................... 3
`
`III. REQUIREMENTS FOR IPR UNDER 37 C.F.R. § 42.104 .................................................... 3
`
`IV. Summary of the ’027 Patent .................................................................................................... 6
`
`V. ANalysis of ground for trial..................................................................................................... 9
`
`VI. CONCLUSION ..................................................................................................................... 24
`
`
`
`
`
`ii
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`
`
`Petition for Inter Partes Review of U.S. Patent No. 7,151,027
`(IPR2014-00898)
`
`EXHIBITS
`
`Exhibit No.
`MX027II-1001
`
`Description
`U.S. Patent No. 7,151,027
`
`MX027II-1002
`
`Declaration of Dhaval J. Brahmbhatt
`
`MX027II-1003
`
`U.S. Patent No. 6,458,655 to Yuzuriha, et al.
`
`MX027II-1004
`
`MX027II-1005
`
`MX027II-1006
`
`MX027II-1007
`
`MX027II-1008
`
`U.S. Patent Application Publication No. 2003/0042520 to
`Tsukamoto et al.
`
`Decision: Institution of Inter Partes Review in IPR2014-
`00108, Paper No. 16 (May 8, 2014)
`
`Second Joint Submission Regarding Proposed Constructions
`of Disputed Claim Terms, 337-TA-893 (Feb. 12, 2014).
`
`C.-F. Lin, et al., A ULSI shallow trench isolation process
`through the integration of multilayered dielectric process
`and chemical-mechanical planarization, Thin Solid Films,
`249-252 (1999).
`
`S. Wolf & R.N. Tauber, Silicon Processing for the VLSI
`Era: Vol. 1 – Process Technology 2d Ed. (Lattice Press
`2000).
`
`MX027II-1009
`
`CV of Dhaval J. Brahmbhatt
`
`MX027II-1010
`
`U.S. Patent No. 5,371,030 to Bergemont
`
`MX027II-1011
`
`U.S. Patent No. 4,571,819 to Rogers et al.
`
`
`
`iii
`
`
`
`Petition for Inter Partes Review of U.S. Patent No. 7,151,027
`(IPR2014-00898)
`
`
`Macronix International Co., Ltd., Macronix Asia Limited, Macronix (Hong
`
`Kong) Co., Ltd., and Macronix America, Inc. (collectively “Petitioners”) petition
`
`for Inter Partes Review (“IPR”) under 35 U.S.C. §§ 311-319 and 37 C.F.R., Part
`
`42 of claims 7 and 14 of U.S. Patent No. 7,151,027 (“the ’027 Patent”) (MX027II-
`
`1001). As shown below, there is a reasonable likelihood that Petitioners will
`
`prevail with respect to each of the challenged claims.
`
`A motion for joinder of this proceeding with IPR2014-00108 accompanies
`
`this Petition.
`
`I. MANDATORY NOTICES UNDER 37 C.F.R. § 42.8
`A. Real Parties-in-Interest
`Macronix International Co., Ltd., Macronix Asia Limited, Macronix (Hong
`
`Kong) Co., Ltd., and Macronix America, Inc. are real parties-in-interest.
`
`B. Related Matters under 37 C.F.R. § 42.8(b)(2)
`Pending Actions
`1.
`The ’027 Patent is asserted in actions styled: (1) Spansion LLC v. Macronix
`
`International Co., Ltd., et. al., Case No. 3:13-cv-03566, filed August 1, 2013, in
`
`the United States District Court for the Northern District of California; and (2) In
`
`re Flash Memory Chips and Products Containing Same, Inv. No. 337-TA-893,
`
`filed August 1, 2013, before the U.S. International Trade Commission.
`
`
`
`1
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`
`
`Petition for Inter Partes Review of U.S. Patent No. 7,151,027
`(IPR2014-00898)
`
`
`The ’027 Patent is also involved in IPR2014-00108 filed by Petitioners
`
`against Patent Owner. Trial has been instituted on claims 1-6 and 8-13 in
`
`connection with that proceeding.
`
`Prior Action
`
`2.
`The ’027 Patent was asserted by Spansion LLC against various Samsung
`
`entities in an action styled Spansion LLC v. Samsung Electronics Co., Ltd., et al.,
`
`Case No. 1:10-cv-00881 (E.D. Va.). That action is no longer pending.
`
`C. Lead and Back-Up Counsel under 37 C.F.R. § 42.8(b)(3)
`Lead Counsel
`Back-Up Counsel
`Michael M. Murray (Reg. # 32,537)
`Andrew R. Sommer (Reg. # 53,932)
`
`WINSTON & STRAWN LLP
`
`WINSTON & STRAWN LLP
`
`200 Park Ave.
`
`1700 K Street NW
`
`New York, NY 10166-4193
`
`Washington, D.C. 20006-3817
`
`Telephone: (212) 294-4700
`
`Telephone: (202) 282-5000
`
`Fax: (212) 294-6700
`
`Fax: (202) 282-5100
`
`Email: mmurray@winston.com
`
`Email: asommer@winston.com
`
`Service Information
`
`D.
`Documents may be delivered by hand to the addresses of lead and back-up
`
`counsel above. Petitioner consents to electronic service by e-mail at the above
`
`listed e-mail addresses of Lead and Back-Up Counsel.
`
`
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`2
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`Petition for Inter Partes Review of U.S. Patent No. 7,151,027
`(IPR2014-00898)
`
`
`PAYMENT OF FEES – 37 C.F.R. § 42.103
`
`II.
`
`The required fee is being paid through the Patent Review Processing
`
`System. No excess claim fees are required. The Office is authorized to charge any
`
`fee deficiency, or credit any overpayment, to Deposit Acct. No. 501814.
`
`III. REQUIREMENTS FOR IPR UNDER 37 C.F.R. § 42.104
`A. Grounds for Standing under 37 C.F.R. § 42.104(a)
`Petitioners certify that the ’027 Patent is available for IPR and that: (1) none
`
`of the Petitioners own the ’027 Patent; (2) prior to the date this Petition was filed,
`
`neither Petitioners nor any real party-in-interest filed a civil action challenging the
`
`validity of a claim in the ’027 Patent; (3) this Petition has been filed less than one
`
`year after the date on which Petitioners, a real party-in-interest, or a privy of the
`
`Petitioners were served with a complaint alleging infringement of the ’027 Patent;
`
`and (4) neither Petitioners, any real parties-in-interest, nor any privies of
`
`Petitioners, are estopped from challenging the claims on the grounds identified in
`
`this Petition.
`
`B.
`
`Identification of Challenge under 37 C.F.R. § 42.104(b) and Relief
`Requested
`
`Petitioners are requesting cancellation of claims 7 and 14 of the ’027 Patent
`
`on the following grounds:
`
`• Ground 1: Claims 7 and 14 are unpatentable as obvious under 35 U.S.C. §
`
`103(a) over Yuzuriha in view of U.S. Patent Application Publication No.
`
`
`
`3
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`
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`Petition for Inter Partes Review of U.S. Patent No. 7,151,027
`(IPR2014-00898)
`
`
`2003/0042520 A1 to Tsukamoto et al. (hereafter “Tsukamoto”) and C.F.
`
`Lin, et al..
`
`C. Claim Construction Under 37 C.F.R. §§ 42.100(b), 42.104(b)(3)
`Pursuant to 37 C.F.R. § 42.100(b), a claim in an unexpired patent is given its
`
`broadest reasonable interpretation in light of the specification. Because the claim
`
`construction standard in an IPR is different than that used in litigation, Petitioners
`
`reserve the right to present different constructions of terms in litigation under claim
`
`construction standards appropriate for those cases. See In re Am. Acad. of Sci.
`
`Tech. Ctr., 367 F.3d 1359, 1369 (Fed. Cir. 2004). Petitioner submits, for the
`
`purposes of this IPR only, and unless otherwise indicated below, the claim terms
`
`are presumed to take on their broadest reasonable meaning that the term would
`
`have to a person having ordinary skill in the art in light of the specification of the
`
`’027 Patent and that, for the purposes of this IPR, the broadest reasonable
`
`interpretation is consistent with the plain meaning of the various claim terms.
`
`The Board has already construed certain terms in the claims of the ’027
`
`Patent.1 See MX027II-1005 at 8-12. The term “poly-2 layer” was construed to
`
`mean “a polysilicon layer deposited later in time than a first polysilicon layer.” Id.
`
`
`1 Certain terms construed in connection with the Institution Decision in IPR2014-
`00108 are not germane to this petition. See MX027II-1005 at 9-10 (“stacked gate
`etch” and “second gate etch”).
`
`
`
`4
`
`
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`Petition for Inter Partes Review of U.S. Patent No. 7,151,027
`(IPR2014-00898)
`
`
`at 8 (citing MX027II-1001 at 5:11-12, 5:17-18 ). The term “poly-1 layer” was
`
`construed to mean “a first polysilicon layer.” MX027II-1005 at 9.
`
`The Board construed the phrase “etching said poly-1 layer and said poly-2
`
`layer proximate to said memory array” in claim 8 of the ’027 Patent by rejecting
`
`Patent Owner’s argument that “etching said poly-1 layer and said poly-2 layer
`
`proximate to said memory” array requires a single etching “step.” MX027II-1005
`
`at 9. The Board’s construction is consistent with the understanding of a person
`
`having ordinary skill in the art in that it was common practice to perform etching
`
`steps, including the stacked gate etch of claim 9, using multiple process steps and
`
`multiple etching gases that were tailored to etch specific layers of the
`
`semiconductor device to form the stacked gate. See, e.g., MX027II-1002 at ¶ 37;
`
`MX027II-1010 at 4:11-21 (discussing a sequence of etching poly-2, ONO, and
`
`poly-1 layers—using terms “next” and “then”—as well as selectivity during the
`
`etching steps as part of a stacked gate etch).
`
`Although not construed in the earlier Institution Decision, the phrase “such
`
`that step size is smoothed out reducing an occurrence of stringers from spacer
`
`etching,” found in claims 7 and 14, is not a limitation. The parties and the ITC
`
`Staff have agreed to such a construction in the parallel ITC investigation as well.
`
`See MX027II-1006 at 13. Instead, this limitation is an intended result of the
`
`claimed process. See, e.g., Minton v. Nat’l Ass’n of Securities Dealers, Inc., 336
`
`
`
`5
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`
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`Petition for Inter Partes Review of U.S. Patent No. 7,151,027
`(IPR2014-00898)
`
`
`F.3d 1373, 1381 (Fed. Cir. 2003) (“[A] whereby clause in a method claim is not
`
`given weight when it simply expresses the intended result of a process step
`
`positively recited); Lockheed Martin Corp. v. Space Systems/Loral, 324 F.3d 1308
`
`(Fed. Cir. 2003) (“[A] whereby clause that merely states the result of the
`
`limitations in the claim adds nothing to the substance of the claim.”); Ideal
`
`Instruments, Inc. v. Rivard Instruments, Inc., 498 F.Supp. 2d 1131, 1196 (N.D.
`
`Iowa 2007) (applying the same reasoning to a phrase beginning with “so that”); see
`
`also MPEP § 2111.04 (stating that “determination of whether such a clause is
`
`limiting depends on the specific facts of the case”). The ’027 Patent states that
`
`making the heights of the structures the same reduces step size, which in turn,
`
`reduces stringers from spacer etching. See MX027II-1001 at 2:62-66; see also
`
`MX027II-1002 at ¶ 56 n.1. Therefore, based on the specific facts presented here,
`
`the phrase “such that step size is smoothed out reducing an occurrence of stringers
`
`from spacer etching” does not limit claims 7 and 14 because it is the natural
`
`consequence of the claimed process steps.
`
`IV. SUMMARY OF THE ’027 PATENT
`The ’027 Patent describes a method for fabricating a memory device that
`
`supposedly reduces the interface area and formation of “stringer spacers.” The
`
`’027 Patent acknowledges a long-recognized goal of the semiconductor industry:
`
`decreasing component size. MX027II-1001 at 1:19-20. According to the ’027
`
`
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`6
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`Petition for Inter Partes Review of U.S. Patent No. 7,151,027
`(IPR2014-00898)
`
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`Patent, when reducing the size of “operational components” such as a memory
`
`array and “periphery components, an important consideration is the interface
`
`between the operational components and periphery components.” Id. at 1:20-24.
`
`The ’027 Patent says that “[c]urrent fabrication processes . . . form the
`
`operational components and the periphery components using separate processes,”
`
`which can result in “steps” between adjacent structures on the semiconductor
`
`device. Id. at 1:24-38. The ’027 Patent further explains that “[s]idewall spacers
`
`are commonly formed,” but when these steps exist between the periphery and
`
`memory, “stringer spacers . . . are formed in the interface area at the steps.” Id. at
`
`1:43-47. These stringer spacers can damage the device. Thus, the prior art
`
`allegedly used “silicide block[s]” fabricated over the interface area, resulting in
`
`larger interface areas, and complicating manufacturing. Id. at 1:54-62.
`
`To solve these problems with the prior art, the ’027 Patent explains how to
`
`form an interface structure in the area between the memory array core and the
`
`periphery using certain steps. MX027II-1001 at 1:66-2:12; 6:2-12. The process
`
`for creating the interface area is described as follows:
`
`First, a first gate polysilicon (poly-1) (310a, 310b), shown in green, is
`
`disposed over a substrate (300), shown in darker blue, and an isolation area (305),
`
`shown in lighter blue. MX027II-1001 at 3:50-67.
`
`
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`7
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`Petition for Inter Partes Review of U.S. Patent No. 7,151,027
`(IPR2014-00898)
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`Second, a film of dielectric material (315), shown in red, is applied over the
`
`substrate (300) and the poly-1 (310a, 310b). MX027II-1001 at 4:1-9. “In one
`
`embodiment a[n] oxide-nitride-oxide (ONO) dielectric layer is applied.”
`
`MX027II-1001 at 4:7-9.
`
`Third, a process, such as an etch-back process is then used to remove some
`
`of the dielectric (315) and poly-1 (310b). MX027II-1001 at 4:10-21.
`
`Fourth, a second polysilicon layer (poly-2) (320), shown in yellow, is
`
`deposited over the dielectric (315), shown in red, and the substrate (300), shown in
`
`blue. MX027II-1001 at 4:22-26.
`
`Fifth, a process, such as a “stacked gate etch” can be used to etch a portion
`
`of poly-1 (310a), shown in green, dielectric (315), shown in red, and poly-2 (320),
`
`shown in yellow, proximate to the memory array. This etch forms “individual
`
`transistors from the polysilicon layers,” and a distinct boundary between the
`
`memory array and interface region is created; some poly-1 (green) and poly-2
`
`(yellow) remains in the interface region following the etch. MX027II-1001 at
`
`4:27-37.
`
`Sixth, a second process, such as a “second gate etch” is used to etch a
`
`portion of the poly-2 (320), shown in yellow, proximate to the periphery, thus
`
`forming an “interface structure” (360). MX027II-1001 at 4:38-54.
`
`
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`8
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`Petition for Inter Partes Review of U.S. Patent No. 7,151,027
`(IPR2014-00898)
`
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`Finally, a film of dielectric material (345), shown in purple, is applied above
`
`the transistor (330), interface structure (360), and periphery poly-2 (340). A set of
`
`spacers (350) may be formed along the side walls of the interface structure (360),
`
`the transistor (330), and periphery poly-2 (340). MX027II-1001 at 4:55-66.
`
`V. ANALYSIS OF GROUND FOR TRIAL
`A. Ground 1: Obviousness of Claims 7 and 14 Under § 103(a) over
`Yuzuriha in View of Tsukamoto and C.F. Lin, et al.
`Summary of Relevant Teachings of Yuzuriha as Applied to
`1.
`Claims 1 and 8
`
`The Board has already instituted trial as to claims 1 and 8 based on the
`
`teachings of U.S. Patent No. 6,458,655 to Yuzuriha (“Yuzuriha”). See MX027II-
`
`1005 at 12-16, 33. Yuzuriha issued on October 1, 2002—more than one year
`
`before the ’027 Patent was filed—and therefore constitutes prior art to the ’027
`
`Patent under 35 U.S.C. § 102(b). See MX027II-1003 (cover). Yuzuriha describes
`
`a “dummy gate region” that is located between a “memory cell region” and a
`
`“peripheral circuit region,” as shown in FIG. 5 below.
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`
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`9
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`Petition for Inter Partes Review of U.S. Patent No. 7,151,027
`(IPR2014-00898)
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`
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`To create this structure, a tunneling oxide film (9) is first disposed on a
`
`substrate (1) (shown below in blue). MX027II-1003 at FIG. 6; 12:1-2. Then, a
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`first layer of polysilicon (10) (shown below in green), commonly referred to as
`
`“poly-1,” MX027II-1002, ¶ 49, is formed on the tunneling oxide film (9).
`
`MX027II-1003 . at FIG. 6; 12:3-6; MX027II-1002, ¶ 48. A “poly-poly insulation
`
`film” 11 is added above the poly-1 layer, and a layer of photoresist (15) is added
`
`above the “memory cell region” and the “dummy gate region,” the latter of which
`
`constitutes an “interface.” MX027II-1003 at 12:6-10. Since photoresist is applied
`
`only over the memory array and part of the interface, the poly-1 is etched away
`
`from the interface proximate to the periphery, as well as the periphery. See
`
`MX027II-1002, ¶ 50; MX027II-1003 at FIGS. 6 & 7.
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`
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`10
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`Petition for Inter Partes Review of U.S. Patent No. 7,151,027
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`A second polysilicon layer (13), or “poly-2” (shown in yellow), is then
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`formed on semiconductor substrate (1); the poly-2 layer is formed in, among other
`
`areas, the interface. MX027II-1003 at 12:28-30, FIG. 8; MX027II-1002, ¶ 51.
`
`An oxide film (16) is
`
`formed on the poly-2 layer (13).
`
`See MX027II-1003 at 12:28-30.
`
`The oxide film (16) is used as an
`
`etching mask, “and a memory
`
`cell’s control gate 13 and a
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`peripheral circuitry’s transistor gate 13 are patterned” and etched. See MX027II-
`
`1003 at 12:56-59; FIG. 9; MX027II-1002, ¶ 53.
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`
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`11
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`Petition for Inter Partes Review of U.S. Patent No. 7,151,027
`(IPR2014-00898)
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`
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`
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`As shown in FIG. 10, another etching step is performed to etch the poly-1
`
`layer (10) (shown in green) proximate to the memory array. MX027II-1003, FIG.
`
`10; MX027II-1002, ¶ 54. The resulting interface structure has poly-1, poly-2, and
`
`insulating film (16). See MX027II-1003 at FIGS. 5 & 10; MX027II-1002, ¶ 54.
`
`As shown in FIGS. 5, 8, and
`
`10, and described at col. 12,
`
`lines 34-55, the method of
`
`making the structure in the
`
`interface results in a “gentle
`
`step” instead of an “abrupt step
`
`variation,” and thus the heights of the adjacent structures proximate to the memory
`
`array and the periphery are generally equal. MX027II-1003 at 12:37-52;
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`MX027II-1002, ¶ 56. This resulting gentle step reduces the occurrence of stringers
`
`due to spacer etching. MX027II-1002, ¶ 56.
`
`
`
`12
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`Petition for Inter Partes Review of U.S. Patent No. 7,151,027
`(IPR2014-00898)
`
`
`Claim Charts Showing How Yuzuriha Anticipates Claims 1
`and 8 of the ’027 Patent
`
`2.
`
`As shown in the claim charts below, and adopted by the Board in its
`
`Institution Decision in IPR2014-00108, MX027II-1005 at 12-16, 33, Yuzuriha
`
`anticipates claims 1 and 8 of the ’027 Patent.
`
`Claims
`1. A method for
`fabricating a
`memory device,
`said method
`comprising:
`
`U.S. Pat. No. 6,458,655 to Yuzuriha et al. (MX027II-1003)
`“A semiconductor manufacturing method is mainly
`contemplated . . . .” MX027II-1003 at Abstract. “The present
`invention relates generally to methods of manufacturing
`semiconductor devices . . . .” Id. at 1:7-8 see also id.at 1:13-
`14; 11:41-45.
`
`forming a poly-2
`layer above a
`substrate at an
`interface between
`a memory array
`and a periphery of
`said memory
`device;
`
`“On the semiconductor substrate, a memory cell region and a
`peripheral circuitry region are provided to sandwich the
`dummy gate region.” MX027II-1003 at 11:50-52. “On
`isolating oxide film 8, a second conductive layer 13 is
`provided to cover the first conductive layer 10 and insulating
`layer 11.” Id. at 11:60-62. “[A] second polysilicon layer and
`an oxide film 16 used as an etching mask are formed on the
`semiconductor substrate 1.” Id. at 12:28-30, FIGS. 5 & 8;
`MX027II-1002, ¶¶ 45, 51.
`
`etching said poly-
`2 layer proximate
`to said memory
`array; and
`
`“As shown in FIGS. 8 and 9, oxide film 16 used as an etching
`mask is patterned and a memory cell’s control gate 13 and
`peripheral circuit’s transistor gate 13 are patterned.”
`MX027II-1003 at 12:56-59; see also id. FIGS. 5 & 8-9;
`MX027II-1002, ¶ 53.
`
`
`
`
`
`13
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`Petition for Inter Partes Review of U.S. Patent No. 7,151,027
`(IPR2014-00898)
`
`
`U.S. Pat. No. 6,458,655 to Yuzuriha et al. (MX027II-1003)
`
`Claims
`
`
`“As shown in FIGS. 8 and 9, oxide film 16 used as an etching
`mask is patterned and a memory cell’s control gate 13 and
`peripheral circuit’s transistor gate 13 are patterned.”
`MX027II-1003 at 12:56-59; see also id. FIGS. 5 & 8-9;
`MX027II-1002, ¶ 53.
`
`etching said poly-
`2 layer proximate
`to said periphery
`such that a
`portion of said
`poly-2 layer
`remains at said
`interface.
`
`
`
`
`8. A method for
`fabricating a
`memory device,
`said method
`comprising:
`
`
`“A semiconductor manufacturing method is mainly
`contemplated . . . .” MX027II-1003 at Abstract. “The present
`invention relates generally to methods of manufacturing
`semiconductor devices . . . .” Id. at 1:7-8. “The present
`invention also relates to methods of manufacturing flash
`memories . . . .” Id. at 1:13-14; see also id. at 11:41-45.
`
`forming a poly-1
`layer above a
`substrate at an
`interface between
`a memory array
`
`“On the semiconductor substrate, a memory cell region and a
`peripheral circuit region are provided to sandwich the dummy
`gate region.” MX027II-1003 at 11:50-52. “As shown in FIG.
`6 . . . on semiconductor substrate 1 a first polysilicon layer 10
`(serving as a floating gate) is etched . . . .” Id. at 12:3-6, FIG.
`
`
`
`14
`
`
`
`Claims
`and a periphery of
`said memory
`device;
`
`forming a poly-2
`layer above said
`poly-1 layer at
`said interface;
`
`Petition for Inter Partes Review of U.S. Patent No. 7,151,027
`(IPR2014-00898)
`
`
`U.S. Pat. No. 6,458,655 to Yuzuriha et al. (MX027II-1003)
`5; MX027II-1002, ¶¶ 47-49.
`
`
`“On the semiconductor substrate, a memory cell region and a
`peripheral circuitry region are provided to sandwich the
`dummy gate region.” MX027II-1003 at 11:50-52. “On
`isolating oxide film 8, a second conductive layer 13 is
`provided to cover the first conductive layer 10 and insulating
`layer 11.” Id. at 11:60-62. “[A] second polysilicon layer and
`an oxide film 16 used as an etching mask are formed on the
`semiconductor substrate 1.” Id. at 12:28-30, FIGS. 5 & 8;
`MX027II-1002, ¶ 51.
`
`
`
`etching said poly-
`1 layer and said
`poly-2 layer
`proximate to said
`memory array;
`and
`
`“As shown in FIGS. 8 and 9, oxide film 16 used as an etching
`mask is patterned and a memory cell’s control gate 13 and
`peripheral circuit’s transistor gate 13 are patterned.”
`MX027II-1003 at 12:56-59. “As shown in FIG. 10, with oxide
`film 16 as an etching mask used, poly-poly insulation film 11
`and floating gate 10 are etched only in the memory cell region.
`Thus, the FIG. 5 flash memory completes.” Id. at 12:60-63,
`FIGS. 8-10; MX027II-1002, ¶¶ 53-54.
`
`
`
`15
`
`
`
`Petition for Inter Partes Review of U.S. Patent No. 7,151,027
`(IPR2014-00898)
`
`
`U.S. Pat. No. 6,458,655 to Yuzuriha et al. (MX027II-1003)
`
`Claims
`
`“As shown in FIGS. 8 and 9, oxide film 16 used as an etching
`mask is patterned and a memory cell’s control gate 13 and
`peripheral circuit’s transistor gate 13 are patterned.”
`MX027II-1003 at 12:56-59, FIGS. 5 & 8-9; MX027II-1002, ¶
`53.
`
`
`
`etching said poly-
`2 layer proximate
`to said periphery,
`such that an
`interface structure
`including a
`portion of said
`poly-1 layer and a
`portion of said
`poly-2 layer
`remains at said
`interface.
`
`
`
`
`
`3.
`
`Teachings of the Prior Art As Applied to Claims 7 and 14
`and the Obviousness of Claims 7 and 14
`
`Claims 7 and 14 both require that “said portion of said poly-2 layer
`
`remaining at said interface is a same height as said memory array proximate to said
`
`memory array a same height as said periphery proximate to said periphery, such
`
`that step size is smoothed out reducing an occurrence of stringers from spacer
`
`
`
`16
`
`
`
`Petition for Inter Partes Review of U.S. Patent No. 7,151,027
`(IPR2014-00898)
`
`
`etching.”2 Yuzuriha discloses that the goal of fabricating the dummy gate region is
`
`to reduce “any abrupt step variation,” and that the interface structure is designed to
`
`result in “a gentle step” resulting in improvements in further photolithographic
`
`steps. MX027II-1003 at 12:37-55; MX027II-1002, ¶ 56. Despite the explicit
`
`teachings of smoothing out step-size, it is difficult to tell whether the height of the
`
`interface structure taught by Yuzuriha is the same as the memory array proximate
`
`to the memory array and the periphery proximate to the periphery. MX027II-1003
`
`at 12:37-55, FIG. 5; MX027II-1002, ¶ 56.
`
`Yuzuriha discloses a “memory cell region” and a “peripheral circuit region”
`
`that “sandwich[es]” an interface—the “dummy gate region.” MX027II-1003 at
`
`11:50-52. The memory cell region and the peripheral circuit region are isolated
`
`from one another using an “isolating oxide film,” which is formed “on” the
`
`substrate. Id. at 11:52-54, 12:1-2. Yuzuriha further discloses that a “gentle step”
`
`is formed between the memory array and the periphery, suggesting to a person of
`
`ordinary skill in the art, when taken in combination with, for example, Yuzuriha’s
`
`Figure 10, that the “isolating oxide film,” may be formed using a process such as
`
`“local oxidation of silicon,” or LOCOS. MX027II-1002, ¶¶ 58-59.
`
`2 While the “such that” clause is not limiting for these process claims, it is
`
`inherently present because the steps are smoothed out to reduce the occurrence of
`
`debris. MX027II-1002, ¶ 56 n.1.
`
`
`
`17
`
`
`
`Petition for Inter Partes Review of U.S. Patent No. 7,151,027
`(IPR2014-00898)
`
`
`The C.-F. Lin Article was published in 1999, more than one year before the
`
`filing of the ’027 Patent, and therefore constitutes prior art under 35 U.S.C. §
`
`102(b). See MX027II-1007 at 248 (showing date of 1999). As explained in the
`
`C.-F. Lin, et al. article, isolation oxides such as those made by LOCOS had been
`
`used “[f]or a long time,” and was “the standard technology to provide electrical
`
`isolation between active devices for integrated circuits.” MX027II-1007 at 248
`
`(left column). However, as semiconductor device geometries were becoming
`
`smaller and densities were increasing, “even more stringent requirements were
`
`being placed upon isolation performance, and problems with LOCOS began to
`
`surface.” Id. One such problem was “poor planarity.” Id. “In light of these
`
`limitations, an alternative process called shallow trench isolation (STI) has been
`
`pursued actively be IC manufacturers as the substitute to LOCOS for device
`
`isolation.” Id. After noting that planarization of the STI portion is “the most
`
`critical step to the success of STI,” id. at 248 (right column), the process described
`
`in the C.-F. Lin paper “produces a STI structure with a well-planarized surface
`
`and minimum amount of dishing.” Id. at 252. Thus, a person having ordinary skill
`
`in the art would have understood that, to the extent that the Yuzuriha “oxide
`
`isolating film” was raised—and not planar, resulting in a height difference between
`
`the interface and periphery on one hand, and the interface and the memory array on
`
`the other, a person of ordinary skill in the art would have seen the obvious benefits
`
`
`
`18
`
`
`
`Petition for Inter Partes Review of U.S. Patent No. 7,151,027
`(IPR2014-00898)
`
`
`of substituting STI in place of the oxide structure disclosed in Yuzuriha because
`
`(1) it was a known substitute for performing electrical isolation between active
`
`areas on integrated circuits, see, e.g., MX027II-1007 at 248 (left column);
`
`MX027II-1002, ¶ 59, and (2) STI had advantages over local oxidization of silicon
`
`in that it could be planarized, thus reducing the “gentle step,” and furthermore
`
`eliminated problems known as “lateral encroachment” of the oxide (a phenomenon
`
`called “bird’s beak”), MX027II-1007 at 248 (left column); MX027II-1002, ¶ 60;
`
`MX027II-1011 at 1:25-30.
`
`Moreover, the evening of heights between a “memory cell forming region”
`
`and a “peripheral circuit forming region” using a polysilicon interface structure is
`
`described in Tsukamoto. Tsukamoto was published March 6, 2003, more than 1
`
`year before the ’027 Patent was filed, and thus constitutes prior art under 35 U.S.C.
`
`§ 102(b). See MX027II-1004 (item 43 on cover). Tsukamoto describes a
`
`semiconductor memory device that uses a structure formed at the “outer periphery
`
`portion of the memory cell array” to (1) diminish “the influence of dust parties
`
`developed during the formation of memory cells” and (2) “eliminating the
`
`difference in height between the memory cell forming region and the peripheral
`
`circuit forming region.” MX027II-1004 at ¶ [0058]. This structure is formed on a
`
`shallow trench isolation area (6) which is subjected to chemical mechanical
`
`polishing in order to allow the isolation material to be “buried in the interior of the
`
`
`
`19
`
`
`
`Petition for Inter Partes Review of U.S. Patent No. 7,151,027
`(IPR2014-00898)
`
`
`trench,” and then used to isolate different elements. Id. at ¶¶ [0002], [0046]. The
`
`layout of the device is shown in the combined Figures 1 and 2, reproduced below
`
`with highlighting and red lines added:
`
`A structure formed at the “outer periphery portion of the memory cell array
`
`by the same layer as the control gates CG,” id. at ¶ [0058], and also includes
`
`
`
`20
`
`
`
`
`
`Petition for Inter Partes Review of U.S. Patent No. 7,151,027
`(IPR2014-00898)
`
`
`floating gate polysilicon (“FG”), id. ¶ [0087], and ONO film (21) [0076]. In this
`
`regard, the DSG structure shown in Tsukamoto is analogous to the “dummy gate
`
`region” of Yuzuriha. Moreover, both gate (“G”) and floating gate memory cell are
`
`formed over oxide layers 9 and 9b, as shown in Figure 2. E.g., MX027II-1004 at
`
`FIG. 2 (elements 9, 9b); ¶¶ [0049], [0053], [0074], [0077].
`
`Based on the foregoing, it would have been obvious to a person having
`
`ordinary skill in the art to modify Yuzuriha’s structure to (1) use a planarized oxide
`
`isolation area such as a shallow trench isolation area to isolate the memory array
`
`and the periphery, and (2) to include a dummy gate structure that eliminates “the
`
`difference in height between the memory cell forming region and the peripheral
`
`circuit forming region,” because such a configuration would have furthered
`
`Yuzuriha’s goals of reducing—and in this case eliminating—a height differential
`
`between adjacent components and would have further improved “subsequent
`
`photolithography, processing and the like,” MX027II-1003 at 12:52-55. See also
`
`MX027II-1002, ¶¶ 56-57, 63-65.
`
`More specifically, a person having ordinary skill in the art would have
`
`appreciated that a raised isolation area under the “dummy gate region” would have
`
`been a problem for making devices in a technology generation below 0.25 μm, as
`
`disclosed by the C.-F. Lin article. MX027II-1006 at 248 (left column). Thus, one
`
`way to solve that problem, as discussed in the C.-F. Lin article, was to use an STI
`
`
`
`21
`
`
`
`Petition for Inter Partes Review of U.S. Patent No. 7,151,027
`(IPR2014-00898)
`
`
`followed by a chemical mechanical polishing step to ensure that the surface
`
`remained planar, rather than having the seemingly raised oxide disclosed in
`
`Yuzuriha. Id.; see also MX027II-1002, ¶¶ 59-60, 63, 65. This STI process is also
`
`employed by Tsukamoto. MX027II-1004 at ¶¶ [0002], [0046]. Indeed, STI was
`
`becoming a well-known substitute for prior art LOCOS technology which had been
`
`the “standard technology” for isolating adjacent electrical elements. MX027II-
`
`1006 at 248 (left column). Thus, when it came to creating an isolation area under a
`
`dummy structure residing between a memory array and a periphery as disclosed in
`
`Yuzuriha, there were a limited number of known solutions that yielded predictable
`
`results. See KSR Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 421 (2007) (“When there
`
`is a design need or market pressure to solve a problem and there are a finite
`
`number of identified, predictable solutions, a person of ordinary skill has good
`
`reason to pursue known options within his or her technical grasp. If this leads to
`
`the anticipated success, it is likely the product not of innovation but of ordinary
`
`skill and common sense.”); MX027II-1002, ¶¶ 64-65. Indeed, that Yuzurhia’s
`
`seemingly raised isolation area could be replaced by a planar STI area over which
`
`a dummy structure can be formed is taught expressly in Tsukamoto as discussed
`
`herein.
`
`Additionally, eliminating the height difference as disclosed in the
`
`Tsukamoto reference, MX027II-1004, ¶ [0058], would have had well-understood
`
`
`
`22
`
`
`
`Petition for Inte
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