United States Patent [19}
`Rogers et a1.
`
`[11]
`[45]
`
`Patent Number:
`Date of Patent:
`
`4,571,819
`Feb. 25, 1986
`
`[54]
`
`[75]
`
`[73]
`[21]
`1221
`[51]
`[52]
`
`[58]
`
`METHOD FOR FORMING TRENCH
`ISOLATION STRUCTURES
`
`Inventors: Steven H. Rogers, Midwest City,
`Okla.; Randall S. Mundt, Colorado
`Springs; Denise A. Kaya, Woodland
`Park, both of Colo.
`
`Assignee: NCR Corporation, Dayton, Ohio
`
`Appl. No.: 667,181
`
`Filed:
`
`Nov. 1, 1984
`
`Int. Cl!‘ ........................................... .. H01L 21/95
`
`US. Cl. . . . . . . . . . . . .
`
`. . . . .. 29/576 W; 29/580;
`
`148/1.5; 148/191; 148/DIG. 43; 148/DIG. 50;
`148/DIG. 133; 357/49; 357/50; 357/54;
`156/653; 427/93
`Field of Search .............. .. 29/576 W, 576 T, 580;
`148/1.5, 191, DIG. 43, DIG. 50, DIG. 85,
`DIG. 86, DIG. 133; 357/49, 50, 54; 156/653,
`657; 427/86, 93, 94, 95
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`4,104,086 8/1978
`4,356,211 10/1982
`4,396,460 8/ 1983
`4,404,735 9/1983
`4,506,434 3/ 1985
`4,519,128 5/1985
`
`Bondur et a1. .
`
`Riseman .
`Tamaki et a1. ............ .. 29/576 W X
`Sakurai .
`Ogawa et a1. ............. .. 29/576 W X
`Chesebro et al.
`.... .. 357/49 X
`
`FOREIGN PATENT DOCUMENTS
`
`0113248 7/1982 Japan ............................. .. 29/576 W
`0050540 3/ 1984 Japan ......... ..
`8200782 9/ 1983 Netherlands ................... .. 29/576 W
`
`OTHER PUBLICATIONS
`Abbas, S. A., “Recessed Oxide Isolation Process” in
`IBM Technical Disclosure Bulletin, vol. 20, No. 1, Jun.
`1977, pp. 144-145.
`Rung et a1., “Deep Trench Isolated CMOS Devices”,
`IEDM 82, pp. 237-240.
`Kurosawa et al., “A New Bird’s-Beak Free Field Isola
`tion Technology for VLSI Devices”, IEDM 81, pp.
`384-387.
`Primary Examiner-Brian E. Hearn
`Assistant Examiner—A1an E. Schiavelli
`Attorney, Agent, or Firm-Wilbert Hawk, Jr.; Casimer
`K. Salys
`ABSTRACT
`[57]
`A method for forming trench isolation oxide using
`doped silicon dioxide which is re?owed at elevated
`temperatures to collapse any voids therein and produce
`surface planarity. An underlying layered composite
`selected from oxide, polysilicon and silicon nitride per
`mits the formation and re?ow of the doped isolation
`oxide and remains in place in the trench to contribute to
`the trench isolation structure.
`
`16 Claims, 10 Drawing Figures
`
`28
`
`'/29
`
`29\
`
`28
`
`mums-m
`POLY-l1
`OXIDE-l6
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`
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`NITRlDE-l?
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`
`IPR2014-00898
`Exhibit MX027II-1011, p. 1
`
`

`
`US. Patent Feb. 25, 1986
`
`Sheetlof3
`
`4,571,819
`
`FIG- I
`
`PRIOR ART
`
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`
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`4
`
`INSIDE
`OXIDE ANGLE I“)
`
`II/\— INSIDE OXIDE ANGLE
`I
`
`ORIGINAL GROOVE ANGLE
`
`0 _ _ _ _ _ _ __
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`""m
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`
`IPR2014-00898
`Exhibit MX027II-1011, p. 2
`
`

`
`U.S. Patent
`
`Feb. 25, 1986
`
`Sheet2of3
`
`4,571,819
`
`IPRZO1 -
`Exhibit MXO27||—10
`
`898
`, p. 3
`
`IPR2014-00898
`Exhibit MX027II-1011, p. 3
`
`

`
`U.S. Patent
`
`Feb. 25, 1986
`
`Sheet 3 of3
`
`4,571,819
`
`|PR2014—
`Exhibit MXO27||-101 ,
`
`8
`.4
`
`IPR2014-00898
`Exhibit MX027II-1011, p. 4
`
`

`
`1
`
`METHOD FOR FORMING TRENCH ISOLATION
`STRUCTURES
`
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`BACKGROUND OF THE INVENTION
`This invention relates to techniques for electrically
`isolating semiconductor devices and components in
`monolithic integrated circuits. In particular, the inven
`tion is a method for forming void-free, planarized di
`electric trench structures. The method uses doped oxide
`re?ow to provide a void-free planar isolation layer and
`a multiple underlayer which functions as an etch stop
`and dopant/oxidation barrier.
`Dielectric isolation techniques have been the pre
`ferred technology for isolating integrated circuits and
`their constituent devices and elements, at least in part
`because of the ability to closely pack the isolation di
`electric and the circuit elements. Integrated circuit iso
`lation by the so-called local oxidation of silicon
`(LOCOS) has been known for a number of years, as
`have the attendant problems. The well-known limita
`tions of the LOCOS process include at least three fac
`tors which may constrain the process from applicability
`to future small geometry, highly dense LSI and VLSI
`structures. These limitations are, ?rst, the formation of 25
`the so-called bird’s beak oxide con?guration and the
`associated encroachment of the ?eld oxide beneath the
`oxidation mask. Encroachment by the bird’s beak oxide
`limits the percentage of chip surface area which is avail
`able for device formation. Secondly, the limited thick
`ness results in undesirably high circuit capacitances.
`Third, the characteristic non-planar surface topography
`makes it dif?cult to perform the increasingly high reso
`lution photolithographic operations which are required
`to fabricate VSLI circuits. In turn, the decreased resolu
`tion increases the minimum feature sizes and minimum
`tolerances and, as a consequence, decreases the achiev
`able device densities.
`The use of LOCOS isolation has persisted, however,
`because of the past shortcomings of the available substi
`tute isolation technologies. Typical trench isolation
`processes involve etching grooves about 1 to 6 microns
`deep into the semiconductor substrate, filling the
`grooves with a suitable dielectric and performing a
`planarization operation. The dielectric material typi
`cally is undoped silicon dioxide or polysilicon. Typical
`prior art approaches are discussed, for example, in
`Rung, Momose and Nagakubo, “Deep Trench Isolated
`CMOS Devices”, IEDM 82, pp. 237-240. The Rung et
`al. article discusses a trench isolation process which
`involves oxidizing the silicon substrate trench sidewalls,
`?lling the trench with polysilicon or deposited oxide,
`etching the poly/oxide, then capping the structure with
`oxide. Another typical trench isolation approach is
`described in the article “A New Bird’s-Beak Free Field
`Isolation Technology For VLSI Devices”, by
`Kurosawa, Shibata and Iizuka, IEDM 81, pp. 384-387.
`The Kurosawa et a1. technique involves the selective
`etching of stressed silicon dioxide following confomal
`deposition, combined with a lift-off of the silicon diox
`ide over the active regions.
`In particular, trench isolation technology has the
`inherent potential advantages of small width-to-depth
`ratios, relative process simplicity, well-de?ned vertical
`wall isolation regions and surface planarity. Like other
`VSLI features, however, the width of isolation trenches
`must be scaled downward to near micron and even
`submicron size to achieve the densities required in
`
`4,571,819
`2
`VSLI and future monolithic integrated circuit technol
`ogies. Unfortunately, it becomes increasingly dif?cult
`to completely ?ll the narrow, yet relatively deep trench
`con?gurations which are used for VSLI isolation. The
`resulting tendency to form voids is well-known and is
`shown, for example, by the data of Bondur et al, US.
`Pat. No. 4,104,086. Bondur et al. discloses a process for
`eliminating voids by precisely tapering the walls of the
`trenches, which tapers vary in relation to the sizes of the
`trenches. FIG. 1 illustrates the data of Bondur et al.,
`which show that for vertical side wall trenches, the
`deposited silicon dioxide forms negative sloping side
`walls and, thus, voids.
`Several approaches have been proposed which have
`as their purpose the control or elimination of such
`voids.
`For example, Riseman, US. Pat. No. 4,356,211, forms
`a composite dual-oxide trench isolation structure in
`which a ?rst oxide layer is formed, then a layer of
`polysilicon is deposited, anisotrophically etched, and
`heavily doped at the upper edge of the trench to accel
`erate silicon dioxide formation at such upper edge.
`Thereby the voids are sealed by the differential oxida
`tion rate of the polysilicon. Clearly the parameters of
`the Riseman process do not provide for applications in
`which trenches of varying dimension are being pro
`cessed simultaneously.
`The above-mentioned Bondur et al. US. Pat. No.
`4,104,086 uses tapered trench sidewalls to control the
`depth of isolation oxide voids relative to the substrate
`surface in a silicon substrate which has a highly doped
`near-surface region. Brie?y, the Bondur et al process
`involves (l) forming the trench to a tapered pro?le, as
`by the use of reactive ion etching (RIE); (2) growing a
`thin layer of thermal oxide in the trench outline; (3)
`depositing CVD oxide; (4) etching back the CVD oxide
`using RIE; and (5) optionally, annealing in steam at 900°
`to 950° C. to enhance the “quality” of the silicon diox
`ide. The data disclosed in the Bondur et a1 patent indi
`cate the vertical walls (which, of course, are desirable
`for density and resolution) inherently product voids in
`the deposited silicon oxide (see FIG. 1 herein). Also, the
`voids are buried deeper in the oxide relative to the
`substrate surface as the trench width increases and the
`taper increases. Conversely, the voids are formed closer
`to the surface and to exposure by the planarization
`etch-back in the case of narrower, vertical grooves.
`Sakurai, U.S. Pat. No. 4,404,735, discloses a process
`for forming trench isolation structures. Initially, dry
`etching such as plasma etching, reactive sputter etching
`or ion beam etching is used for form the trench. The
`trench is then covered with a thin layer of deposited
`silicon dioxide which is formed to a thickness of be
`tween 500 to 1,000 angstroms to prevent substrate heat
`ing by the subsequent laser re?ow process, prevent
`doping of the substrate from the isolation layer, and to
`isolate the silicon isolation layer from the substrate.
`Next, a CVD layer is formed to a thickness which is less
`than the trench depth and less than one-half the trench
`width using silicon or doped glass (phosphosilicate
`glass, PS6). The PSG/ silicon is subsequently re?owed
`by laser heating. Essentially, the Sakurai process is a
`laser re?ow process for filling narrow trenches from a
`thin silicon or PS6 layer. In other words, the trench
`?lling layer is formed to an initial shallow thickness
`within the trench and laser heating is used to redistrib
`ute material from outside the trenches into the trenches.
`
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`65
`
`IPR2014-00898
`Exhibit MX027II-1011, p. 5
`
`

`
`5
`
`4,571,819
`3
`Apparently, the 500 to 1,000 Angstrom thickness of the
`blocking silicon dioxide layer is critical in that a mini
`mum thickness is required to perform the heat-shielding
`and dopant-blocking functions, while, presumably, a
`maximum thickness is necessary for consistency with
`the state depth and width dimensions.
`In view of the above-discussed constraints and dif?
`culties associated with conventional trench isolation
`processes and structures, it is an object of the present
`invention to provide a method for forming a trench
`isolation structure which is free of voids.
`Another object of the present invention is to provide
`a method for forming such a trench isolation structure
`which has planar surface topography over the trenches
`as well as the active regions.
`Still another object of the present invention is to
`provide a process for forming void-free trench isolation
`structures which are suitable for use in high density
`monolithic integrated circuit structures such as VLSI
`circuits.
`20
`
`In an alternative aspect of the present invention, the
`polysilicon etch stop layer is formed on the silicon ni
`tride blocking layer, rather than vice versa. This ap
`proach eliminates possible interaction between the glass
`isolation layer and the nitride, which can occur when
`the nitride is formed on the polysilicon. Typically, an
`oxidizing re?ow ambient is not used with this poly-on
`nitride con?guration, because the resulting polysilicon
`oxidation can consume the poly etch stop layer.
`In still another alternative, a poly-nitride-poly-oxide
`sequence of layers can be used. The outermost poly
`layer in this con?guration acts as a passivation barrier
`over the nitride to eliminate nitride reaction with the
`glass isolation layer. When re?ow is done in an oxidiz
`ing ambient, oxidation of the poly helps to ?ll in the
`trench. The nitride blocks oxidation of the innermost
`poly layer during re?ow and limits any poly consump
`tion to the outermost poly layer. In blocking oxidation
`of the innermost poly layer, the nitride permits the use
`of an oxidizing re?ow ambient.
`
`25
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`
`BRIEF SUMMARY
`In one aspect, the method of the present invention
`comprises the steps of forming, in a substrate, a trench
`which has substantially vertical sidewalls; forming a
`thin, stress relief oxide layer in the trench outline; form
`ing an etch-stop buffer layer in the trench outline; form
`ing a dopant-blocking and oxidation blocking layer in
`the trench outline; forming a doped dielectric isolation
`.layer on the structure; heating the resulting structure to
`reflow the dielectric collapse voids therein and smooth
`. the outer surface of the isolation layer; etching the di
`electric isolation layer to a level at or below the etch
`stop buffer layer; heating the structure for a time suffi
`cient to outgas the dopant, while at the same time such
`blocking layer prevents diffusion of the dopant into the
`underlying structure; and selectively etching the etch
`--stop buffer layer, as required, preparatory to further IC
`fabrication.
`Optionally for relatively wide trenches (typically
`40
`those wider than 5 microns), a polymer such as PMMA
`(polymethylmethacylate) may be formed on the dielec
`tric after the re?ow step to facilitate forming a smooth
`outer surface topology of the complete wafer.
`In speci?c aspects of the preferred working embodi
`ment, the stress relief layer is thermal oxide which is 300
`to 1,000 Angstroms thick. The etch-stop layer is depos
`ited polycrystalline silicon (polysilicon) which is 1,000
`to 3,000 Angstroms thick. The blocking layer is silicon
`nitride formed to a thickness of 1,000 to 3,000 Ang
`stroms thick to prevent doping and oxidation of the
`underlying polysilicon and other structural layers. The
`dielectric isolation layer is chemical vapor deposited
`(CVD) silicon oxide approximately 2.5 microns thick
`which contains approximately 3 to 9 weight percent
`dopants such as phosphorus or boron to provide the
`requisite re?ow characteristics. Reflow itself is done at
`950" to 1,150° C. in a steam or nitrogen ambient for a
`period of approximately 30 minutes to four hours, de
`pending upon the thickness of the dielectric isolation
`layer and the dimensions of the trench. The etch-back
`and selective etch can be done by conventional RIE
`techniques. The outgassing step involves heating at
`about 1,000’ to l,200° C. in a nitrogen ambient for two
`to eight hours to deplete the dielectric surface of dopant
`and, optionally, to drive in surface adjacent diffusion
`regions such as the p/n wells used in CMOS integrated
`circuits.
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`DESCRIPTION OF THE DRAWINGS
`FIG. 1 illustrates prior art data which demonstrates
`that formation of dielectric such as silicon dioxide in
`vertical sidewall trenches produces a negatively sloped
`dielectric walls and voids.
`FIGS. 2 through 7 are cross-sectional representations
`of a preferred process for fabricating the void-free sili
`con dioxide composite trench isolation structures of the
`present invention.
`FIG. 3A and 3B are cross-sectional representations of
`alternative composite structures which may be used in
`the structure and process of the present invention.
`FIG. 8 is an exemplary IC structure based upon the
`trench isolation process and structure of the present
`invention.
`
`DETAILED DESCRIPTION
`The present invention is a trench isolation technology
`which utilizes the re?ow characteristics of doped silica
`glass at elevated temperatures to compensate for the
`tendency for form voids in the trenches of varying
`dimensions which are required for small geometry,
`high-density, monolithic integrated circuits. The pro
`cess therby provides a high-quality, void-free planar
`trench isolation structure. In one aspect, the use of re
`?owed doped silica glass is made possible by the prelim
`inary formation of a silicon nitride barrier layer which
`prevents doping and oxidation of the underlying struc
`ture, particularly the semiconductor substrate; and un
`derlying polysilicon layer which provides an etch-stop
`during the oxide planarization etchback; and an under- _
`lying silicon oxide layer which decreases stress in the
`novel four-layer composite trench structure. The pro
`cess is believed unique in its approach to the use of
`vertical sidewalls in trench structures of various widths.
`These vertical sidewalls minimize the effective wafer
`area allocated to the trenches. In addition, the process
`results in a planar wafer surface suitable for use with
`high resolution photolithography. Foremost, these ob
`jectives are obtained through the use of conventional
`fabrication techniques, and without imposing elaborate
`trench shape or dimensional controls.
`Referring to FIG. 2, there is shown a semiconductor
`substrate 10, typically of silicon. As an example, for
`NMOS integrated circuits the substrate would be p
`silicon having a resistivity of l to 20 ohms - centimeter.
`A typical CMOS starting structure would be an n—
`
`IPR2014-00898
`Exhibit MX027II-1011, p. 6
`
`

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`15
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`4,571,819
`5
`epitaxial layer on an n + substrate. The substrate 10 can
`be masked using any of a number and combinations
`thereof, as well as by the exemplary photoresist mask
`which is shaped by exposure to ultraviolet radiation. In
`addition, mask compositions suitable for X-Ray or ion
`beam exposure can be used. Using photoresist, a layer
`thereof is formed on the substrate 10, then is exposed
`and developed to produce the etch mask 11 which has
`openings 12 corresponding to the desired trench width.
`Note that the dimensions of the drawings herein are
`chosen for convenience of representation, are not to
`scale, and according to the invention are subject to
`variation.
`Subsequently, the trench is etched to a typical depth
`of l to 6 microns, preferably using an anisotropic etch
`process to produce a trench 13 having vertical sidewalls
`14-14. One preferred etch process is reactive ion etching
`using a fluorine etchant gas such as nitrogen tri?uoride
`(NF3). In reactive ion etching, the mechanical compo
`nent or ion bombardment component 15 dominates the
`chemical reaction component and provides the vertical
`sidewalls which are desirable in order to provide suffi
`cient dielectric width for effective isolation without
`lateral encroachment into active device regions.
`Referring to FIG. 3, after the trench etching, the
`mask 11 is removed such as by a plasma ashing process.
`Next, a stress relief oxide layer 16 is formed to a thick
`ness of about 300 to 1,000 Angstroms by thermal oxida
`tion in steam at 950° to l,l50° C., or by chemical vapor
`deposition (CVD). The oxide layer 16 provides stress
`relief between the silicon substrate 10 and the overlying
`layer, in this instance a polycrystalline silicon etch-stop
`layer 17 which is formed to a thickness of about 1,000 to
`3,000 Angstroms, for example, by the LPCVD tech
`nique (low pressure chemical vapor deposition) using
`silane in argon and hydrogen at 600°—800° C. The poly
`layer 17 prevents etching of the underlying structure,
`particularly the substrate, during the planarization pro
`cess. The primary purpose of the oxide layer 16 is stress
`relief of the substrate 10, to preserve the electrical integ
`rity of the substrate.
`Referring still further to FIG. 3, the silicon nitride
`barrier layer 18 is then formed to a thickness of 1,000 to
`2,500 Angstroms on the polysilicon layer 17, preferably
`by low pressure chemical vapor deposition using silane
`and ammonia and a reaction temperature of about 800°
`C. The silicon nitride layer 18 provides a barrier to
`doping and oxidation of the underlying structure, par
`ticularly substrate 10, during subsequent processing.
`Thereby, silicon nitride layer 18 permits formation and
`re?ow of the doped isolation oxide and subsequent
`outgassing of the dopant in the isolation oxide without
`affecting the substrate or polysilicon or the rest of the
`underlying structure.
`Next, referring to FIG. 4, the doped silicon dioxide
`glass layer 19 can be formed to a thickness of about 2.5
`microns containing 3-9 weight percent of impurities
`such as phosphorus or boron, e.g., using the low pres
`sure chemical vapor deposition technique. Typically,
`the reactants silane and oxygen are used, with phos
`phine as the n-type dopant, and a reaction temperature
`of about 500°-800° C.
`As shown in FIG. 4, the resulting silicon dioxide
`layer 19 includes voids 21-21, which is typical when
`silicon dioxide or other dielectric layers are formed in
`deep trenches. The voids occur because the arrival
`angles of the depositing silicon dioxide at the botton 22
`and sidewalls 14-14 of the trench are small in compari
`
`6
`son to the arrival angle at the top edges 23-23 of the
`trench. This produces relatively low deposition growth
`rates at the bottom and sides in comparison to the top
`and edge. The deposition rate differential produces the
`negatively sloped sidewalls which are evidenced by the
`data of FIG. 1, with the result that the fast growing
`oxide in the edge regions 23-23 closes up the opening of
`the trench before the bottom regions are ?lled. The
`resulting voids 21-21 are not ?lled in by subsequent
`oxide growth or by the application of planarization
`materials such as polymer layers. The voids would be
`exposed during the subsequent etchback which is used
`to planarize the doped glass, creating an open recepta
`cle for process chemical or impurities and allowing
`subsequently deposited metallization to flow into the
`voids and short other devices and components along the
`trench.
`.,
`In the present process, the doped glass is melted and
`re?owed by applying a temperature of about 950° to
`l,l50° C. in steam (oxidizing) or nitrogen (non-oxidiz
`ing) ambient for about 30 minutes to four hours depend
`ing upon the glass thickness and the trench dimensions.
`See FIG. 5. The range of times results from the faster
`re?ow which occurs as the process temperature is in
`creased and from the requirement of longer processing
`times for thicker silicon dioxide layers 19. This process
`collapses the voids 21-21 and, for trench width dimen
`sions of up to about 5 microns, re?ows the upper sur
`face 26 of the glass to a substantially level topography.
`During the glass deposition and re?ow process steps,
`the silicon nitride layer 18 provides a barrier to oxida
`tion and doping of the underlying polysilicon layer 17.
`For trench widths _Z. 5 microns, planarization is aided
`by depositing after the re?ow a layer 27 of polymer
`such as PMMA to a thickness which is appropriate to
`the particular trench depth and width being used. It
`should be noted that one of the advantages of the pres
`ent process is its adaptability to a wide range of trench
`dimensions, e.g., trench widths of one micron to 50
`microns. According to this embodiment, planarization
`of the underlying glass is carried out by using an etch
`which removes PMMA and glass at substantially equal
`rates.
`Next, as shown in FIG. 6, the silicon dioxide isolation
`layer 19 is etched back so that the surface 28 of the
`resulting glass ?eld isolation regions 19-19 of the trench
`structure 29-29 is level with or below the surface of the
`polysilicon etch-stop/buffer layer 17. The etch can be
`done using a selective wet chemical etchant such as
`buffered hydrogen ?uoride, or using dry etching such
`as reactive ion etching with CHF3 etchant gas. As
`shown in FIG. 6, the use of an RIE oxide etch also
`removes the silicon nitride layer 18 outside the trench
`con?nes. If the optional polymer layer has been used, it
`can be removed using the same reactive ion etching
`process which is applied to remove the silicon dioxide.
`Preferably, the etchant used does not attack poly, so
`that the polymer 27, oxide 19 and nitride 18 can be
`etched using the poly as an etch stop and thereby pre
`vent overetching into regions such as the active regions
`31.
`The next step is to outgas the phosphorus or boron
`dopant from the trench oxide 19-19 at a temperature of
`about l,000° to 1,200“ C. in a nitrogen ambient for about
`two to eight hours. This step depletes the surface of the
`glass of the dopant and may also be used, for example,
`for the well drive-in of CMOS integrated circuits. Dur
`ing the outgassing thermal cycle, the silicon nitride
`
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`IPR2014-00898
`Exhibit MX027II-1011, p. 7
`
`

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`4,571,819
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`layer again serves as a barrier to prevent doping or
`oxidation of the underlying trench structure including
`the substrate. It is no doubt recognized that even small
`amounts of dopant diffused through the barrier into
`silicon substrate 10 create parasitic current leakage
`paths.
`Next, and referring to FIG. 7, the polysilicon layer 17
`is removed from the active regions such as 31-31. The
`polysilicon can be removed using reactive ion etching
`or by wet chemical etching. Standard integrated circuit
`processing may then proceed.
`The resulting trench structures 29-29 shown in FIG.
`7 form the narrow, yet relatively deep, vertical side
`wall, void-free structures which are necessary for small
`geometry, high-density, integrated circuits. In addition,
`the silicon nitride blocking layer 18, the polysilicon
`etch-stop/buffer layer 17 and the stress relief oxide
`layer 16 remain in place and contribute to the dielectric
`isolation. Foremost, the structure is created without
`critical reliance on exotic equipment or highly re?ned
`trench shape control procedures.
`In the alternative embodiment of the invention shown
`in FIG. 3A, the polysilicon etch-stop layer 47 is formed
`on the silicon nitride blocking layer 48, rather than vice
`versa. This poly-overnitride approach eliminates possi
`ble interaction between the glass isolation layer 19 and
`the nitride, which can occur when the nitride is formed
`on the poly (see FIGS. 3 and 4). Typically, an oxidizing
`re?ow ambient is not used with the poly-on-nitride
`con?guration of FIG. 3A, because the resulting polysili
`con oxidation can consume the poly etch-stop layer 17.
`Otherwise, the fabrication process for the poly-nitride
`oxide composite of FIG. 3A is similar to that described
`relative to the nitride-poly-oxide composite of FIG. 3
`with the exception that the nitride 48 is under the poly
`etch-stop layer 47 and thus typically cannot be removed
`during the etch back of glass 19. Instead, the etching
`sequence is glass 19, poly 47 and then nitride 48.
`The poly 47, nitride 48 and oxide 16 of FIG. 3A
`perform the same functions—-etch-stop, oxidation and
`dopant blocking, and stress relief—as do the poly 17,
`nitride 18 and oxide 16 of FIG. 3.
`Referring to FIG. 3B, in still another alternative em
`bodiment of the present invention, a poly-nitride-poly
`oxide sequence of layers is used. Here the outermost
`poly layer 47 acts as a barrier for the nitride 18 to elimi
`nate any nitride reaction with the glass isolation layer
`19, e.g., during the oxide re?ow. Also, during re?ow in
`an oxidizing ambient, oxidation of the poly 47 helps ?ll
`in and level the trench structures. The nitride 18 in turn
`blocks oxidation of the innermost poly layer 17 and
`thereby limits any poly consumption during the re?ow
`step to the outermost poly layer 47. Thus, the nitride
`layer 18 preserves the innermost poly layer 17 and per
`mits the use of an oxidizing ambient during re?ow. The
`result is that the nitride 18 and poly 17 perform the same
`respective oxidation and dopant blocking and etch-stop
`functions as do the nitride 18 and poly 17 in FIG. 3. The
`fabrication process for the polynitride-poly-oxide com
`posite structure involves obvious modi?cations of the
`nitride-poly fabrication of FIG. 3, involving primarily
`the addition of a second poly CVD step. Typically, if
`poly 47 is not consumed during the re?ow step, the
`glass 19, poly 47, nitride 18 and poly 17 layers are re
`moved sequentially. If the poly 47 is totally consumed
`during the re?ow, the removal sequence for the FIG. 3
`structure can be used.
`
`55
`
`60
`
`65
`
`8
`Referring to FIG. 8, there is shown one example of a
`MOSFET structure based upon the trench isolation
`structures 29 of the present invention. In the illustrated
`case, an NMOS FET of a complementary structure is
`shown formed in the p-well 33 of an n-type epitaxial
`layer 34. The FET includes source and drain diffusions
`36 and 37 and LDD implants 38, all of which are self
`aligned with the polysilicon gate 39, as well as gate
`sidewall spacers 41, interlevel dielectric 42 and alumi
`num interconnects 43. Quite obviously, this is only one
`possible application among the various NMOS, PMOS,
`CMOS, bipolar and other applications of the present
`trench isolation structure and process.
`Having thus described preferred and alternative ap
`proaches for implementing our process for forming
`doped oxide ?lled trenches for semiconductor device
`isolation, what is claimed is:
`1. A process for forming a composite trench isolation
`structure in a substrate, comprising: forming a trench in
`the substrate; forming a polysilicon etch-stop layer on
`the trench walls; forming an oxidation-and dopant
`blocking silicon nitride layer on the etch-stop layer;
`?lling the trench will silicon dioxide doped to approxi
`mately three to nine weight percent of n-type or p-type
`impurities; heating the resulting structure for a time
`suf?cient to re?ow the oxide to thereby collapse voids
`therein and provide a relatively smooth upper surface;
`etching back the oxide to remove the oxide outside the
`trench areas; heating the resulting structure to outgas
`the impurity dopant from the surface-adjacent region of
`the oxide; simultaneously or separately to the oxide
`etch-back step, removing the nitride blocking layer
`outside the trench; and removing the etch-stop layer
`from at least selected regions outside the trench;
`whereby the nitride blocking layer prevents oxidation
`and doping the underlying structure during the re?ow
`and outgassing steps and the polysilicon layer prevents
`etching of the underlying structure during the oxide and
`nitride removal.
`2. The process of claim 1 wherein prior to the forma
`tion of the etch-stop layer, a silicon dioxide stress relief
`layer is formed on the trench walls.
`3. The process of claims 1 or 2, further comprising
`forming a second layer of polysilicon over the nitride
`prior to forming the silicon dioxide isolation layer, the
`second polysilicon layer preventing interaction be
`tween the nitride and the oxide isolation layer during
`the re?ow step; and the process still further comprising
`removing the second poly layer as required after re
`moval of the oxide isolation layer.
`4. A process for forming a composite trench isolation
`structure in a substrate, comprising: forming a trench in
`the substrate; forming an oxidation-and dopant-block
`ing silicon nitride layer on the trench walls; forming a
`polysilicon etch-stop layer on the blocking layer; ?lling
`the trench with silicon dioxide doped to approximately
`three to nine weight percent of n-type or p-type impuri
`ties; heating the resulting structure for a time suf?cient
`to re?ow the oxide to thereby collapse voids therein
`and provide a relatively smooth upper surface; etching
`back the oxide to remove the oxide outside the trench
`areas; heating the resulting structure to outgas the impu
`rity dopant from the surface-adjacent region of the
`oxide; removing the etch-stop layer as required from
`selected regions outside the trench; and removing the
`nitride blocking layer from selected regions outside the
`trench; whereby the nitride blocking layer prevents
`oxidation and doping of the underlying structure during
`
`IPR2014-00898
`Exhibit MX027II-1011, p. 8
`
`

`
`4,571,819
`9
`the re?ow and outgassing steps and the polysilicon
`layer prevents etching the underlying structure during
`the oxide removal.
`5. The process of claim 4 wherein prior to the forma
`tion of the silicon nitride layer, a silicon dioxide stress
`relief layer is formed on the trench walls.
`6. A process for forming a trench oxide isolation
`structure in a substrate, comprising: forming an etch
`mask on the substrate to de?ne the trench surface con
`?guration; etching the substrate in the presence of the
`mask; forming a stress relief layer on th