"S.
`
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`
`EXHIBIT
`
`MACRONIX
`MX027ll-1 08
`
`isejccsqa‘ Edit
`
`ion
`
`.ebw.T
`
`\ I
`
`IPR2014-00898
`Exhibit MX027II-1008, p. 1
`
`

`

`SILIOON PHOOESSENO
`
`FOR
`
`THE ' ELSE EM
`
`VOLUME 1:
`
`PROCESS TEOHNOLOGY
`
`Second Edition
`
`STANLEY WOLF FILE
`
`BlOHARON. TAOBER PILO.
`
`. LATTICE PRESS
`
`Sunset Beach, California
`
`|PR2014-O0898
`Exhibit MX027II-1008, p. 2
`
`IPR2014-00898
`Exhibit MX027II-1008, p. 2
`
`

`

`DISCLAIMER
`
`This publication is based on sources and information believed to be reliable, but the
`authors and Lattice Press disclaim any warranty or liability based on or relating to the
`contents of this publication.
`
`Published by:
`
`LATTICE PRESS
`Post Office Box 340
`
`Sunset Beach, California 90742, USA.
`
`Cover design by Roy Montibon, New Archetype Publishing, Los Angeles, 'CA.
`
`Copyright © 2000 by Lattice Press.
`All rights reserved. No part of this book may be reproduced or transmitted in any form
`or by any means, electronic or mechanical, including photocopying, recording or by any
`information storage and retrieval system without written permission from the publisher,
`except for the inclusion of brief quotations in a review.
`
`Library of Congress Cataloging in Publication Data
`Wolf, Stanley and Tauber, Richard N.
`
`Silicon Processing for the VLSI Era
`Volume 1: Process Technology
`
`Includes Index
`
`1. Integrated circuits—Very large scale
`integration. 2. Silicon. I. Title
`
`ISBN 0-9616721-6-l
`
`9 8 7 6 5 4 3 2 l
`
`PRINTED IN THE UNITED STATES OF AMERICA
`
`|PR2014-00898
`Exhibit MX027II-1008, p. 3
`
`IPR2014-00898
`Exhibit MX027II-1008, p. 3
`
`

`

`MULTI—LEVEL INTERCONNECTS FOR ULSI 727
`
`Table 15.4 DESIRED PROPERTIES OF tNTERLEVEL DIELECTRIcs FOR VLSI 7
`
`1. Low dielectric constant for frequencies up to ~20 MHZ, in order to keep capacitance between metal
`
`lines low;
`
`2. High breakdown field strength (> 5 MV/cm);
`
`3. Low leakage, even under electric fields close to the breakdown field strength. Bulk resistivity
`should exceed 1015 Q—cm.;
`4. Low surface conductance, surface resistivity should be >1015 Q-cm;
`
`5. No moisture absorption or permeability to moisture should occur;
`6. Films should exhibit low stress, and the preferred stress is compressive (~5xlO8 dynes/cmz),
`since dielectric films under tensile stress exhibit more of a tendency to crack;
`
`7. Good adhesion to aluminum, and of aluminum to the dielectric. (Good adhesion is also needed to the
`
`other conductors used in ULSI, such as doped polysilicon and silicides.) In cases of poor adhesion
`
`(such as with Cu or W), a glue layer (such as Ti or TiN) may need to be applied between the conduc—
`tor and the dielectric;
`
`8. Good adhesion to dielectric layers above or below. Such dielectric layers could be thermal oxides,
`
`doped-CVD oxides, nitrides, oxynitrides, polyimides, or spin—on glasses;
`9. Stable up to temperatures of 500°C;
`
`10. Easily etched (by wet or dry processing).
`11. Permeable to hydrogen. This is important for IC processing, in which an anneal in a hydrogen
`
`containing ambient must be used to reduce the concentration of interface states between Si and the,
`
`gate oxides of MOS devices (see Chap. 8);
`12. No incorporated electrical charge or dipoles, some polyimides in particular contain polar
`molecules that can orient themselves in an electric field and give rise to an electric field even
`
`when the externally applied field is removed;
`
`13. Contains no metallic impurities;
`
`14. Step coverage that does not produce reentrant angles;
`
`15. Good thickness uniformity across the wafer, and from wafer to wafer.
`16. In the case of doped oxides, good dopant uniformity across the wafer, and from wafer to wafer;
`
`17. Low defect density (pinholes and particles);
`
`18. Contains no residual constituents that outgasduring later processing to the degree that they
`
`degrade the properties of other layers of the interconnect system (e.g., outgassing from some
`polyimide films, SOG films, or low—temperature TEOS films)
`
`Pre-metal dielectric (PMD) films can be flowed and reflowed at temperatures in excess of
`800°C. However, when Al is present on the wafer surface, the maximum temperature of the
`intermetal dielectric layers is limited to ~450°C.
`
`15.3 PLANABIZATION 0F INTEBLEVEI. DIELECTRIC LAYERS
`
`1
`
`As pointed out in the chapter introduction, the planarization of interlevel dielectrics is one of
`three critical issues that must be addressed when implementing a multilevel interconnect system
`for VLSI applications. This assertion is now justified and the various approaches developed for
`dealing with this issue are described.
`
`|PR2014-00898
`Exhibit MX027II-1008, p. 4
`
`IPR2014-00898
`Exhibit MX027II-1008, p. 4
`
`

`

`728 SILICON PROCESSING FOR THE VLSI ERA
`
`15.3.1. Terminology nl Planarizalion in Multilevel Interconnects
`
`As additional levels are added to multilevel~interconnection schemes and circuit features are
`scaled to submicron dimensions,
`the required degree of planarization is increased. Such
`planarization can be implemented in either the conductor or the dielectric layers.
`In this section
`processes developed to planarize dielectric layers are described. In later sections, techniques for
`planarizing conductor layers and vias will be considered.
`The term planarization is employed quite frequently (and loosely) both here and in other
`technical literature. Therefore it is useful to define this term more completely, especially as it
`applies to planarization of dielectric layers in multilevel—interconnect technology. The example
`case used for this discussion is that of a dielectric layer (IMD) deposited after Metal
`1
`is
`patterned. In the case where no planarization exists (Fig. 15—4a), the step heights on the DMl
`surface closely approximate the step heights of the Metal 1 layer and the underlying topography,
`Furthermore, in this case the steps on the IMD surface also have steep slopes (i.e., vertical, or
`even reentrant).
`
`15.3.1.1 Degree 01 Planarizalinn: The steps on the surface of DM1 can be made less severe
`through various planarization processes. The degree to which this can be successfully
`accomplished differs according to the technique used. The degree of planarization is classified
`according to the following qualitative planarization criteria:
`
`1. The first degree of planarization (smoothing) involves a lessening of the step slopes at
`the IMD surface (Fig. 15-4b). The step heights in this case, however, are not significantly
`reduced in magnitude.
`2. In the second degree of planarization (partial or semi—planarization) the step heights are
`reduced (but not eliminated), and the slopes of the steps are also smoothed (Fig. 15-4c).
`3. In the third degree of planarization (complete local planarization), the steps at the sur-
`face of IMD are completely eliminated wherever the spaces in the underlying topography
`are relatively close together (e.g., <10 ,um apart), but the steps at isolated, wide features
`still exhibit a step (Fig. 15—4d).
`.
`4. In the fourth degree of planarization (complete global planarization), the surface of the
`IMD is completely planarized over arbitrary topography (Fig. 15—4e).
`A quantitative measure of the step—height reduction, referred to as the planarization factor, B, is
`given by8
`_
`— (tfstep/tlstep)
`
`[3 = 1
`
`(15.4)
`
`where tistep and tfsmp are the initial and final step heights, respectively. In complete~
`planarization cases, 8 = 1. If no planarization (or only smoothing) exists, then [3 = 0.
`15.3.1.2 The Need ler Dielectric Planarizalion: As the number of levels in an interconnect
`technology is increased, the stacking of additional layers on top of one another produces a more
`and more rugged topography. Consider, for example, a two—level metal, single—poly CMOS
`process. Assume the step height of the semi-recessed field oxide is 0.3 pm, and the thicknesses
`of the poly and the first and second metals are 0.4, 0.5 and 1.0 pm, respectively. The maximum
`height of the steps on the wafer surface after each of these processes will be 0.3, 0.7, 1.2, and
`
`|PR2014-00898
`Exhibit MX027II-1008, p. 5
`
`IPR2014-00898
`Exhibit MX027II-1008, p. 5
`
`

`

`N o P Ia nati zation
`
`MULTI—LEVEL INTERCONNECTS FOR ULSI 729
`
`
`
`
`(a)
`
`ml")
`
`
`
`Smoothing Ion y
`titep 3
`ti... = tile.
`
`Smoothing and
`
`amal
`
`planarizatlon g
`Itstep
`.
`'
`f
`tstep <tlstep
`
`.....
`
`Complete Local
`Planarlzation
`
`
`
`
`Complete Global
`Planarization
`f
`_
`Imp — O
`everywhere
`
`
`
`Fig. 15-14 Degrees of dielectric planarization.
`
`2.2 pm, respectively (Fig. 15—5). It is apparent that the surface of the wafer must be planarized
`in some fashion to prevent the topography roughness from growing with each level. Without
`such planarization,
`the microscopic canyons that result on the wafer surface from stacking of
`device features can lead to topography conditions that would eventually reduce the yield of
`circuits to unacceptably small values.
`A nonplanar wafer topography results in three conditions that prevent the fabrication of re-
`liable electrical connections in multilevel interconnect systems. These conditions are as follows:
`
`1. Poor step-coverage of the metal lines as they cross over the high and steep steps. A
`measure of how well a film maintains its nominal thickness is expressed by the ratio of
`minimum thickness of a film as it crosses a step, ts, to the nominal thickness of the film
`on horizontal regions, tn (Fig. 15—6a). This property is referred to as the step coverage of
`the film, and is expressed as the percentage of the nominal thickness that occurs at the
`step:
`
`Step coverage (%) = (ts/tn) x 100%
`
`[15.5)
`
`Step coverage of 100% is ideal for a conductor, but in general the height of the step and
`the aspect ratio of the features being covered impact the expected step coverage. (The
`aspect ratio is defined as the height-to-spacing ratio of two adjacent steps.) The greater
`the step height or the aspect ratio, the more difficult it is to attain coverage of the step
`without a corresponding thinning of the film that overlies it. Figure 15-6b shows an
`
`|PR2014-00898
`Exhibit MX027II-1008, p. 6
`
`IPR2014-00898
`Exhibit MX027II-1008, p. 6
`
`

`

`730 SILICON PROCESSING FOR THE VLSI ERA
`
`
`
`-human-<22
`
`Field Oxide
`
`“step = 0.3 um
`
`H9. 15-5 As the number of levels in an interconnect technology is increased, the stacking of additional
`layers on top of one another produces steps of progressively greater heights.
`example of poor step coverage. Hence, worse step coverage is expected under these
`conditions. In addition to the step height and aspect ratio, step coverage depends on two
`other topological factors: the contour and the slope of the step. In general, the smoother
`the steps contour and the less vertical its slope, the better will be the step coverage of any
`overlying films.
`
`2. Metal stringers remain behind at the foot or sides of steep steps when anisotropic etch—
`ing is used. This condition is shown in Fig. 15—6c. In addition, the resist is typically
`eroded by the same gases that etch the metal. The resist must therefore be thick enough in
`all locations that it will not be completely removed before the etch process is completed.
`If the dielectric surface has steps, in certain locations (i.e., over the upper corners of the
`steps in the dielectric, see Fig. 15—6d), there may not be sufficient resist thickness to
`survive during the time of overetch that must be used for removal of the stringers. The
`resist—erosion rate during the overetch time is also generally enhanced, Because most of
`the exposed metal has been etched away, the reactant gases that were being consumed
`during etching of the metal are now present in greater concentrations. In cases where the
`resist is completely eroded at thin spots, the metal beneath the resist will be exposed to
`the reactive species and may be etched away to an unacceptable degree.
`Even. if the above two limitations could be overcome, the following obstacle would
`eventually force planarization to be implemented:
`3. The depth—of-field limitations of submicron optical-lithography tools will require
`surfaces to be planar within :0.5 pm. As a result, if steps larger than 0.5 pm exist on the
`surface of MD (or any other layer on the wafer), it will not be possible to pattern features
`in Metal—1 to the maximum resolution of the stepper. Thus, planarization will be
`mandatory if optical lithography is to be usable for fabricating ICs with such submicron
`feature sizes. (This topic is discussed in more detail in Chap. 13.)
`
`|PR2014-00898
`Exhibit MX027II-1008, p. 7
`
`IPR2014-00898
`Exhibit MX027II-1008, p. 7
`
`

`

`MULTI-LEVEL INTERCONNECTS FOR ULSI 731
`
`Planarization of the intermetal dielectric layers is one of the chief approaches that have been
`taken to alleviate the problem of rough surface topography.
`
`15.3.1.3 The Price That Must Be Paid as the Degree of Dielectric Planarizalion ls Increased: In
`the sections that follow, a progression of planarization techniques will be described, beginning
`with the smoothing of dielectric films, and going through complete global planarization. At least
`two significant penalties are encountered as the degree of planarization is increased, since ‘the
`maximum variation in the thickness of the dielectric layer at different locations on the circuit
`will also increase. This is illustrated in Figs.'15-7a and b,
`in which the variations in the
`thickness of the dielectric in a non—planarized topography are compared to the variations that
`
`occur in a fully planarized interconnect structure.
`
`
`
`l s
`
`(a)
`
`Step Coverage (%) = (is l in) x (100%)
`
`
`'EESIDUE '
`
`
`
`1/
`../ _/'
`
`
`/suesrRAr£-/
`.
`/"/' /.// -’ ."
`
`
`DIELECTRIC
`
`d )
`
`l3 > '1 > 32 > y
`
`Fig. 15-6 (a) Definition of step coverage. (b) SEM micrograph showing poor step coverage. (0) Metal
`stringers remain behind at
`the foot or
`sides of a steep step when anisotropic etching is used. (d)
`Problem of resist thinning as film crosses underlying steps.
`
`|PR2014-00898
`Exhibit MX027II-1008, p. 8
`
`
`
`b)
`
`enoronesrsr
`
`
`
`
`IPR2014-00898
`Exhibit MX027II-1008, p. 8
`
`

`

`732 SILICON PROCESSING FOR THE VLSI ERA
`
`5" 1;?
`&m
`
`b)
`
`
`III I
`
`.2?
`
`
`
`
`
`E _ _
`.__
`
`
`
`
`
`
`
`
`
`‘».‘-
`
`
`
`
`
`ACTIVE AREA
`
`
`
`Fig. 15-7 (a) When no planarization is used, the via and contact holes between adjacent conductor levels all
`have approximately the same depth. (b) If planarization of the intermetal dielectric layer, IMD, is achieved,
`the via depths can vary very widely in depth.
`
`The first penalty associated with this effect is the dielectric layer may end up being too thin
`over some of the underlying conductors after the dielectric has been planarized (Fig. 15-7b). If
`this occurs, it may be necessary to deposit an additional dielectric layer to increase the thickness
`'of IMD before depositing Metal—2.
`The second, and more serious, penalty involves the process of creating openings in the
`dielectric layers to allow selective contacting between conductors on different interconnect
`levels. As the degree of planarization is increased, such openings (referred to as vias when they '
`are established in intermetal dielectric layers) will have different depths. For example, consider
`the two—level-metal structure shown in Fig. 15—9. In this structure, the LOCOS field—oxide step
`is 200 nm, the polysilicon thickness is 400 nm, and the PMD layer thickness is 400 nm. It can
`be seen that if a completely planarized IMD layer is used, via depths will vary from 0.3 to 1.3
`,urn. Such a large variation can lead to insurmountable via-filling problems.
`If the technology for adequately covering vias with metal requires that the via sidewalls the
`sloped, an etch process for forming such sloped sidewalls will have to be used.* However, if the
`vias have significantly different depths, it may not be possible to implement a sloped—sidewall
`etch process. If a sloped-sidewall etch is used in the case shown in Fig. 15-8, the dimensions of
`the shallow vias will continue to increase during the time needed to completely etch the deep
`vias. If the lateral dimensions of the shallow vias exceed the width of the Metal~l pattern below
`these vias, the etch process will begin to erode the PMD layer (Fig. 15-8b), even if a nested Via
`is used (nested vias are discussed in Sect. 15.5).
`In such cases, it may be necessary to avoid the use of a complete planarization process and to
`resort instead to a smoothing or semi-planarization procedure. With these methods it is possible
`to select a small enough maximum variation in via depths that a sloped-sidewall etch process
`can be successfully implemented.9 In general, however, the smoothing and semi—planarization
`techniques lose their effectiveness when three or more levels of metal are required and when
`* Via sidewall sloping is usually needed when metal films are deposited by sputtering. In such cases, ifthe
`via sidewalls are too steep, metal step‘coverage becomes inadequate, and metal thinning (or even metal—
`film discontinuity) occurs. Therefore, it becomes necessary to slope'the sidewalls as much as possible.
`
`|PR2014-00898
`Exhibit MX027II-1008, p. 9
`
`IPR2014-00898
`Exhibit MX027II-1008, p. 9
`
`

`

`MULTI—LEVEL INTERCONNECTS FOR ULSI 733
`
`a)
`
`Fig. 153 (a) If a sloped-sidewall etch is used to etch vias, the dimensions of the shallow vias will continue
`to increase during the time needed to completely etch the deep vias. (b) If the lateral dimensions of the
`shallow vias exceed the width of the Metal—1 pattern below these vias, the etch process will begin to erode
`the PMD layer even if a nested via is used.
`device dimensions are smaller than 1 pm. Here, the use of complete planarization processes
`becomes mandatory, and technologies must be employed that allow vertically sided contact
`holes and vias of varying depths to be completely filled. The techniques developed for such
`complete via filling wrllbe discussed in subsequent sections.
`15.3.1.1; Design Rules Related to Inlermetal Dielectric-Formation and Planarization Processes:
`The type of intermetal dielectric material, its thickness, and the method of its deposition and
`planarization can all have an impact on the design rules that must be applied when laying out an
`integrated circuit with a particular multilevel—metal system. Here a two~level—metal system with
`an underlying polysilicon level. Assume that the topography beneath the polysilicon is
`completely planar. In this system, design rules dealing with the following conditions must be
`specified: (1) minimum polysilicon-to-Metal-l spacing, assuming no metal overlap of the poly,
`(2) minimum distance between coincident edges when Metal-1 overlaps polysilicon, and (3)
`minimum spacing of Metal-l to Metal—1.
`If polysilicon and Metal—l come too close together, a gap will exist between them that will
`lead either to void formation in the CVD oxide PMD layer following deposition (Fig. 15—9a) or
`to the formation of a deep narrow crevice that cannot be covered by the next level of metal, even
`after some planarization procedures have been implemented (Fig. 15—9b).
`'In the second case, if polysilicon and metal edges are coincident, the total step height may be
`too high for adequate coverage by Metal-2 to be achieved (Fig. 15—90). Figure 15—9d illustrates
`the case in which the problems of coincident edges and a narrow crevice are exacerbated by
`In the third case, the spacing between adjacent Metal—1 lines must be large enough to prevent
`void or crevice formation in the deposited dielectric film. The step that exists in the LOCOS
`field oxide must also be considered in real situations when such design rules are being
`
`their simultaneous occurrence.
`
`|PR2014-00898
`.
`Exhlbit MX027II-1008, p. 10
`
`IPR2014-00898
`Exhibit MX027II-1008, p. 10
`
`

`

`734 SILICON PROCESSING FOR THE VLSI ERA
`
`formulated. One possible way to prevent the formation of voids, crevices, and excessively high
`steps, is to allow the spacings between Metal-1 and underlying features to be sufficiently large
`that any possible combination of misalignment cannot lead to the problems listed. However, this
`alternative is impractical, because it increases chip size and causes excessive complexity in
`layout design.
`The trend in advanced IC designs today is toward the elimination of all such restrictive diel—
`ectric—layer-related design rules. The development focus is on dielectric planarization processes
`
`
`
`Fig. 15-9 Conditions associated with the relative spacing of polysilicon and Metal—l that lead to layout
`design rules of these layers
`
`|PR2014-00898
`Exhibit MX027II-1008, p. 11
`
`IPR2014-00898
`Exhibit MX027II-1008, p. 11
`
`

`

`MULTI—LEVEL INTERCONNECTS FOR ULSI 735
`
`-
`
`that allow all spaces between any adjacent or overlapping features (and all possible step
`heights), to be covered with a dielectric layer whose surface does not exhibit any voids,
`crevices, or excessively high steps. Even though this is an actively pursued goal, it has not yet
`been attained in all processes and technologies. Various planarization approaches that have been
`developed along the path toward the condition in which no restrictive design rules need be
`invoked will be described.
`
`15.3.2 Step-Height Reduction oi Underlying Topography as a Technique to
`Alleviate the Need for Planarizalion
`In two—level—metal processes,
`it may be possible to avoid performing any planarization
`procedures with respect to the IMD if the topography underlying IMD is planarized by the
`process steps that precede IMD deposition. Although this approach may appear to be obsolete
`for ULSI and ULSI circuits, several of the step—height reduction techniques turn out to be useful
`for providing a planar surface under Metal 1. Such a condition will ultimately be required for
`three and four—level-metal processes. The survey of planarization techniques of dielectric layers
`begins by considering this approach. In this section two older step—height reduction techniques,
`are described, namely: 1) CVD SiO2 and bias—sputter etchback; and 2) planarization through
`sacrificial-layer etchback.
`15.3.2.1 Provide a Semi-Planar Surlaee over Local-Interconnect Levels: Polysilicon or
`polycide interconnect structures are often used as a local-interconnect layer. The oxide spacers
`formed at the edges of the polysilicon during the fabrication of lightly doped drain (LDD)
`structures and salicides (see Chap. 16 for a discussion of both of these structures) result in some
`smoothing of the steps in the dielectric layer between the poly and Metal 1.
`Since this local—interconnect level is made of materials that can normally tolerate relatively
`high temperatures (e.g., > 800°C), the CVD glass that covers it can be flowed to smooth the
`steps at its surface. As shown in Fig. 15-10, a 30-minute 900°C anneal in N2 of a BPSG film
`(4.8 wt% B and 4.6 wt% P) over patterned polysilicon can result in an almost completely planar
`15.3.2.2 CVD Slflz and Bias-Snulter Elohbaok: An early method for forming partially planarized
`dielectrics is the CVD/bias-sputter etchback technique (CVD/Etch), is presented here because it
`was a predecessor of the high—density plasma (HDP) CVD dielectric deposition process more
`
`
`
`
`
`Flu. 15-10 Planarization of the PMD layer (BPSG) by thermal flow.10 Reprinted with permission of
`
`Semiconductor International.
`
`|PR2014-00898
`.
`Exhlbit MX027II-1008, p. 12
`
`IPR2014-00898
`Exhibit MX027II-1008, p. 12
`
`

`

`736 SILICON PROCESSING FOR THE VLSI ERA
`
`recently developed for filling high-aspect—ratio features (discussed in Sect. 15—11). In the
`CVD/Etch process, an SiO2 layer is formed by the use of plasma—enhanced CVD (PECVD
`[Figs 15—1 1a and b]).
`'
`
`
`
`erosion rate was much faster, which significantly increased the throughput. Subsequent work
`integrated the process into a single reactor, first with a parallel-plate reactor,l3’14 and later with
`a multi—chamber tool that could perform deposition and etching without exposing the wafers to
`atmosphere between process steps.”-16
`One disadvantage of the CVD/Etch method is that at low temperatures the CVD film does
`not fill high aspect ratio openings (e.g., a 0.5-pm space between 0.7-,um-thick metal lines) with
`just a single sputter-etch step. Instead, for high-aspect-ratio applications, the deposition and
`etchback procedure must be performed in several sequential deposition/etch sequences to
`prevent the formation of voids in such spaces.16 First, an oxide layer is deposited that is not
`thick enough to cause seam closure in the opening. Sputter etching 13 then used to form sloped
`surfaces in the small openings. This keeps the small trenches open during deposition, allowing
`them to eventually be completely filled without the formation of keyholes (voids). This
`approach also tends to stop the propagation of pinholes.
`At the end of this multistep process, the surface topography will have pyramid structures
`over narrow lines, as shown in Fig, 15-12. To eradicate these pyramids, an erosive4mode step
`such as a resist—etchback technique can be used.17 A report has been made of a two—level—metal
`
`
`
`(a) Photograph of an as-deposited PECVD oxide over vertical
`Fly. 15-" CVD SiOZ and in situ etchback.
`sidewalled Metal-l
`lines. (b) Shape of PECVD oxide after reactive ion etching using energetic ion
`bombardment.“ (o 1987 IEEE).
`
`|PR2014-00898
`Exhibit MX027II-1008, p. 13
`
`IPR2014-00898
`Exhibit MX027II-1008, p. 13
`
`

`

`
`
`MULTI—LEVEL INTERCONNECTS FOR ULSI 737
`
`
`
`Fig. 15-12 At the conclusion of a CVD/Etch process, the surface topography over narrow lines will have a
`pyramid structure.16 (© 1987 IEEE).
`
`wiring technology with metal pitches of 1.9 pm for Metal—l and 2.4 pm for Metal—2 that uses
`this method to form the interlevel dielectric.18
`
`There are three main drawbacks to this multiple CVD/Etch process: 1) the throughput is very
`low, even when batch CVD and etch reactors are used; 2) an erosion step must be used to
`planarize the pyramid structures over narrow lines (further reducing throughput); and 3) global
`planarization is not achieved (i.e., complete planarization is not achieved over wide steps).
`
`15.3.3 Planarization through SacriticiaI-Laver Etchback
`
`Planarization of CVD interlevel—dielectric films can also be achieved using the sacrificial-layer
`etchback technique (Fig. 15-13). This method gained the most widespread acceptance in two—
`level—metal processes down to ~1 pm device technologies (and even in some reported three—
`level—metal bipolar processes). Using this approach, it is possible to achieve a high degree of
`planarization between steps that are ~2-lO ,um apart. With more closely spaced features, the
`technique runs into problems. For more widely spaced steps, planarization is less complete. The
`process is carried out by first depositing the CVD film that will serve as the PMD or IMD. This
`layer is then coated with a film that will later be etched off (sacrificed). In most cases, such
`sacrificial
`layers are photoresists, spun on in liquid form. Upon being baked, these liquids
`become solid thin films that are thick enough so they provide a film surface that is close to
`being flat, as shown in Fig. 15-14. As long as the feature size is smaller than 10 pm, the degree
`of planarization can exceed 70% with most photoresists.
`In the next step, the sacrificial layer is first rapidly etched back in a plasma (typically, 02 or
`02 mixed with CF4) until the topmost regions of the dielectric layer are just exposed (Fig. 15-
`13b). The etch chemistry is then modified so the sacrificial-layer material and the dielectric are
`etched at approximately the same rate. The etch is continued under these conditions until all of
`the sacrificial layer has been etched away. At this point, the surface of the dielectric film is
`highly planarized since the profile of the sacrificial layer is transferred to the dielectric layer by
`the etchback procedure. The thickness of the dielectric film over underlying features, such as
`metal lines, may be thinner than desired after the etchback is completed. In some processes, in
`fact,
`the etchback step is allowed to proceed until the Metal—1 lines are exposed. In any case, an
`
`
`
`|PR2014-00898
`Exhibit MX027II-1008, p. 14
`
`IPR2014-00898
`Exhibit MX027II-1008, p. 14
`
`

`

`738 SILICON PROCESSING FOR THE VLSI ERA
`
`
`
`«.4 INSULATOR
`
`SUBSTRATE
`LOWER METAL
`
`
`INTERCONNECT
`
`PLASMA ETCH
`PLANARIZING
`LAYER
`
`PLASMA ETCH TO INSULATOR
`
`
`/ INSULATOR
`LOWER METAL
`SUBSTRATE
`
`
`INTERCONNECT
`
`PLASMA ETCH INTO INSULATOR
`
`LOWER METAL
`INTERCONNECT
`
`4,,— INSULATOR
`
`SUBSTRATE
`
`Fig. 15-13 Sequence of steps used in a sacrificial-layer etchback process for planarization.
`additional layer of CVD dielectric is generally deposited in order to establish a minimum
`adequate thickness everywhere on the wafer surface.
`15.3.3.1 Sacrificial-Elchhack Process Problems: To achieve the desired degree of planaiity and
`final dielectric film thickness, very tight process control is necessary for such parameters as the
`magnitude of the etch rate, the etch—rate uniformity across a wafer, end—point detection, and
`oxide—thickness uniformity under the resist layer. The resist etch-rate is sensitive to the cure
`cycle (especially if a high-temperature bake step [>150°C] is used to improve surface planarity),
`and to chamber preconditioning. In batch processes, the etch rate is also sensitive to the number
`100
`
`oEGae E
`
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`
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`
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`
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`
`5mm SPEED 4000RPM
`0300
`FE . 200T
`W235
`re . 200%
`H204
`FE . 200%
`A p(
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`Fig. 15-114 Degree of planarization vs. various feature sizes for different polymers. 142 (© 1987 IEEE).
`
`5
`
`10
`
`'
`
`30
`
`2255
`
`|PR2014-00898
`Exhibit MX027II-1008, p. 15
`
`IPR2014-00898
`Exhibit MX027II-1008, p. 15
`
`

`

`MULTl-LEVEL INTERCONNECTS FOR ULSI 739
`
`
`Void Formation
`
`
`
`
`Dielectric
`
`
`
`Fin. 15-15 (a) Diagram of void formation due to cusping of the dielectric. (b) SEM of voids left between
`1.5—pm-spaced Metal-1 lines in a 3.0—pm—thick PMD PECVD oxide.
`
`of wafers present in the chamber. Such tight process control of a complex process is hard to
`maintain in production line.
`The process also requires a multitude of steps, which implies a lengthy process, and thus a
`low throughput. Etchback is a difficult process to successfully implement in a batch-etch mode,
`resulting in an even lower throughput. Finally, if the aspect ratio between adjacent Metal—1 lines
`with vertical sidewalls exceeds 0.4, voids will form when most CVD—SiO2 layers are deposited
`(Fig. 15—15). These voids can trap resist and moisture, which can subsequently be released if the
`voids are Opened during the etchback process. Opened voids will also trap metal during the
`Metal—2 deposition step. It will remain in the form of metal stringers following Metal-2 pattern—
`ing. Thus, this process is not feasible for Metal—1 spacings of less than ~1.25 pm (unless a pro-
`cess is available for deposition of Si02 layers at low temperatures without formation of voids in
`high—aspect ratio spaces [e.g., PECVD TEOS films, O3:TEOS films, or HDP CVD films]).
`
`15.4 DOUBLE-LEVEL—METAI. (DLM) INTERGONNEGTS FOR 1-Ilm CMOS
`Double-level—metal (DLM) interconnect systems were used in CMOS technologies ranging from
`2.0 ,um down to about 0.8 pm. In this section an example of the kinds of materials and sequence
`of process technologies employed to fabricate such DLM systems is described. In later sections
`(after some additional interconnect processes are covered), examples of a triple-level metal
`(TLM) system (used in the 0.65—0.35 pm CMOS generations), and a 5-level (or more) inter-
`connect technology (used for 0.25—0.18 pm CMOS generations) are presented. These examples
`are merely academic constructs of a multi-level interconnect system. That is, actual systems
`used in ICs are likely to differ in various details from the examples given here. But the process
`flows and materials used for descriptive purposes are reasonably representative of the way such
`interconnects are actually implemented (see Figs. 1617 to 16-19).
`
`|PR2014-00898
`Exhibit MX027II-1008, p. 16
`
`IPR2014-00898
`Exhibit MX027II-1008, p. 16
`
`

`

`740 SILICON PROCESSING FOR THE VLSI ERA
`
`The fabrication of DLM interconnect structures begins after the contacts in a PMD BPSG
`layer are opened and a reflow step has been carried out. At that point Metal—l
`is deposited. In
`this DLM technology an alloy of Al, such as Al-Si
`(e.g., lwt% Si) or Al-Cu (e.-g., l—2wt% Cu)
`is the material of choice, deposited to a thickness of about 500 nm by sputtering. The Al-Si
`alloys were used in earlier NMOS and CMOS technologies (i.e., 2—pm CMOS), with the silicon
`being added to the aluminum to prevent spiking of the contacts during subsequent annealing
`steps (see Chap. ll). In 1.2-,um (and smaller) CMOS, such Al:S_i alloys were replaced with a
`metallization system that included a diffusion barrier (typically Ti/TiN) and an Al:Cu alloy film
`for the main interconnect layer. The Cu was added to the Al increase the electromigration
`resistance of the films. Dry etc