United States Patent [191
`Sonohara et al.
`
`ll
`
`US005646960A
`[11] Patent Number:
`[45] Date of Patent:
`
`5,646,960
`Jul. 8, 1997
`
`[54] INVERSE MODIFIED DISCRETE COSINE
`TRANSFORM SIGNAL TRANSFORMING
`SYSTEM
`
`[75] Inventors: Mito Sonohara; Kyoya Tsutsui. both
`of Kanagawa, Japan
`
`[73] Assignee: Sony Corporation, Tokyo, Japan
`
`[21]
`[22]
`
`Appl. No.:
`731,645
`Oct. 17, 1996
`
`Filed:
`
`Related US. Application Data
`
`[60] Continuation of Ser. No. 458,338, Jun. 2, 1995, abandoned,
`which is a division of Ser. No. 119,003, Sep. 9, 1993,
`abandoned.
`Foreign Application Priority Data
`
`[30]
`
`Sep. 28, 1992
`
`[JP]
`
`Japan .................................. .. 4-282440
`
`[51] Int. 01.6 ................................................... .. H04B 14/00
`[52] US. Cl. ............ ..
`375/340; 364/725.01
`[58] Field of Search ................................... .. 375/240, 241,
`375/243, 245; 381/29; 348/400, 403, 408;
`364/725-726
`
`[56]
`
`References Cited
`TE] H :U] [E H,
`U'S' P
`DO
`S
`6/1993 Iwadare ................................. .. 364/725
`5,218,561
`5/1994 Mahieux
`5,311,549
`9/1994 TSlltSlli .................................. .. 364/725
`5,349,549
`FOREIGN PMENT DOCUMENTS
`
`GO6F 15/332
`0 402 145 A3 12/1990 European Pat. Off.
`GO6F 15/332
`0 463 473 A2 U19” European P21. O?.
`0 535 893 A2 4/1993 European Pat. Off. .... .. G06F 15/332
`444099 2/1992 Japan ............................. .. GlOL 9/18
`
`OTHER PUBLICATIONS
`E.O. Bringharm “Fast Fourier Transform,” transl. by Miya
`gawa and Imai, pp. 196-198.
`F. Hazu et a1., “Adaptive Transform Coding with an Adap
`tive Block Size (AFC-ABS) using MDCT,” Extended
`Abstracts in Spring Meeting of Japan Society of Electronic
`Information Communication 1990, A-197.
`M. Iwadare et al.. “On a Modi?ed Discrete Cosine Trans
`form (MDCI‘) and its Fast Algorithm.” C&C Systems
`Research Laboratories, NEC Corporation, CAS90-9,
`DSP90-l3, pp. 49-54.
`T. Mochizulci et al., “Constraint Conditions for Multiple
`Blocksize Modi?ed-DCT.” C&C Systems Research Labo
`ratories, NEC Corporation, CAS90-10, DSP90-14, pp.
`55-60.
`Primary Examiner-Young T. Tse
`Attorney, Agent, or Firm-Limbach & Limbach L.L.P.
`[57]
`ABSTRACT
`
`An MDCT calculating circuit includes an x01 calculating
`circuit for multiplying input signals with a forward trans
`forming window and a linear forward transforming unit for
`linear forward transforming an output signal of the calcu
`lating circuit The linear forward transforming unit includes
`an X02 calculating circuit and an x03 calculating circuit for
`pre-processing the output signal of the x01 calculating circuit
`and an integration and summation processing circuit for
`executing integration and summation processing operations
`on an output signal of the pre-processing unit. The integra
`tion and summation processing circuit executes an integra
`tion and summation operation on an N/2 number of input
`signals from the pl'c_proccssing unit
`grouping a k number
`of input signals as a processing unit and lteratively executes
`the integration and summation processing operations a
`N/(2*K) number of times for outputting a sum total of N/2
`number of signals_
`
`16 Claims, 7 Drawing Sheets
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`US. Patent
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`Jul. 8, 1997
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`Jul. 8, 1997
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`Jul. 8, 1997
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`Jul. 8, 1997
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`5,646,960
`
`1
`INVERSE MODIFIED DISCRETE COSINE
`TRANSFORM SIGNAL TRANSFORMING
`SYSTEM
`
`This is a continuation of application Ser. No. 08/458338
`?led on Jun. 2, 1995, which is a divisional application of
`application Ser. No. 08/119,003 ?led on Sep. 9. 1993 now
`both are abandoned.
`
`2
`number of chronological data 104 which are multiplied by a
`window Wf for executing inverse transform or a synthetic
`?lter to produce chronological data 105. The resulting data
`are summed to output results of the forward and backward
`blocks to restore the original chronological input data.
`Meanwhile, in practical processing operation of MDCI‘
`and lMDCI‘. a method for implementing fast operation using
`fast Fourier transform has been proposed in “A research in
`MDCI‘ System and Fast Operation” by Iwatare. Nishiya and
`Sugiyama, in SHNGAK-GIHO, CAS 90-9. DSP 90-13,
`pages 49 to 54. The same method has also been disclosed in
`JP Patent KOKAI Publication NO. 444099 (1992). The
`calculating method for MDCI‘ and IMDCF disclosed therein
`is hereinafter explained.
`The de?nition of MDCI‘ is given by an equation (1).
`
`(1) 1
`
`In the above equation (1), x0 is an MDCI‘ input signal. N
`a block length, Wh a window function for forward
`transform, y0 an MDCI‘ output signal, C0 a constant, 11 an
`integer of from 0 to N-l. and k an integer of from 0 to
`N/2-1. Since MDCI‘ processing on sliced chronological
`data is executed independently for each of the blocks, the
`block number J is omitted. Meanwhile, since the value of C0
`is not critical in carrying out the calculation of MDCT, the
`following explanation is made on the assumption that Co=1.
`For carrying out the operation, x0 is multiplied by a window
`for forward transform to ?nd x01 as indicated by the equation
`(2).
`
`x0r(")=xo(")h(") OénéN-l
`
`(2)
`
`From x01, as found from equation (2), x02 is calculated in
`accordance with equation (3).
`
`X0201) = [
`x03 is calculated in accordance with equation (4).
`
`OénéNM-l
`
`(3)
`
`Then, x03 is multiplied by a coe?icient as shown by the
`equation (5) to produce a series of complex number signals
`
`This signal series is processed with FPT having a length
`of N/2 to produce a series of complex number signals 202
`shown by the equation (6).
`
`yO1 is calculated from the produced series of complex
`number signals, as indicated by the following equation (7).
`
`The above is coincident with y0 de?ned by the equation
`(1). as demonstrated by the above-cited Research Concem
`ing MDCT System and Fast calculation.
`On the other hand, de?nition of IMDCI' is given by an
`equation (8).
`
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`This invention relates to a modi?ed discrete cosine trans
`form (“MDCI‘”) signal transforming device for executing
`fast calculation of linear transformation on digital signals
`such as speech. audio or picture signals.
`2. Description of the Related Art
`There has hitherto been known a transform encoding
`employing a so-called orthogonal transform as a type of high
`e?iciency encoding of encoded chronological sampling data
`such as audio signals encoded by high-e?iciency bit com
`pression. The transform encoding means encoding after
`block-based orthogonal transform of input signals. Typical
`of the transform encoding is a discrete cosine transform
`(DCI‘). Such transform encoding suffers from a problem of
`block distortion in which non-continuous block-to-block
`transitions are perceived as noises. The conventional prac
`tice for coping with such problem has been to have an end
`of a block overlapped with an adjacent block. According to
`a modi?ed DCI‘ (MDCT), a given block is overlapped with
`both adjacent blocks each by one-half a block size in such
`a manner as to preclude super?uous transmission of samples
`of overlapped portions. Thus the MDCI‘ is highly suitable
`for high ef?ciency encoding.
`Such MDCI‘ and IMDCI‘ (inverse modi?ed discrete
`cosine transform). which is its inverse transformation, are
`disclosed in “Filter Constraints in Hybrid MDCI‘ Containing
`Plural Block Sizes” by Mochizuki, Yano and Nishiya in
`SHLNGAKU-GIHO, CAS 90-10, DSP90-14. pages 55 to 60
`and in “Adaptive Transform Encoding with Adaptive Block
`Lengths Using MDCI‘” by Uzu, Sugiyama, Iwatare and
`Nishiya in Extended Abstracts in Spring Meeting of Japan
`Society of Electronic Information Communication 1990.
`A- 197. The above-mentioned MDCI‘ and IMDCI‘ are
`explained brie?y by referring to FIG. 1.
`Referring to FIG. 1, a given block of chronological
`sampling data, such as Jth block, has an overlap with the
`(J—1)th block and the (J+1)th block each by a half block
`(50% overlap). If the number of samples of the Jth block is
`N, N being a natural number, there is an overlap of N/2
`samples between the Jth bock and the (J—1)th block, while
`there is similarly an overlap of N/2 samples between the Jth
`block and the (J+1)th block. Each of N samples of each of
`these blocks, such as the above-mentioned Jth block, is
`multiplied by a window Wh for forward transform or a
`pre-processing ?lter to produce an N number of chronologi
`cal data 102.
`The characteristics of the pre-processing ?lter or window
`Wh for orthogonal transform are selected depending on
`statistic properties of input signals so that power concentra
`tion of the transformed data will be maximum. By process
`ing these N samples of the chronological data 102 by linear
`forward transformation by MDCT, an N/2 number of inde
`pendent spectral data 103, that is one-half the number of
`input samples of the spectral data. are produced on the
`frequency domain. These N/2 number of the spectral data
`103 are processed by inverse MDCI‘ for producing an N
`
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`method by modi?ed DCT in which the operation of the
`modi?ed DCI‘ and IMDCI‘, its inverse transform, may be
`realized by integration and summation based on a K number
`of terms as a processing unit with the use of a small-sized
`processing unit.
`According to the present invention, there is provided a
`modi?ed DCI‘ signal transforming device for processing an
`N number of sample input signals, comprising a forward
`transforming window unit for multiplying input signals with
`a forward transforming window and a linear forward trans
`forming unit for linear forward transforming output signals
`of said forward transforming window unit, characterized in
`that the linear forward transforming unit comprises a pre
`processing section for pre-processing the output signals of
`the forward transforming window unit and an integration
`and summation processing section for executing integrating
`and summation processing operations on output signals of
`the pre-processing section, the integration and summation
`processing section executing integration and summation
`processing operations on an N/2 number of input signals
`supplied from the pre-processing section, the N/2 number of
`the input signals being previously grouped into sets each
`consisting of a K number of terms, said integration and
`summation operations being iteratively executed an N/(2* K)
`number of times for outputting a sum total of N/2 number of
`signals.
`It is noted that K in the convolution unit is a power of 2
`and is not less than 4.
`The pre-processing unit outputs, with an N number of
`samples of input signals of from 0 to (N-l), obtained on
`multiplying the forward transforming windows in the for
`ward transforming window section, the n+3N/4th input
`signal inverted in sign as the nth intermediate signal for n of
`from 0 to N/4-1, and an n-N/4th input signal as the nth
`intermediate signal for n of ?’om N/4 to N-l. With an N
`number of samples of intennediate signals of from 0 to
`(N-l), the pre-processing unit outputs the 2n-th intermedi
`ate signal less the N—l-2n—th intermediate signal as an nth
`output signal.
`The integration and summation processing unit decreases
`the number of times of the processing operations by
`grouping-an N/2 number of input signals supplied from the
`pre-processing unit into sets each consisting of a K number
`of terms, based on periodicity, for outputting the N/2 number
`of the signals.
`The integration and summation processing unit performs,
`on an N/2 number of input signals supplied from the
`pro-processing unit, a series of processing operations for
`m of from 0 to N/(2K)-1 until the number of output signals
`becomes equal to N12. The series of the processing opera
`tions consists in providing, as a jth ?rst intermediate signal,
`a sum for I of from 0 to N/2-1 of a product of the (I?+j)th
`input signal multiplied by cos((1t(2m+1) (4K+1)/(2N)), for j
`of from 0 to K-l, providing, as a jth ?rst intermediate signal,
`a sum for I of from O to N/2-l of a product of the
`(K(l—l)+j)th input signal multiplied by sin((1t(2m+l)(4Kl+
`1)/(2N)), for j of from K to (2K-1), providing, as a jth
`second intermediate signal, a sum of the jth ?rst intermediate
`signal multiplied by —cos(21't(2m+l)(j/N)) and the (j-K)th
`?rst intermediate signal multiplied by —sin(21t(2m+1)(j/N)),
`for j of from K to K-l, providing, as a jth second intenne
`diate signal, a sum of the (j-K)th ?rst intermediate signal
`multiplied by —sin(21t(2m+1)(j—K)/N) and the jth ?rst inter
`mediate signal multiplied by —cos(21t(2m+1)(i—K)/N), for j
`of from K to 2K-1, providing, as a k-th third intennediate
`signal, a sum of the jth second intermediate signal multiplied
`by cos(2Jk(4j+l)/(4K)), for j of from 0 to K-l, providing, as
`
`In the above equation (8), y1 is an IMDCI‘ input signal,
`N a block length, f a window function for inverse
`transformation, x1 is an IMDCI‘ output signal, C1 is a
`constant, 11 an integer of from 0 to N-l and k an integer of
`from 0 to N/2-1. Since IMDCI‘ processing on sliced chro
`nological data is executed independently for each of the
`blocks, the block number I is omitted. Meanwhile, since the
`value of Co is not critical in carrying out the calculation of
`MDCI‘, the following explanation is made on the assump
`tion that C0=1. For carrying out the calculation, y1 is
`re-arrayed in accordance with the following equation (9) to
`produce yu:
`
`y1(2k)
`
`20
`
`y1L1 is then multiplied by a coe?icient as shown by the
`equation (10) to produce a series of complex number signals
`Z112
`
`(10)
`zu(k)=y“(k) exp (~J21WN) 0§k§N/2—1
`The complex number signal series is processed by inverse
`FFI‘ over a length N/2 to produce a series of complex
`number signals 212 by the equation (11):
`
`25
`
`N/Z
`212(71): 2
`ll
`
`(11)
`
`The complex number signal series Z12 thus formed is
`multiplied by a coe?icient as shown by the equation (12) and
`a real number part is taken out to produce x11:
`
`This x11 is re-arrayed, while changing its sign, as indi
`cated by the equation (13), and is multiplied by inverse
`transforming window.
`
`(13)
`
`45
`
`The above is coincident with y0 de?ned by the equation
`(8), as demonstrated by the above-cited Research Concern
`ing MDCl" System and Fast calculation.
`However, since the fast processing of MDCI‘ for ?nding
`the spectrum for each domain having a length N and IMDCI‘
`which is its inverse operation are carried out with the present
`method using a complex number FFI‘ having a length N/2,
`the N/4 log(N/2) times of multiplication of complex
`numbers, the N/4 log(N/2) times of addition of complex
`numbers and a work area for storing N/2 number of complex
`numbers are required if the algorithm as described above all
`in pp. 196 to 198 of “Fast Fourier Transform”, by E. ORAN
`BRlNGHAM, translated by Miyagawa and Imai, Theory of
`Base 2 FFI‘ Algorithm, is used, meaning that the method
`cannot be said to be su?iciently effective if it is attempted to
`carry out fast processing by a small-scale processing unit.
`OBJECTS AND SUMMARY OF THE
`INVENTION
`In View of the above-depicted status of the art, it is an
`object of the present invention to provide a signal processing
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`the k-th third intermediate signal, a sum of the jth second
`intermediate signal multiplied by sin(21rk(4(j—K)+l)/(4K)),
`for k of from K to (2K-1), and providing, as a (m+kN/
`(2K))th output signal, a sum of the k-th third intermediate
`signal and a (m+kN/(2K))th third intermediate signal, for k
`of from O to K-l.
`The integration and summation processing unit performs
`a processing operation of computing an output signal of the
`integration and summation processing unit from the second
`intermediate signal by a processing volume reduced by one
`half by grouping the second intermediate signals by each
`two terms by taking advantage of periodicity so that the
`number of output signals becomes equal to N/2.
`The integration and summation processing unit performs
`a processing operation of computing an output signal of the
`integration and summation processing unit from the second
`intermediate signal by a processing volume reduced by one
`quarter by grouping the second intermediate signals each by
`four terms by taking advantage of periodicity so that the
`number of output signals becomes equal to N/2.
`A modi?ed DCI‘ signal processing device for processing
`an N/2 number of independent input signals, comprising a
`linear inverse transforming unit for linear inverse transform
`of input signals, and an inverse transforming window unit
`for multiplying an output signal of the linear inverse trans
`form unit by an inverse transforming window, wherein the
`linear inverse transforming unit comprises a pre-processing
`unit for pre-processing an input signal, an integration and
`summation processing unit for executing an integration and
`summation processing operations on an output signal of said
`pre-processing unit, and a post-processing unit for post
`processing an output signal of the integration and summa
`tion processing unit, the integration and summation process
`ing unit executing the integration and summation operations
`35
`on the N/2 number of input signals supplied from the
`pre-processing unit by grouping the input signal by a K
`number of terms, and executing the operations iteratively by
`N/(2*K) number of times for outputting a sum total of an
`N/2 number of signals.
`In the integration and summation processing section, K is
`a power of 2 which is not less than 4.
`The pre-processing unit outputs a signal equivalent to a
`k-th output signal which is the 2k-th input signal for values
`of k of from 0 to N/4-1 and a signal equivalent to a k-th
`output signal which is the (N—1—2k)th input signal inverted
`in sign for values of k of from N/4 to N/2-l.
`The integration and summation processing unit decreases
`the number of times of processing operations for integration
`and summation processing of N/2 number of input signals
`supplied from the pre-processing unit based on periodicity
`for outputting said N/2 number of signals.
`The integration and summation processing unit performs,
`on an N/2 number of input signals supplied from the
`pre-processing unit, a series of processing operations for
`m of from 0 to N/(2K)—1 until the number of output signals
`becomes equal to N/2. The series of the processing opera
`tions consists in providing, as a jth ?rst intermediate signal,
`a sum for 1 of from 0 to N/2-l of a product of the (Kl+j)th
`input signal multiplied by cos((7t(2m+1)(4K+l)/(2N), for j
`of from 0 to K-l, providing, as a jth ?rst intermediate signal,
`a sum for 1 of from 0 to N/2-1 of a product of the
`(K(l—1)+j)th input signal multiplied by sin((7t(2m+1)(4Kl+
`1)/(2N), for j of from K to (2K-1), providing, as a th second
`intermediate signal, a sum of the th ?rst intermediate signal
`multiplied by —cos(21t(2m+l)(j/N) and the (j-K)th ?rst
`intermediate signal multiplied by —sin(21t(2m+1)(i/N), for j
`
`45
`
`6
`of from K to K-l, providing. as a jth second intermediate
`signal, a sum of the Q—K)th ?rst intermediate signal multi
`plied by —sin(21t(2m+1)(j-K)/N) and the th ?rst intermedi
`ate signal multiplied by —cos(21r(2m+1)(i—K)/N), for of
`from K to 2K-l, providing, as a k-th third intermediate
`signal, a sum of the jth second intermediate signal multiplied
`by cos(2nJk(4j+l)/(4K)), for j of from 0 to K-l, providing,
`as the k-th third intermediate signal, a sum of the jth second
`intermediate signal multiplied by sin(21tk(4(j-K}t-l)/(4K)).
`for k of from K to (2K-l), and providing, as a (m+kN/
`(2K))th output signal, a sum of the k-th third intermediate
`signal and a (m+kN/(2K))th third intermediate signal, for k
`of from 0 to K-l.
`The integration and summation processing unit performs
`a processing operation of computing an output signal of the
`integration and summation processing unit from the second
`intermediate signal by a processing volume reduced by one
`half by grouping the second intermediate signals by each
`two terms by taking advantage of periodicity so that the
`number of output signals becomes equal to N/Z.
`The integration and summation processing unit performs
`a processing operation of computing an output signal of the
`integration and summation processing unit from the second
`intermediate signal by a processing volume reduced by one
`quarter by grouping the second intermediate signals by each
`four terms by taking advantage of periodicity so that the
`number of output signals becomes equal to N/2.
`The pre-processing unit outputs a signal equivalent to an
`(n+N/4)th input signal for the value of n of from 0 to N/4-l,
`a signal equivalent to a 3N/4-l-nth input signal reversed in
`sign for values of n of from N/4 to 3N/4-1 and a signal
`equivalent to an n-3N/4th input signal reversed in sign for
`values of n of from 3N/4-l to N/4-1.
`According to the present invention, the integration and
`summation processing unit in the linear forward transform
`ing unit or in the linear inverse transforming unit performs
`an integration and surmnation processing operations on an
`N/2 number of input signals outputted from the pre
`processing unit by grouping the input signals by a K number
`of terms and performing the operations iteratively by an
`N/(2*K) number of times for producing a sum total of N/2
`signals, for simplifying the constitution.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a diagrammatic view showing the operating
`sequence of modi?ed DCI‘ or MDCI‘ operations and an
`inverse MDCT or IMDCT operations.
`FIG. 2 is a block circuit diagram showing an arrangement
`for realizing an MDCI‘ signal transforming method accord
`ing to an illustrated embodiment.
`FIG. 3 is a block circuit diagram showing an arrangement
`for carrying out the IMDCI‘ signal transforming method
`according to an illustrated embodiment.
`FIG. 4 is a ?ow chart showing the process steps of a basic
`embodiment of an MDCI‘ signal transforming method
`according to an illustrated embodiment.
`FIG. 5 is a ?ow chart showing the process steps of a basic
`embodiment of an IMDCI‘ signal transforming method
`according to an illustrated embodiment.
`FIG. 6 is a block circuit diagram showing an example of
`a circuit of a high ef?ciency encoding device for carrying out
`the MDCI‘ signal transforming method according to the
`illustrated embodiment.
`FIG. 7 is a block circuit diagram showing an example of
`a circuit of a high ef?ciency decoding device for carrying out
`
`55
`
`65
`
`11
`
`

`
`7
`the lMDCl‘ signal transforming method according to the
`illustrated embodiment.
`
`5,646,960
`
`8
`
`EMBODIMENTS
`Referring to the drawings, preferred embodiments of the
`signal transforming device by the modi?ed DCT is
`explained in detail.
`Speci?cally, the signal transforming device by MDCT of
`the illustrated embodiment (MDCI‘ processing circuit 30)
`has an arrangement as shown in FIG. 2, while the signal
`transforming device by IMDCI‘ (IMDCI‘ processing circuit
`50) has an arrangement as shown in FIG. 3. Before pro
`ceeding to description of the signal transforming devices by
`MDCT and lMDCI‘ of the embodiments shown in FIGS. 2
`and 3, the basic principle of the signal processing method
`(signal transforming method) applied to these devices is
`explained.
`With the signal processing method applied to the device
`of the present embodiment, a coe?icient table shown by the
`following equations (14) to (16) is provided for an integer
`_rr_1 which is not less than 0 and not more than (N/(2K)—1):
`
`- i
`
`where am," bmJ, cm’l, dmJ, ekJ and fkJ- are coe?icients.
`For integers m which is not less than 0 and no more than
`(N/(2K)—1), the following calculation is made repeatedly.
`First, using the coe?icients of the equation (14), a K
`number of signals A01, as given by the equation (17), and a
`K number of signals A02, as given by the equation (18), are
`calculated from x03 of the equation (4)
`
`Then, from the coe?icient of the equation (15) and from
`these signals A01, A02, two signal trains or rows B01, B02,
`each being of a length K, are calculated as shown by the
`equations (19) and (20).
`
`BMmOFCmJAMNHWAMQO) 0§j§ K—1
`
`BngOZ0)=dmJAngOl0-)_Cm?m,O2O-) Oéjé K—1
`
`( 19)
`
`(20)
`
`45
`
`50
`
`Using the coefficients of the equation (16) and B01, B02,
`a K number of signals X0 are obtained, as shown by the
`equation (21).
`
`55
`
`60
`
`This is coincident with y0 as y0 de?ned by the equation
`(1), as may be seen from the following:
`First, from the relationship of the equations (1), (2), 3) and
`(4), the equation (22) holds:
`
`65
`
`Modifying this, the equation (23) is derived.
`
`(7-3)
`
`12
`
`

`
`9
`-continued
`21t(2m + 111m + 21rk(4j + 1)/(4K))
`
`5 ,646,960
`
`10
`If the periodicity of the equation (16) is utilized, the
`amount of convolution processing of the equation (21) may
`be reduced to one half or to a quarter.
`That is, the coefficient of the equation (16) is modi?ed to
`5 the form shown in Equations (26) and (27).
`
`Using the equations (14), (15), (17) and (18). the equation 15
`(24) is derived.
`
`(24)
`
`25
`
`Therefore. as shown by equation (28). by setting, as
`shown by the equation (28),
`
`X0 is expressed as shown by the equation (29), so that the
`amount of integration and summation processing operations
`is halved.
`
`K/2-1
`
`Besides, since the coe?icient of the equation (16) may
`also be expressed as shown by the equations (30), (31):
`
`eu-wmm =
`
`the equation (32) holds.
`
`50
`
`(30)
`
`(31)
`
`(32)
`
`From the equations (19) and (20), the equation (24) is
`changed to the equation (25).
`
`(25)
`
`This coincides with the equation (21) for the method
`embodying the present invention. It follows from this that
`the MDCI‘ processing may be achieved with the method
`embodying the present invention.
`
`13
`
`

`
`11
`
`5 ,646,960
`
`12
`
`Then, using the coe?icients of equation (16) and B01, B02,
`a K number of signals Wo are obtained, as shown by the
`equation (40):
`
`5
`
`Since one of sine and cosine values in the equation (31)
`is >1, with the other value being 0, by setting so that, as
`shown in equation (33) and equation (34)
`
`61-10(1) = 871L010) + BntorU + K/4) + BMOIU + 2K/4) + Mntot? + 3K/4)
`
`33
`(
`)
`
`These signals W0, obtained by the equation (40), are
`processed with a sign change, re-arraying and windowing
`for inverse transform, as shown by the equation (41), for
`calculating an N number of W1:
`
`?n)w0(n +N/4)
`
`O E I: § N/4 - 1
`
`(41)
`
`W101) =
`
`-?n)w0(3N/4 -1- n) N/4 é n g 3N/4 — 1
`
`—j(n)wo(n — 3N/4)
`
`3N/4 é n g N/l
`
`This may be found to be coincident with x1 de?ned by
`equation (8) as shown by the following.
`First, an equation (42) holds from the equations (8) and
`(9)
`
`BM,
`
`) + E,,,_0,(i + K14) - Emma + 2K14) - Mama + 3K14)
`
`0 § j E K14 - 1
`
`_
`
`0050104411» 1)/(4K))
`
`0 § j é K14 — 1
`
`(34)
`
`g” : sin(21rk(4(i— K14) + 1)/(4K))
`the equation (35)
`
`K14 é j é K12 _ 1
`
`25
`
`30
`
`35
`
`(35)
`
`holds, so that the volume of the integration and summation
`operation of the equation (21) may be halved.
`Besides, in carrying out the operation of IMDCI‘ with the
`signal processing method of the present invention, coe?i
`cient tables of the equations (14), (15) and (16), which are
`the same as those for MDCI‘, are used for integers m which
`are not less than 0 and not more than (N/(2K)—1). The
`following operations are repeated for integers m which are
`not less than 0 and not more than (N/(2K)—1).
`First, using the coe?icients of the equation (14), a K
`number of signals Po1 as given by the equation (36)
`
`N/2-1
`
`1
`N/
`PngOlG) = (25K)- GMJYMKI +1)
`[=0
`
`0 g j é K -1
`
`36
`(
`)
`
`N/2-1
`
`and a K number of signals P02 as given by the equation (37)
`
`55
`
`1
`N/
`511.020) = (2213K)- bmJyuUQ +1)
`1:0
`
`0 § j é K-1
`
`37
`(
`)
`
`are calculated from y11 of the equation (9).
`Then, from the coe?icients of equation (15) and from
`these signals P01, P02, two signal trains Q01, Q02, each
`having a length K, are calculated, as shown by the following
`equations (38), (39):
`
`If the equation (43)
`
`14
`
`

`
`is set. an equation (44)
`
`13
`
`5 ,646,960
`
`14
`
`(50)
`
`g1 Snead; + n/emmmm
`
`holds from the equations (14), (15). 36), (37), (38) and (39),
`in the same manner as the equation (24).
`Since the equations (45) and (46)
`
`holds. Since one of sine and cosine values in the equation
`(50) is 5 1. with the other value being 0. by setting so that.
`as shown in equation (51)
`
`15
`
`25
`
`and by using the equation (34), an equation (52)
`
`35
`
`holds. so that the volume of the integration and summation
`operations of equation (40) may be reduced to a quarter.
`It is seen from above that, with the method of the present
`invention. both MDCT de?ned by the equation (19 and
`IMDCI' de?ned by the equation (3) may be realized by
`integration of a k number of terms and summation. so that
`outputting of an N/2 number of signals may be executed by
`
`number of times of integration and summation operations
`and a
`
`number of coe?icient tables, so that the MDCT and IMDCT
`operations may be realized by a simpler hardware even
`although the number of times of the processing operations
`and the coef?cient tables are increased as compared to the
`conventional method.
`Returning to FIG. 2 and those following, a preferred
`embodiment for practicing the above-mentioned principle of
`the illustrated embodiment of the present invention is
`explained.
`That is, a signal transforming device for MDCT (MDCT
`calculation circuit 30) of the illustrated embodiment com
`prises an 1101 calculating circuit 33, as a forward transform
`ing Window unit for multiplying an input signal with a
`forward transforming window, and circuit components
`inclusive of an x02 calculating circuit 34 as a linear forward
`transforming unit for linear forward transforming an output
`signal of the x01 cal