Prentice Hall Series in Solid State Physical Electronics, Nick Holonyak, Jr., Series Editor
`
`

`

`
`F U R-
`
`= D
`
`N
`
`SolLi itate
`Electroni
`
`B.EN G. STREET
`Microelectronics Research Center
`Department of Electrical and Computer Engineering
`The University of Texas at Austin
`
`ev ces
`
`PREHME FMLL
`Englewood CThhTs, New Jersey 07458
`
`IPR2004-00108
`Exhibit MX027-1008, p. 2
`
`(cid:9)
`

`

`Library of Congress Cataloging-in-Publication Data
`Streetrnan, Ben G.
`Solid state electronic devices / Ben G. Streetman. — 4th ed.
`p. cm. — (Prentice Hall series in solid state physical
`electronics)
`Includes bibliographical references and index.
`ISBN 0-13-158767-6 (hard cover)
`I. Semiconductors. I. Title. II. Series.
`TK7871.85.S77 1995
`621.3815'2—dc20
`
`94-37720
`CIP
`
`Developmental Editor: Sondra Chavez
`Acquisitions Editor: Man Apt
`Production Editor: Joe Scordato
`Interior Design: Lee Cohen
`Cover Design: Amy Rosen
`Cover: Power PC RISC microprocessor chip courtesy of IBM Corp.
`Photograph by Tom Way.
`Manufacturing Buyer: Lori Bulwin
`
`©1995, 1990, 1980, 1972 by Prentice-Hall, Inc.
`A Simon & Schuster Company
`Upper Saddle River, New Jersey 07458
`
`All rights reserved. No part of this book may be
`reproduced, in any form or by any means,
`without permission in writing from the publisher.
`
`Printed in the United States of America
`
`10 9 8 7 6 5
`
`ISBN 0-13-158767 - 6
`
`Prentice-Hall International (UK) Limited, London
`Prentice-Hall of Australia Pty. Limited, Sydney
`Prentice-Hall Canada Inc., Toronto
`Prentice-Hall Hispanoamericana, S.A., Mexico
`Prentice-Hall of India Private Limited, New Delhi
`Prentice-Hall of Japan, Inc., Tokyo
`Simon & Schuster Asia Pte. Ltd., Singapore
`Editora Prentice-Hall do Brasil, Ltda., Rio de Janeiro
`
`IPR2004-00108
`Exhibit MX027-1008, p. 3
`
`

`

`1111.1imr
`
`Section 9.3 MONOLITHIC DEVICE ELEMENTS 347
`
`lem for bipolar circuits. We mentioned in Section 8.3.6 that using a field oxide
`about ten times as thick as the gate oxide increases V T, in these areas. We can-
`not make the field oxide arbitrarily thick, however, because of practical prob-
`lems of deposition and the fact that metallization patterns must be deposited
`over the "hills and valleys" of the resulting surface. A further increase in the
`field threshold voltage can be obtained by doping the region between transis-
`tors with the impurity type of the substrate (Fig. 9-13). For example, a mask-
`ing and implant or diffusion step can be used to dope the field region prior to
`forming the source and drain regions. Such doping increases VT in the field by
`increasing (:),/ (see Fig. 8-17). Combined with a small value of C, due to the
`thick field oxide, the Q d /C, term can lead to very high threshold voltage be-
`tween devices. The disadvantage of channel stop doping is that the breakdown
`voltage of the source and drain junctions is reduced by the more heavily doped
`channel stop. Therefore, it is necessary to control the field doping carefully to
`increase VT appropriately without significant lowering of the junction break-
`down voltage. This close control of doping makes ion implantation particularly
`attractive for this application.
`
`Reflow glass
`
`Poly-Si gate
`
`Figure 9-13
`
`p-Si
`
`Gate oxide
`
`Field oxide
`
`p + Channel stop
`
`The use of thick field oxide and channel stops to prevent inadvertent channel
`formation outside the active region of the MOS transistor. Shown also is a
`chemical-vapor deposited Si0 2 glass layer that will be patterned prior to
`metallization. This glass overlayer is often doped with phosphorus and boron
`and heated to the softening point to flatten out the surface before patterning
`for metallization (a process called reflow glass).
`LDD and Sidewall Spacers. The use of the lightly doped drain (LDD) struc-
`ture was described in Section 8.3.9 as a way of reducing the high field in the
`drain junction of small-geometry devices. Figure 9-14 illustrates the formation
`of an LDD transistor for application in integrated circuits. An important aspect
`of LDD fabrication is the use of sidewall spacers on each side of the gate.
`After foi ination of the thin gate oxide and polysilicon gate, an n-type implant
`forms the shallow, lightly doped source and drain regions (a). Then a thick
`oxide layer is deposited by a low-temperature chemical-vapor-deposition pro-
`
`IPR2004-00108
`Exhibit MX027-1008, p. 4
`
`

`

`348 Chapter 9 INTEGRATED CIRCUITS
`
`Poly-Si
`gate
`
`(cid:9)L_____Gate oxide
`
`(a)
`
`(b)
`
`(,)
`
`(d)
`
`Figure 9-14
`Fabrication of the
`lightly doped drain
`structure, using
`sidewall spacers.
`The polysilicon gate
`covers the thin gate
`oxide and masks
`the first low-dose
`implant (a). A thick (cid:9)
`oxide layer is
`deposited by low
`temperature CVD
`(b) and is
`anisotropically
`etched away to
`leave only the
`sidewall spacers (c).
`These spacers serve
`as a mask for the
`second, high-dose
`implant. After a (cid:9)
`drive-in diffusion,
`the LDD structure
`results (d).
`
`Sidewall spacer
`
`Lightly
`doped source & drain
`
`IPR2004-00108
`Exhibit MX027-1008, p. 5
`
`(cid:9)
`(cid:9)
`

`

`Section 9.3 MONOLITHIC DEVICE ELEMENTS 349
`
`cess (b). The oxide is then removed by reactive ion etching, leaving only the
`sidewall spacers (c), which serve as a mask for the second implant. This high-
`dose n + implant is then driven in by a diffusion step. The result is heavily
`doped source and drain regions, separated from the channel region by small
`lightly doped extensions.
`
`Self-aligned Sllicide.
`Since it is very important to reduce the series resis-
`tance of the gate and the source and drain regions for small-geometry devices,
`several techniques have been developed to improve the contact resistance. This
`is important not only because the areas of these regions decrease with smaller
`geometries, but also because shallower source and drain junctions are neces-
`sary as the device is scaled down, resulting in higher resistance regions. One
`approach to reducing substantially the resistance of the source and drain re-
`gions, and also the polysilicon gate region, is to use a refractory metal silicide
`to contact these regions. In Figure 9-15 the source—drain implant and sidewall
`spacer steps are followed by formation of a silicide simultaneously in the
`source, drain, and polysilicon gate regions. In this process, a thin layer of re-
`fractory metal is deposited and heated to form silicide wherever it touches ex-
`
`Poly-Si (cid:9)
`
`Spacer
`
`Silicide
`
`(a)
`
`(b)
`
`Figure 9-15
`The formation of
`silicided
`source—drain and
`gate regions for
`low-resistance
`contacts: (a) the
`source-drain
`implant is followed
`by formation of the
`sidewall spacers as
`in Fig. 9-14; (b) a
`layer of refractory
`metal is deposited
`and reacted in
`regions of exposed
`Si to form a
`conducting silicide
`layer; (c) the
`unreacted metal is
`removed and a
`CVD glass is
`deposited and
`patterned for
`contact
`metallization.
`
`IPR2004-00108
`Exhibit MX027-1008, p. 6
`
`

`

`350 Chapter 9 INTEGRATED CIRCUITS
`
`posed silicon. Various silicides, including PtSi, MoSi2 , CoSi2 , and TiSi2 have
`been used for this process. An advantage of the process shown in Fig. 9-15 is
`the fact that the source, drain, and gate silicide regions are formed simulta-
`neously, with the sidewall spacers serving to align the gate edges. This self-
`aligned silicide process is sometimes called salicide.
`Complementary MOS Devices. A particularly useful device for digital appli-
`cations is a combination of n-channel and p-channel MOS transistors on adja-
`cent regions of the chip. This complementary MOS (commonly called CMOS)
`combination is illustrated in the basic inverter circuit of Fig. 9-16a. In this cir-
`cuit the drains of the two transistors are connected together and form the out-
`put, while the input terminal is the common connection to the transistor gates.
`The p-channel device has a negative threshold voltage, and the n-channel tran-
`sistor has a positive threshold voltage. Therefore, a zero voltage input (V = 0)
`gives zero gate voltage for the n-channel device, but the voltage between the
`gate and source of the p-channel device is —V. Thus the p-channel device is
`on, the n-channel device is off, and the full voltage V is measured at K u, (i.e.,
`V appears across the nonconducting n-channel transistor). Alternatively, a posi-
`tive value of Vin turns the n-channel transistor on the p-channel off. The output
`voltage measured across the "on" n-channel device is essentially zero. Thus,
`the circuit operates as an inverter— with a binary "1" at the input, the output is
`in the "0" state, whereas a "0" input produces a "1" output. The beauty of this
`circuit is that one of the devices is turned off for either condition. Since the
`devices are connected in series, no drain current flows, except for a small
`charging current during the switching process from one state to the other. Since
`the CMOS inverter uses very little power, it is particularly useful in appli-
`
`+ v
`
`p-channet
`
`you,
`
`ID
`
`n-channel
`
`vim
`
`t
`
`Figure 9-16
`Complementary
`MOS structure:
`(a) CMOS inverter;
`(b) formation of
`p-channel and
`n-channel devices
`together.
`
`yin
`
`you,
`
`id
`
`(a)
`
`(b)
`
`IPR2004-00108
`Exhibit MX027-1008, p. 7
`
`