(12) United States Patent
`Nakagawa
`
`111111
`
`1111111111111111111111111111111111111111111111111111111111111
`US006359304B2
`US 6,359,304 B2
`*Mar.19,2002
`
`(10) Patent No.:
`(45) Date of Patent:
`
`(54) NONVOLATILE SEMICONDUCTOR
`MEMORY AND PROCESS FOR
`FABRICATING THE SAME
`
`(75)
`
`Inventor: Ken-ichiro Nakagawa, Tokyo (JP)
`
`(73) Assignee: NEC Corporation, Tokyo (JP)
`
`( *) Notice:
`
`This patent issued on a continued pros(cid:173)
`ecution application filed under 37 CFR
`1.53( d), and is subject to the twenty year
`patent term provisions of 35 U.S.C.
`154(a)(2).
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. No.: 09/449,760
`
`(22) Filed:
`
`Nov. 26, 1999
`
`(30)
`
`Foreign Application Priority Data
`
`Nov. 26, 1998
`
`(JP) ........................................... 10-335171
`
`Int. Cl? ................................................ H01L 29/76
`(51)
`(52) U.S. Cl. ....................... 257/314; 257/315; 257/316;
`257/317
`(58) Field of Search .................................. 257/314--317
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`5,856,691 A * 1!1999 Hazama ...................... 257/316
`
`6,064,592 A * 5!2000 Nakagawa et a!.
`
`. .. . 365/185.05
`
`FOREIGN PATENT DOCUMENTS
`
`JP
`JP
`JP
`JP
`
`61191052
`774326
`8167661
`10308502
`
`8/1986
`3/1995
`6/1996
`11/1998
`
`* cited by examiner
`
`Primary Examiner-Tom Thomas
`Assistant Examiner-Thien F Tran
`(74) Attorney, Agent, or Firm-Young & Thompson
`
`(57)
`
`ABSTRACT
`
`A nonvolatile semiconductor memory comprises a memory
`cell region including a number of memory cells formed
`therein and each having a floating gate and a control gate
`formed above the floating gate, a plurality of word lines
`extending in a first direction in parallel to each other,
`separately from each other, and a selection transistor region
`positioned adjacent to the memory cell region and including
`one selection transistor formed therein and a selection signal
`line extending in parallel to the word lines. The selection
`signal line is formed on an inactive region in a substrate to
`extend in parallel to a boundary line between the memory
`cell region and the selection transistor region.
`
`14 Claims, 9 Drawing Sheets
`
`200
`
`100
`
`200
`
`

`

`U.S. Patent
`
`Mar.19,2002
`
`Sheet 1 of 9
`
`US 6,359,304 B2
`
`Fig. 1 Prior Art
`
`61{~~~
`61{~~~
`
`52
`
`54
`
`55
`
`57
`
`56
`
`IPR2004-00108
`Exhibit MX027-1006, p. 2
`
`

`

`U.S. Patent
`
`Mar. 19, 2002
`
`Sheet 2 of 9
`
`US 6,359,304 B2
`
`Fig. 2 Prior Art
`
`66
`
`52
`
`Fig. 3A Prior Art
`
`Fig. 38 Prior Art
`
`52
`
`52
`
`52
`
`62
`
`65
`
`52
`51
`
`51
`
`51
`
`IPR2004-00108
`Exhibit MX027-1006, p. 3
`
`

`

`U.S. Patent
`US. Patent
`
`Mar.19,2002
`Mar. 19, 2002
`
`Sheet 3 of 9
`Sheet 3 0f 9
`
`US 6,359,304 B2
`US 6,359,304 B2
`
`Fig. 4
`Fig. 4
`
`7
`
`\\\\-\\\\ /
`\\\\‘-.\\\‘
`7////////////7/////////////////////4
`\\\\II\\\-\\\-\\\
`7////////////l7////////////////////A
`\\\II\\\-\\\-\\
`7////////////W//////////////////////.
`§llm\\\\I\\
`
`14A
`
`7///////////7/
`C \\\7//A“
`\\\\\7\\\\\/Au\
`////////////
`
`‘N\\\-\\\‘\\\-\\‘
`7//////////////////////////
`B
`\\-\\IEI\\\-\\
`7////%’{/9”””/7/////////////////
`
`200
`200
`
`100
`
`100
`
`200
`200
`
`mum 2 m—\\\\‘
`3A2
`
`23A 23
`
`21
`
`2
`
`23
`
`3
`
`6
`
`|PR2004-00108
`Exhibit MX027-1006, p. 4
`
`IPR2004-00108
`Exhibit MX027-1006, p. 4
`
`

`

`U.S. Patent
`
`Mar. 19, 2002
`
`Sheet 4 of 9
`
`US 6,359,304 B2
`
`Fig. 5A
`100
`
`200
`
`I
`")lot-<:
`I
`I
`I
`I
`I
`I
`
`2 1
`
`Fig. 5C
`
`30
`
`Fig. 50
`
`33
`
`22
`
`30
`
`1b
`
`IPR2004-00108
`Exhibit MX027-1006, p. 5
`
`

`

`U.S. Patent
`
`Mar. 19, 2002
`
`Sheet 5 of 9
`
`US 6,359,304 B2
`
`Fig. SE
`
`1 00 ----::>o~\ <~- 200
`
`I
`I
`
`40
`
`40
`
`33
`
`Fig. SF
`
`12
`
`5b
`33
`
`5
`
`11
`
`3
`
`41
`
`IPR2004-00108
`Exhibit MX027-1006, p. 6
`
`

`

`U.S. Patent
`
`Mar.19,2002
`
`Sheet 6 of 9
`
`US 6,359,304 B2
`
`1b
`
`23
`
`1b
`
`Fig. 6A
`
`21
`
`Fig. 68
`
`21
`
`Fig. 6C
`
`21
`
`Fig. 60
`
`30
`
`2
`
`21
`
`Fig. 6E
`
`1b
`
`30
`
`21
`
`23A
`
`1b
`
`21
`300
`
`24
`21
`300
`
`24
`21
`300
`
`33
`24
`21
`300
`
`40
`(41)
`
`33
`24
`21
`300
`
`IPR2004-00108
`Exhibit MX027-1006, p. 7
`
`

`

`U.S. Patent
`
`Mar. 19, 2002
`
`Sheet 7 of 9
`
`US 6,359,304 B2
`
`1b
`
`1b
`
`Fig. 7A
`
`21
`
`23
`
`23
`
`Fig. 78
`
`1b
`
`1b
`
`21
`
`Fig. 7C
`
`21
`
`Fig. 70
`
`24
`
`21
`
`23
`
`23
`
`23
`
`23
`
`23
`
`23
`
`24
`21
`300
`
`IPR2004-00108
`Exhibit MX027-1006, p. 8
`
`

`

`U.S. Patent
`
`Mar. 19, 2002
`
`Sheet 8 of 9
`
`US 6,359,304 B2
`
`Fig. 7E
`
`Fig. 7F
`24
`21
`
`~...,.....,_.....-.-.,
`
`32
`
`32
`
`24
`21
`
`Fig. 7H
`
`32
`
`32
`
`24
`21
`
`Fig. 71
`
`24
`21
`
`23
`
`23
`
`23
`
`24
`21
`300
`
`33
`24
`21
`300
`
`40
`
`33
`24
`21
`
`24
`21
`
`41
`
`IPR2004-00108
`Exhibit MX027-1006, p. 9
`
`

`

`U.S. Patent
`
`Mar. 19, 2002
`
`Sheet 9 of 9
`
`US 6,359,304 B2
`
`Fig. BA
`
`1 00
`
`I
`I
`
`)lo : <
`
`I
`
`200
`
`40A
`
`40A
`
`40B
`
`21
`
`Fig. 88
`
`41A
`
`I
`I
`I
`I
`
`I
`
`:~1 I
`: 120
`
`I
`I
`I
`
`I
`I
`I
`
`41B
`
`I
`I
`I
`I
`I
`
`41A
`
`21~
`)
`300
`
`(
`
`\
`
`"
`\
`5
`
`IPR2004-00108
`Exhibit MX027-1006, p. 10
`
`

`

`US 6,359,304 B2
`
`5
`
`15
`
`1
`NONVOLATILE SEMICONDUCTOR
`MEMORY AND PROCESS FOR
`FABRICATING THE SAME
`BACKGROUND OF THE INVENTION
`The present invention relates to a nonvolatile semicon-
`ductor memory and a process for fabricating the same, and
`more specifically to a nonvolatile semiconductor memory
`having a reduced chip area and a process for fabricating the
`same.
`Referring to FIG. 1, there is shown a diagrammatic plan 10
`view illustrating a prior art nonvolatile semiconductor
`memory. FIG. 2 is a diagrammatic sectional view taken
`along the line D-D in FIG. 1, and FIGS. 3A and 3B are
`views similar to that of FIG. 2 but showing different
`problems in the prior art nonvolatile semiconductor
`memory.
`In FIGS. 1, 2, 3A and 3B, Reference Number 51 desig(cid:173)
`nates a floating gate of a memory cell in the nonvolatile
`semiconductor memory, and Reference Number 52 denotes
`a control gate formed above the floating gate 51 and func(cid:173)
`tioning as a word line. Reference Number 53 indicates an 20
`insulating film between the floating gate 51 and the control
`gate 52. Reference Numbers 54 and 55 show a drain and a
`source of the memory cell, respectively, and Reference
`Number 56 designates a channel region between the drain 54
`and the source 55. Thus, one memory cell is formed by the 25
`drain 54, the source 55, the channel region 56 between the
`drain 54 and the source 55, and the floating gate 51 and the
`control gate 52 stacked above the channel region 56, and
`each memory cell is isolated by a device isolation region 57
`from adjacent memory cells.
`Reference Number 61 indicates a selection transistor
`(selector) for selecting the memory cells. The selection
`transistor 61 is controlled by a selection signal line 62
`functioning as a gate electrode.
`The nonvolatile semiconductor memory thus formed 35
`includes a memory cell region in which a number of memory
`cells are formed and a selection transistor region in which a
`plurality of selection transistors are formed. The memory
`cell region is adjacent to the selection transistor region, but
`since the memory cells and the selection transistors cannot
`be formed in completely the same process, when the 40
`memory cells are formed, the selection transistor region is
`masked, and when the selection transistors are formed, the
`memory cell region is masked. Therefore, because of a
`misalignment of the mask, an unetched portion 64 remains
`at a boundary between the memory cell region and the 45
`selection transistor region, as shown in FIG. 3A, and in a
`later process, the unetched portion 64 collapses, with the
`result that the yield of production is deteriorated.
`Alternatively, because of the misalignment of the mask, a
`substrate is overetched at the boundary between the memory so
`cell region and the selection transistor region, as shown with
`Reference Number 65 in FIG. 3B by two etchings, one of
`which is performed for forming the memory cells, and the
`other of which is performed for forming the selection
`transistors.
`In order to overcome the above problems, the prior art
`nonvolatile semiconductor memory was so constructed to
`have a dummy gate line 66 between the selection transistor
`region and the memory cell region, as shown in FIGS. 1 and
`2. However, if the dummy gate line 66 is provided, the chip
`area of the nonvolatile semiconductor memory inevitably
`becomes increased.
`BRIEF SUMMARY OF THE INVENTION
`Accordingly, it is an object of the present invention to
`provide a nonvolatile semiconductor memory which has
`overcome the above mentioned problem of the conventional
`prior art.
`
`2
`Another object of the present invention is to provide a
`nonvolatile semiconductor memory having a reduced chip
`area by making the dummy gate line unnecessary, and the
`process for fabricating the same.
`Still another object of the present invention is to provide
`a nonvolatile semiconductor memory including the selection
`signal line having the function of the dummy gate line,
`thereby to reduce a necessary chip area, and the process for
`fabricating the same.
`The above and other objects of the present invention are
`achieved in accordance with the present invention by a
`nonvolatile semiconductor memory comprising:
`a memory cell region including a number of memory cells
`formed therein and each having a floating gate and a
`control gate formed above the floating gate, and a
`plurality of word lines extending in a first direction in
`parallel to each other, separately from each other; and
`a selection transistor region positioned adjacent to the
`memory cell region and including one selection tran(cid:173)
`sistor formed therein and a selection signal line extend(cid:173)
`ing in parallel to the word lines;
`wherein the selection signal line is formed on an inactive
`region in a substrate to extend in parallel to a boundary
`line between the memory cell region and the selection
`transistor region.
`In an embodiment of the nonvolatile semiconductor
`memory, the inactive region includes a device isolation
`region formed in a principal surface of the substrate and a
`30 thick oxide film covering a diffused region formed in the
`principal surface of the substrate. For example, the selection
`signal line includes a layer which is formed of the same
`material as that of the control gate, and extends in parallel
`to the boundary line between the memory cell region and the
`selection transistor region, at a position retracting from the
`boundary line between the memory cell region and the
`selection transistor region.
`According to another aspect of the present invention,
`there is provided a nonvolatile semiconductor memory com(cid:173)
`prising;
`a memory cell region including a number of memory cells
`formed therein and each having a floating gate and a
`control gate formed above the floating gate, and a
`plurality of word lines extending in a first direction in
`parallel to each other, separately from each other; and
`a selection transistor region positioned adjacent to the
`memory cell region and including one selection tran(cid:173)
`sistor formed therein and a selection signal line extend(cid:173)
`ing in parallel to the word lines;
`wherein the selection signal line includes a first layer
`which is formed of the same material as that of the
`floating gate and a second layer which is formed of the
`same material as that of the control gate.
`Preferably, the selection signal line includes a short selec-
`ss tion signal line extending therefrom in a second direction
`orthogonal to the first direction and going apart from the
`memory cell region, an end of the short selection signal line
`constituting a gate of the selection transistor.
`In addition, the selection signal line includes a side
`surface extending on and along the boundary line between
`the memory cell region and the selection transistor region.
`In a preferred embodiment, the selection signal line
`includes a short selection signal line extending therefrom in
`a second direction orthogonal to the first direction and going
`65 apart from the memory cell region, an end of the short
`selection signal line constituting a gate of the selection
`transistor.
`
`60
`
`IPR2004-00108
`Exhibit MX027-1006, p. 11
`
`

`

`US 6,359,304 B2
`
`10
`
`3
`According to a third aspect of the present invention, there
`is provided a process for fabricating a nonvolatile semicon(cid:173)
`ductor memory which has a memory cell region including a
`number of memory cells formed therein and each having a
`floating gate and a control gate formed above the floating 5
`gate, and a plurality of word lines extending in a first
`direction in parallel to each other, separately from each
`other, and a selection transistor region positioned adjacent to
`the memory cell region and including one selection transis-
`tor formed therein and a selection signal line extending in
`parallel to the word lines, the processing comprising the
`steps of:
`forming a device isolation film on a principal surface of
`a semiconductor substrate, forming a tunnel insulator
`film for the memory cells on the principal surface of the
`semiconductor substrate, forming a floating gate film 15
`on the tunnel insulator film, partially patterning the
`floating gate film, and forming source/drain regions at
`opposite sides of the partially patterned floating gate
`film by using the partially patterned floating gate film
`as a mask; forming an oxide film to cover the whole 20
`surface of the semiconductor substrate, and etching
`back the oxide film until an upper surface of the
`partially patterned the floating gate film;
`removing the partially patterned floating gate film from
`the selection transistor region;
`forming on the whole surface of the semiconductor sub(cid:173)
`strate an insulating film for insulating between the
`floating gate and the control gate, and removing the
`insulating film from the selection transistor region;
`forming a gate insulator film for the selection transistor;
`forming a polysilicon film on the whole surface of the
`semiconductor substrate;
`selectively etching the polysilicon film and the partially
`patterned floating gate film under the polysilicon film 35
`within the memory cell region to form a control gate
`and a underlying floating gate while etching one side
`surface of the selection signal line, extending on and
`along a boundary line between the memory cell region
`and the selection transistor region; and
`selectively etching the polysilicon film within the selec(cid:173)
`tion transistor region to form a gate of the selection
`transistor while etching the other side surface of the
`selection signal line.
`According to a fourth aspect of the present invention, 45
`there is provided a process for fabricating a nonvolatile
`semiconductor memory which has a memory cell region
`including a number of memory cells formed therein and
`each having a floating gate and a control gate formed above
`the floating gate, and a plurality of word lines extending in 50
`a first direction in parallel to each other, separately from
`each other, and a selection transistor region positioned
`adjacent to the memory cell region and including one
`selection transistor formed therein and a selection signal line
`extending in parallel to the word lines, the processing 55
`comprising the steps of:
`forming a device isolation film on a principal surface of
`a semiconductor substrate so that the device isolation
`film extends over a boundary region between the
`memory cell region and the selection transistor region, 60
`forming a tunnel insulator film for the memory cells on
`the principal surface of the semiconductor substrate,
`forming a floating gate film on the tunnel insulator film,
`partially patterning the floating gate film, and forming
`source/drain regions at opposite sides of the partially 65
`patterned floating gate film by using the partially pat(cid:173)
`terned floating gate film as a mask;
`
`25
`
`30
`
`40
`
`4
`forming an oxide film to cover the whole surface of the
`semiconductor substrate, and etching back the oxide
`film until an upper surface of the partially patterned the
`floating gate film;
`removing the partially patterned floating gate film from
`the selection transistor region;
`forming on the whole surface of the semiconductor sub(cid:173)
`strate an insulating film for insulating between the
`floating gate and the control gate, and removing the
`insulating film from the selection transistor region;
`forming a gate insulator film for the selection transistor;
`forming a polysilicon film on the whole surface of the
`semiconductor substrate;
`selectively etching the polysilicon film and the partially
`patterned floating gate film under the polysilicon film
`within the memory cell region to form a control gate
`and a underlying floating gate by using a mask sub(cid:173)
`stantially completely covering the selection transistor
`region and having a side surface which slightly retracts
`from the boundary line between the selection transistor
`region and the memory cell region and which is still
`positioned on the device isolation region; and
`selectively etching the polysilicon film within the selec(cid:173)
`tion transistor region to form a gate of the selection
`transistor by using a mask substantially completely
`covering the memory cell region and having a side
`surface which slightly retracts from the boundary line
`between the selection transistor region and the memory
`cell region and which is still positioned on the device
`isolation region.
`The above and other objects, features and advantages of
`the present invention will be apparent from the following
`description of preferred embodiments of the invention with
`reference to the accompanying drawings.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a diagrammatic plan view illustrating a prior art
`nonvolatile semiconductor memory;
`FIG. 2 is a diagrammatic sectional view taken along the
`line D-D in FIG. 1;
`FIGS. 3A and 3B are views similar to that of FIG. 2 but
`showing different problems in the prior art nonvolatile
`semiconductor memory;
`FIG. 4 is a diagrammatic plan view illustrating a first
`embodiment of the nonvolatile semiconductor memory in
`accordance with the present invention;
`FIGS. SA to SF are diagrammatic sectional views taken
`along the line A-A in FIG. 4 to show a boundary region
`between a memory cell region and a selection transistor
`region, for illustrating a first embodiment of the process in
`accordance with the present invention for fabricating the
`nonvolatile semiconductor memory in accordance with the
`present invention;
`FIGS. 6A to 6E are diagrammatic sectional views taken
`along the line B-B in FIG. 4 to show the memory cell
`region, for illustrating the first embodiment of the process in
`accordance with the present invention for fabricating the
`nonvolatile semiconductor memory in accordance with the
`present invention;
`FIGS. 7A to 7I are diagrammatic sectional views taken
`along the line C-C in FIG. 4 to show the selection transistor
`region, for illustrating the first embodiment of the process in
`accordance with the present invention for fabricating the
`nonvolatile semiconductor memory in accordance with the
`present invention; and
`
`IPR2004-00108
`Exhibit MX027-1006, p. 12
`
`

`

`US 6,359,304 B2
`
`10
`
`20
`
`5
`FIGS. SA and 8B are views similar to those of FIGS. SE
`and SF, but illustrating a second embodiment of the process
`in accordance with the present invention for fabricating the
`nonvolatile semiconductor memory in accordance with the
`present invention.
`DETAILED DESCRIPTION OF 1HE
`INVENTION
`Referring to FIG. 4, there is shown a diagrammatic plan
`view illustrating a first embodiment of the nonvolatile
`semiconductor memory in accordance with the present
`invention, which is a flash memory.
`As shown in FIG. 4, the shown nonvolatile semiconductor
`memory includes a selection transistor region 100 interposed
`between a pair of memory cell regions 200. In each memory
`cell region 200, a number of word lines 6 are formed to
`extend in parallel to each other.
`As shown in FIGS. SE and SF which are diagrammatic
`sectional views taken along the line A-A in FIG. 4 for
`illustrating an intermediate condition of the process for
`fabricating the nonvolatile semiconductor memory, the word
`line 6 constitutes a control electrode 2 of a floating gate
`MOS transistor, and under the control electrode 2, a floating
`gate 1 is formed, insulated from the control gate by an
`insulating layer 30.
`Returning to FIG. 4, a pair of diffused source/drain
`regions 23 are formed at a surface region of a semiconductor
`substrate at opposite sides of the floating gate, respectively,
`and a surface region of the semiconductor substrate under
`the floating gate constitutes a channel region 23A. Thus, a
`number of memory cells 3 are formed in each memory cell
`region 200. Incidentally, the memory cells 3 are isolated by
`a device isolation region 21 from adjacent memory cells in
`the direction of the word line 6.
`In the selection transistor region 100, two selection signal
`lines S are formed to extend in parallel to each other in the 35
`same direction as that of the word lines 6. Each of the
`selection signal lines S extends along a boundary of a
`corresponding memory cell region 200. As shown in FIGS.
`SE and SF, each of the selection signal lines S is composed
`of a first layer 11 which is formed of the same material as
`that of the floating gate 1 and a second layer 12 which is
`formed of the same material as that of the control gate 2.
`As shown in FIG. 4, each of the two selection signal lines
`S has a short selection signal line 1S extending therefrom in
`a direction orthogonal to the selection signal line S toward
`the other selection signal line but in a staggered relation to
`the short selection signal line 1S extending from the other
`selection signal line. A tip end portion 1Sa of each short
`selection signal line 1S constitutes a gate 14 of a selection
`transistor 4.
`As shown in FIG. 71 which is a diagrammatic sectional
`view taken along the line C-C in FIG. 4 for illustrating an
`intermediate condition of the process for fabricating the
`nonvolatile semiconductor memory, a pair of diffused
`source/drain regions 23 are formed at a surface region of a
`semiconductor substrate at opposite sides of each gate 14,
`respectively. A surface region of the semiconductor substrate
`under the gate 14 constitutes a channel region. Thus, the
`selection transistor 4 is formed. As shown in FIG. 4, the
`common diffused source/drain region 23 of each two selec(cid:173)
`tion transistors 4 is connected through a contact 14A to an
`interconnection layer (not show, acting as a main bit line) of
`a different level, and the other of the pair of source/drain
`regions 23 in each selection transistor 4 joins with one
`(drain) of the pair of source/drain regions 23 of memory
`cells in one corresponding array orthogonal to the word lines
`6.
`
`6
`Next, a first embodiment of the process in accordance
`with the present invention for fabricating the nonvolatile
`semiconductor memory in accordance with the present
`invention will be described with reference to FIGS. SA to SF
`5 which are diagrammatic sectional views taken along the line
`A-A in FIG. 4 to show a boundary region between a
`memory cell region and a selection transistor region, FIGS.
`6A to 6E which are diagrammatic sectional views taken
`along the line B-B in FIG. 4 to show the memory cell
`region, and FIGS. 7A to 71 which are diagrammatic sec(cid:173)
`tional views taken along the line C-C in FIG. 4 to show the
`selection transistor region.
`After a device isolation film 21 is selectively formed in a
`principal surface of a semiconductor substrate 300, a tunnel
`15 insulator film 22 and a partially patterned floating gate film
`1b is formed of polysilicon on the principal surface of the
`semiconductor substrate 300, and impurity is ion-implanted
`using the partially patterned floating gate film 1b as a mask,
`to form diffused source/drain regions 23 at opposite sides of
`each partially patterned floating gate film 1b in a surface
`region of the semiconductor substrate 300 confined by the
`device isolation film 21, as shown in FIGS. SA, 6A and 7 A
`Further, after a thick oxide film 24 (of for example a 100
`nm thickness) is formed to cover the source/drain regions
`25 23, the oxide film 24 is etched back until an upper surface
`of the partially patterned floating gate film 1b is exposed, as
`shown in FIGS. SA, 6B and 7B. Here, it is important that
`after the etching-back process, the source/drain regions 23
`are still covered by the thick oxide film 24. In this
`30 connection, the method for forming the source/drain regions
`23 is not limited to the method mentioned above, but it
`would be apparent to persons skilled in the art that the
`source/drain regions 23 can be formed by various methods
`other than the above mentioned method. In addition, in order
`to increase a capacitance ratio of the memory cell, a second
`floating gate can be formed to increase an overlapping area
`between the control gate and the floating gate.
`Thereafter, the partially patterned floating gate film 1b in
`the selection transistor region 100 is selectively removed as
`40 shown in FIGS. SB, 6B and 7C. At this time, as shown in
`FIG. SB, the partially patterned floating gate film 1b is
`selectively etched so that an end portion la of the partially
`patterned floating gate film 1b projects from the memory cell
`region 200 to a center line of a selection signal line S formed
`45 in a later stage, with the result that the tunnel insulator film
`22 is in no way exposed in the memory cell region 200.
`Therefore, an end face of the remaining portion la in the
`selection transistor region 100 corresponds to the center line
`of the selection signal line S formed in the later stage.
`In order to insulate the floating gate 1 from the control
`gate 2, an ONO (oxide-nitride-oxide) film 30 is formed to
`cover the whole surface as shown in FIGS. SC, 6C and 7D,
`and then, the ONO film 30 is selectively removed from the
`selection transistor region 100, as shown in FIGS. SC, 6C
`55 and 7E. Here, the ONO film 30 is selectively removed so
`that the remaining ONO film 30 covers the end face of the
`end portion la of the partially patterned floating gate film 1b
`remaining in the selection transistor region 100.
`Furthermore, after a gate oxide film 32 is formed as
`60 shown in FIGS. SC, 6C and 7F, a polysilicon film 33 is
`formed on the whole surface, as shown in FIGS. SD, 6D and
`7G. This polysilicon film 33 will become the control gate 2
`(namely, the word line 6), the gate 14 of the selection
`transistor 4 and the selection signal line S after it is patterned
`65 in a later step. Thereafter, in order to reduce a resistance of
`the word line 6, tungsten silicide (WSi) can be deposited on
`the polysilicon film 33 by sputtering.
`
`50
`
`IPR2004-00108
`Exhibit MX027-1006, p. 13
`
`

`

`US 6,359,304 B2
`
`10
`
`7
`In order to form the control gates and the floating gates in
`the memory cell region 200 and in order to form the
`selection signal line S positioned at the boundary between
`the selection transistor region 100 and each memory cell
`region 200, a photo resist 40 is formed on the whole surface
`and then patterned as shown in FIGS. SE, 6E and 7H, and
`the stacked layers consisting of the partially patterned float(cid:173)
`ing gate film 1b, the ONO film 30 and the polysilicon film
`33 in each memory region 200 is patterned by an etching as
`shown in FIGS. SE, 6E and 7H. At this time, since the
`selection transistor region 100 is completely covered with
`the photo resist 40, the polysilicon film 33 in the selection
`transistor region 100 is not etched. On the other hand, since
`the stacked layers of the partially patterned floating gate film
`1b, the ONO film 30 and the polysilicon film 33 remaining
`in the selection transistor region 100 is etched along a
`boundary line between the selection transistor region 100
`and each memory cell region 200, the stacked layers of the
`partially patterned floating gate film 1b, the ONO film 30
`and the polysilicon film 33 remaining in the selection
`transistor region 100 has a side face Sa exposed and extend(cid:173)
`ing along the boundary line between the selection transistor
`region 100 and each memory cell region 200.
`Furthermore, in order to form the selection signal line S,
`the short selection signal line 1Sa and the gate 14 in the
`selection transistor region 100, a photo resist 41 is formed on
`the whole surface and then patterned as shown in FIGS. SF,
`6E and 71, and the polysilicon film 33 in the selection
`transistor region 100 is patterned by an etching as shown in
`FIGS. SF, 6E and 71. Thus, an opposite side surface Sb of the 30
`selection signal line S is formed. At this time, since the
`memory cell regions 200 are completely covered with the
`photo resist 41, the stacked structure consisting of the
`floating gate 1, the ONO film 30 and the control gate 2 is not
`etched. Furthermore, it is preferred to etch transistors in a
`peripheral circuit at this process. Thereafter, contacts and
`interconnections are formed in a conventional process to
`complete a flash memory cell array.
`In the above mentioned process, the etching for forming
`the selection transistors and the etching for forming the
`memory cell transistors can be reversed in order with no
`problem.
`In the above mentioned process, the portion la of the
`floating gate 1 remains at a side adjacent to the memory cell
`region, of a lower portion of the selection signal line.
`However, the floating gate portion 1a remaining at a side
`adjacent to the memory cell region, of the lower portion of
`the selection signal line, can be omitted.
`Now, a process for forming the modified structure will be
`described with FIGS. SA and SB which are views similar to 50
`those of FIGS. SE and SF, but illustrating a second embodi(cid:173)
`ment of the process in accordance with the present invention
`for fabricating the modified structure of the nonvolatile
`semiconductor memory in accordance with the present
`invention.
`In this process, after the steps which are substantially the
`same as the steps shown in FIGS. SA to SD are performed,
`the partially patterned floating gate film 1b is selectively
`etched. At this time, the device isolation region 21 continu(cid:173)
`ing from the selection transistor region 100 extends beyond
`a boundary line 110 between the selection transistor region
`100 and the memory cell region 200, into the memory cell
`region 200. On the other hand, the end portion 1a of the
`partially patterned floating gate film 1b shown in FIG. SB
`terminates on the boundary line 110 between the selection
`transistor region 100 and the memory cell region 200,
`differently from the condition shown in FIGS SB to SF.
`
`8
`When the control gates are formed in the memory cell
`regions 200, the photo resist 40A is so patterned that the
`patterned photo resist 40Asubstantially completely covering
`the selection transistor region 100 has a side surface 40B
`5 which intentionally slightly retracts from the boundary line
`110 between the selection transistor region 100 and the
`memory cell region 200 and which is still positioned on the
`device isolation region 21 as shown in FIG. SA In the
`memory cell regions 200, on the other hand, the patterned
`photo resist 40Ahas a plan shape corresponding to the word
`lines 6. Thus, in only the memory cell regions 200, the
`stacked layers consisting of the partially patterned floating
`gate film 1b, the ONO film 30 and the polysilicon film 33 is
`patterned by an etching to form the word line 6 and the
`stacked structure consisting of the floating gate 1, the ONO
`15 film 30 and the control gate 2.
`Then, when the selection signal lines and the gates are
`formed in the selection transistor region 100, the patterned
`photo resist 41A is so formed that the patterned photo resist
`41A substantially completely covering the memory cell
`20 region 200 has a side surface 41B which intentionally
`slightly retracts from the boundary line 110 between the
`selection transistor region 100 and the memory cell region
`200 and which is still positioned on the device isolation
`region 21 continuing from the selection transistor region 100
`25 to extend beyond the boundary line 110 into the memory cell
`region 200, as shown in FIG. SB. In the selection transistor
`region 100, on the other hand, the patterned photo resist 41A
`has a plan shape corresponding to the selection signal line S,
`the short selection signal line 1Sa and the gate 14.
`In this modified process, a region 120 on the substrate 300
`between the side surface 40B of the photo resist 40A and the
`side s