(12) United States Patent
`Yuzuriha et al.
`
`111111
`
`1111111111111111111111111111111111111111111111111111111111111
`US006458655Bl
`US 6,458,655 Bl
`Oct. 1, 2002
`
`(10) Patent No.:
`(45) Date of Patent:
`
`(54) METHOD OF MANUFACTURING
`SEMICONDUCTOR DEVICE AND FLASH
`MEMORY
`
`(75)
`
`Inventors: Kojiro Yuzuriha, Hyogo (JP); Shu
`Shimizu, Hyogo (JP); Tamotsu
`Tanaka, Hyogo (JP); Takashi Yano,
`Hyogo (JP)
`
`(73) Assignees: Mitsubishi Denki Kabushiki Kaisha,
`Tokyo (JP); Ryoden Semiconductor
`System Engineering, Hyogo (JP)
`
`( *) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. No.: 09/588,475
`
`(22) Filed:
`
`Jun. 7, 2000
`
`(30)
`
`Foreign Application Priority Data
`
`Jan. 17, 2000
`
`(JP) ....................................... 2000-007585
`
`Int. Cl? .............................................. HOlL 21/336
`(51)
`(52) U.S. Cl. ....................... 438/257; 438/264; 438/266;
`438/593; 438/594; 438/763; 438/689; 438/695;
`438/706; 438/725
`(58) Field of Search ................................. 438/257, 266,
`438/264, 593, 594, 763, 689, 695, 706,
`725
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`5,210,047 A * 5/1993 Woo et a!. .................... 437/43
`5,460,991 A * 10/1995 Hong .......................... 437/43
`5,631,178 A * 5/1997 Vogel et a!.
`5,789,293 A * 8/1998 Cho eta!. ................... 438/257
`6,040,216 A * 3/2000 Sung .......................... 438/257
`6,117,732 A * 9/2000 Chu eta!. ................... 438/264
`
`* cited by examiner
`
`Primary Examiner-Michael Sherry
`Assistant Examiner-Lisa Kilday
`(74) Attorney, Agent, or Firm-McDermott, Will & Emery
`
`(57)
`
`ABSTRACT
`
`A semiconductor manufacturing method is mainly
`contemplated, improved to prevent an altered surface layer
`of a resist from being removed when a single patterned resist
`is used to provide dry-etch and wet-etch successively. On a
`semiconductor substrate an insulation film and a conductive
`layer are formed successively. On the conductive layer a
`patterned resist is formed. With the patterned resist used as
`a mask, the conductive layer is dry-etched. A surface layer
`of the patterned resist is partially removed. With the pat(cid:173)
`terned resist used as a mask, the insulation film is wet(cid:173)
`etched.
`
`5 Claims, 12 Drawing Sheets
`
`DUMMY GATE PERIPHERAL
`!<MEMORY CELL REGION
`REGION
`CIRCUITRY REGION
`>!
`>I<
`~I<
`16 1 0 11 13 11 a 1 0~ 14
`
`16
`
`13
`
`16
`13
`16
`11
`13
`10
`9~~--~~~~~L__ijdr~~~~~~~
`1
`
`11 9 10
`
`9
`
`8
`
`12
`
`

`

`U.S. Patent
`
`Oct. 1, 2002
`
`Sheet 1 of 12
`
`US 6,458,655 Bl
`
`FIG. 1
`
`------------------------, I
`
`I
`I
`I
`I
`I
`
`3~
`
`2-?~~~~==~------------~
`
`1~------------------3
`
`FIG. 2
`
`3
`2
`1
`
`z z z 7 fj
`~
`
`IPR2014-00108
`Exhibit MX027-1003, p. 2
`
`

`

`U.S. Patent
`
`Oct. 1, 2002
`
`Sheet 2 of 12
`
`US 6,458,655 Bl
`
`FIG. 3
`ouv-t I I I I I ,I I
`
`3
`2
`1
`
`6
`
`4
`
`FIG. 4
`
`3
`2-?~~~~~~~CZ~LZ~
`1
`
`IPR2014-00108
`Exhibit MX027-1003, p. 3
`
`

`

`U.S. Patent
`
`Oct. 1, 2002
`
`Sheet 3 of 12
`
`US 6,458,655 Bl
`
`FIG. 5
`
`DUMMY GATE PERIPHERAL
`>!SIRCUITR~REGION
`!<MEMORY CELL REGION>!< REGION
`
`16
`
`13
`
`16 1 0 11 13 11 a 1 0~ 14
`
`16
`13
`11
`10
`9~~--~~~~~~--4
`1
`~-~~--
`
`911910
`
`9
`
`8
`
`12
`
`FIG. 6
`
`15
`
`11~~~~~~~~~~~~~~~~~~~~
`10
`g~~~~~~~~~be~
`1
`~~~~
`
`8
`
`9
`
`IPR2014-00108
`Exhibit MX027-1003, p. 4
`
`

`

`U.S. Patent
`
`Oct. 1, 2002
`
`Sheet 4 of 12
`
`US 6,458,655 Bl
`
`FIG. 7
`
`15
`11~~~~~~~~~~~
`10
`9~da~~~~~~~
`1
`
`8
`
`9
`
`FIG. 8
`
`C B A
`
`t t t
`
`16
`13
`11~27777777~7777~~~~~
`10 9~~~~~~~~~75~~~~
`1
`
`8
`
`12
`
`IPR2014-00108
`Exhibit MX027-1003, p. 5
`
`

`

`U.S. Patent
`
`Oct. 1, 2002
`
`Sheet 5 of 12
`
`US 6,458,655 Bl
`
`FIG. 9
`
`16 1316
`
`16
`
`13 11 a 1 Oa 16
`/
`
`14
`
`16
`13
`11~~~~~~~~~~~
`10
`9~~~~~~~~77~~~~~
`1
`
`~~-,-._ __ 16
`~~·-13
`
`8
`
`12
`
`FIG. 10
`
`16 13 16
`
`16
`13
`1 1
`10
`9~~--~~~~~~--~
`1
`
`16 1 0 11 13 11 a 1 Oa
`J?/
`16
`
`14
`
`9 11 9 10
`
`9
`
`8
`
`12
`
`IPR2014-00108
`Exhibit MX027-1003, p. 6
`
`

`

`U.S. Patent
`
`Oct. 1, 2002
`
`Sheet 6 of 12
`
`US 6,458,655 Bl
`
`FIG. 11
`
`PRIOR ART
`
`1 1
`
`10
`2a
`
`~~----4---9
`~~~
`~·--t-----1-----1---- 8
`~~~
`
`13 3 12
`
`FIG. 12
`
`PRIOR ART
`
`FIG. 13
`
`PRIOR ART
`
`4
`2b
`1a
`1
`
`9
`8
`4
`3
`
`1a
`
`1
`
`IPR2014-00108
`Exhibit MX027-1003, p. 7
`
`

`

`U.S. Patent
`
`Oct. 1, 2002
`
`Sheet 7 of 12
`
`US 6,458,655 Bl
`
`FIG. 14
`
`PRIOR ART
`
`1a
`
`1
`
`3 4 8
`
`FIG. 15
`
`PRIORl ART
`
`2a
`
`3 4 8
`
`IPR2014-00108
`Exhibit MX027-1003, p. 8
`
`

`

`U.S. Patent
`
`Oct. 1, 2002
`
`Sheet 8 of 12
`
`US 6,458,655 Bl
`
`FIG. 16
`
`PRIOR ART
`
`3
`2
`1
`
`FIG. 17
`
`PRIOR ART
`
`5
`3
`2~2=~~~=e==~--~~=z~~~2
`1
`
`IPR2014-00108
`Exhibit MX027-1003, p. 9
`
`

`

`U.S. Patent
`
`Oct. 1, 2002
`
`Sheet 9 of 12
`
`US 6,458,655 Bl
`
`FIG. 18
`
`------------------------,
`
`I
`I
`I
`I
`I
`I
`I
`I
`
`3___...
`2~~~~~Cc~~-----------------
`
`1~~--------------------3
`
`FIG. 19
`
`r r r.,.. ..,....,.-,...-,-,-r 7" '7' ..,.-.,..-..--,-,- .,....,.. ..,....,.-~
`__......_._, / / / / / / / / / / / / / / / / / / "",1
`6
`/ A
`/ I
`/)
`/I
`/,/J
`/I
`/ 1
`
`3~
`~=~:~~~~~~~r-~~-:~~z~z--z~z~-~~
`
`IPR2014-00108
`Exhibit MX027-1003, p. 10
`
`

`

`U.S. Patent
`
`Oct. 1, 2002
`
`Sheet 10 of 12
`
`US 6,458,655 Bl
`
`FIG. 20
`
`ouv7 I I I I I I I
`
`6
`7-
`4__,..._,
`
`~~-'--~-'---#--~:....:.:
`
`FIG. 21
`
`7
`
`3
`2
`1
`
`6
`
`3
`~~~~~~=:~z~z~z~z~zq3
`
`IPR2014-00108
`Exhibit MX027-1003, p. 11
`
`

`

`U.S. Patent
`
`Oct. 1, 2002
`
`Sheet 11 of 12
`
`US 6,458,655 Bl
`
`FIG. 22
`
`~----------------~--wL
`Vee
`
`ACCESS
`TRANSISTOR 2
`
`BIT
`
`/
`
`STORAGE
`KODE2
`
`DRIVER
`TRANSISTOR 1
`
`ACCESS
`
`TRANSISTOR 1 BIT\
`
`STORAGE NO/[
`
`DRIVER
`TRANSISTOR 2
`
`FIG. 23
`
`GND
`
`56
`
`54
`53
`
`52
`
`51
`
`PWELL
`
`N SUBSTRATE
`
`IPR2014-00108
`Exhibit MX027-1003, p. 12
`
`

`

`U.S. Patent
`
`Oct. 1, 2002
`
`Sheet 12 of 12
`
`US 6,458,655 Bl
`
`FIG. 24
`
`56
`
`55
`
`54
`
`FIG. 25
`
`57
`
`1
`
`IPR2014-00108
`Exhibit MX027-1003, p. 13
`
`

`

`US 6,458,655 Bl
`
`1
`METHOD OF MANUFACTURING
`SEMICONDUCTOR DEVICE AND FLASH
`MEMORY
`
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`The present invention relates generally to methods of
`manufacturing semiconductor devices and particularly to
`methods of manufacturing semiconductor devices including
`a step of dry etch and wet etch provided successively. The
`present invention also relates to methods of manufacturing
`flash memories including a step of dry etch and wet etch
`provided successively. The present invention also relates to
`flash memories manufactured by such manufacturing meth(cid:173)
`ods. The present invention also relates to methods of manu(cid:173)
`facturing static random access memories (SRAMs).
`2. Description of the Background Art
`FIG. 11 shows a cross section of a memory cell of a
`conventional flash memory.
`Referring to FIG. 11, in a surface of a semiconductor
`substrate containing a p dopant a p doped region 1a is
`formed. On semiconductor substrate 1 a floating gate 4 is
`formed with a tunnel oxide film 3 posed therebetween. In a
`surface of p doped region 1a on opposite sides of floating 25
`gate 4, source/drain regions 2a and 2b are formed. On
`floating gate 4 an insulation film 8 is formed. On insulation
`film 8 a control gate 9 is formed. On semiconductor sub(cid:173)
`strate 1, insulation layers 10 and 11 are formed such that they
`cover control gate 9.
`The flash memory operates as described below.
`In write operation, drain region 2b receives a drain
`voltage of approximately 6 to SV and control gate 9 receives
`a gate voltage of approximately 10 to 15V. Source region 2a
`and semiconductor substrate 1 have a voltage held at a 35
`ground voltage. As such a current of several hundreds fAA
`flows through a channel region 2c. Of the electrons flowing
`from source region 2a to drain region 2b, the electrons
`accelerated in a vicinity of drain region 2b becomes those
`with high energy (i.e., hot electrons). Such electrons flow in 40
`a direction indicated by an arrow 12 due to an electric field
`resulting from the gate voltage applied to control gate 9, and
`are thus introduced into floating gate 4. As such electrons
`accumulate in floating gate 4, the transistor's threshold
`voltage is increased. Such threshold voltage higher than a 45
`predetermined value corresponds to a state. referred to as
`"0".
`In data erase operation, initially source region 2a receives
`a source voltage of approximately 10 to 15V and control
`gate 9 and semiconductor substrate 1 are held at a ground
`potential. Then, drain region 2b is floated, and an electric
`field resulting from the source voltage applied to source
`region 2a allows the electrons accumulated in floating gate
`4 to flow in a direction indicated by an arrow 13, passing
`through tunnel insulation film 3 into semiconductor sub(cid:173)
`strate 1. When the electrons accumulated internal to floating
`gate 4 are extracted, the transistor's threshold is increased.
`Such threshold voltage lower than a predetermined value
`corresponds to a state with data erased, referred to as "1".
`Such erasure allows collective erasure of memory cells 60
`formed in a single semiconductor device. In read operation,
`control gate 9 receives a gate voltage of approximately SV
`and drain region 2b receives a drain voltage of approxi(cid:173)
`mately 1 to 2V, and then if channel region 2c passes current
`or the transistor is ON then data is determined to be "1" and 65
`if channel region 2c does not pass current or the transistor is
`OFF then data is determined to be "0".
`
`5
`
`2
`A flash memory configured as described above is manu(cid:173)
`factured by a method as described below.
`Initially, as shown in FIG. 12, an element isolating oxide
`film is formed on a semiconductor substrate 1 of monoc-
`rystalline silicon to isolate memory cells from each other,
`isolate transistors in peripheral circuitry from each other,
`and isolate the cells and the peripheral transistors from each
`other. Then p doped region 1a in which memory cells are to
`be formed is formed. Then the substrate's upper surface is
`10 oxidized to provide a tunnel insulation film 3 of silicon
`dioxide (Si0 2 ).
`Referring to FIG. 13, chemical vapor deposition (CVD) is
`employed to deposit poly crystalline silicon on tunnel insu(cid:173)
`lation film 3. The polycrystalline silicon only in the memory
`15 cell region is etched in an x direction (a direction horizontal
`relative to the plane of the figure, not shown) to form a
`floating gate 4. Then, chemical vapor deposition is similarly
`employed to form an insulation film 8, such as a silicon
`nitride (SiN) film, a silicon oxide film. Then, insulation film
`20 8, the polycrystalline silicon and tunnel insulation film 3 are
`removed in the peripheral-circuitry region. Then, as in
`forming poly crystalline silicon (floating gate) 4, chemical
`vapor deposition is employed to deposit polycrystalline
`silicon serving as control gate 9.
`Then, as shown in FIG. 14, on a region with polycrys(cid:173)
`talline silicon that is desired as a gate electrode a patterned
`photoresist 14 is provided in a y direction (a direction
`vertical relative to the plane of the figure). With patterned
`photoresist 14 used as a mask, the region is anisotropically
`30 etched to expose a surface of tunnel insulation film 3.
`Then, patterned resist 14 is for example plasma-ashed and
`thus removed.
`As shown in FIG. 15, dopant ions are introduced in a
`direction indicated by an arrow 15 to form at an upper
`portion of p doped region 1a heavily n doped regions
`(source/drain regions) 2a and 2b higher in dopant concen(cid:173)
`tration than p doped region 1a. Then, as shown in FIG. 11,
`chemical vapor deposition or the like is employed to provide
`insulation layers 10 and 11 formed of silicon oxide film and
`serving as a passivation film to complete a flash memory.
`The semiconductor device manufacturing method as
`above has a disadvantage described below with reference to
`simplified drawings.
`As shown in FIG. 16, on a silicon substrate 1 a Si02 film
`2 is formed. On Si02 film 2 a polysilicon film 3 is deposited.
`On polysilicon film 3 a patterned photoresist 4 is provided
`by photolithography. With patterned resist 4 used as a mask,
`polysilicon film 3 is dry-etched and then successively Si02
`50 film 2 is etched with a hydrofluoric acid solution.
`In the hydroflouric acid solution process, however, when
`polysilicon film 3 is dry-etched an altered surface layer 5 of
`patterned photoresist 4 is removed, as shown in FIG. 17.
`Removed surface layer 5 of the resist adheres onto silicon
`55 substrate 1 and thus disadvantageously prevents the under(cid:173)
`lying Si02 film 2 from being etched. Furthermore, removed
`surface layer 5 of the resist disadvantageously flows into the
`hydrofluoric acid treatment bath and as a foreign matter
`contaminates the bath.
`Furthermore, such problem tends to occur particularly
`when polysilicon is etched with chloride type gas.
`Furthermore, such problem also tends to occur when with
`a polysilicon film having an insulation film such as Si02
`film, SiN film deposited thereon the Si02/SiN film is dry(cid:173)
`etched, the polysilicon film is dry-etched and the Si02 film
`is then wet-etched with hydrofluoric acid solution succes-
`sively.
`
`IPR2014-00108
`Exhibit MX027-1003, p. 14
`
`

`

`US 6,458,655 Bl
`
`10
`
`35
`
`3
`SUMMARY OF THE INVENTION
`The present invention has been made to solve such
`disadvantages as described above.
`The present invention contemplates an improved semi(cid:173)
`conductor manufacturing method capable of preventing
`removal of an altered surface layer of a patterned photore(cid:173)
`sist.
`The present invention also contemplates an improved
`flash memory manufacturing method preventing removal of
`an altered surface layer of a patterned photoresist.
`The present invention also contemplates an improved
`static random access memory manufacturing method pre(cid:173)
`venting removal of an altered surface layer of a patterned
`photoresist.
`In accordance with the present invention in one aspect a
`semiconductor device manufacturing method includes the
`steps of: initially forming on a semiconductor substrate an
`insulation film and a conductive layer successively by either
`deposition or deposition followed by patterning (step 1);
`forming a patterned resist on the conductive layer (step 2);
`with the patterned resist used as a mask, dry-etching the
`conductive layer (step 3); partially removing a surface layer
`of the patterned resist (step 4); and with the patterned resist
`used as a mask, etching the insulation film.
`In accordance with the present invention, partially remov(cid:173)
`ing a surface layer of the patterned resist allows removal of
`an altered surface of the patterned resist.
`In accordance with the present invention in a second
`aspect a semiconductor device manufacturing method pro(cid:173)
`vides step 4 using an 0 2 plasma etch to partially remove a
`surface layer of the patterned resist.
`In accordance with the present invention in a third aspect
`a semiconductor device manufacturing method includes
`using an 0 2 mixed gas to dry-etch the conductive layer in
`step 3 and thus providing step 4 in the sequence of dry-
`etching the conductive layer.
`In accordance with the present invention in a fourth aspect
`a semiconductor device manufacturing method includes the
`steps of: forming on a semiconductor substrate an insulation
`film and a conductive layer successively by either deposition
`or deposition followed by patterning (step 1); forming a
`patterned resist on the conductive layer (step 2); with the
`patterned resist used as a mask, dry-etching the conductive
`layer (step 3); joining together an altered surface layer of the
`patterned resist and a normal layer of the patterned resist
`underlying the surface thereof, and thus preventing the
`altered layer and the normal layer from being removed (step
`4); and with the patterned resist used as a mask, etching the
`insulation film (step 5).
`In accordance with the present invention, an altered
`surface layer of a patterned resist and a normal layer of the
`patterned resist underlying the surface thereof can be joined
`together and thus prevented from being removed.
`In accordance with the present invention in a fifth aspect
`a semiconductor device manufacturing method includes in 55
`step 4 the step of illuminating a surface of the patterned
`resist in a N2 ambient with a deep ultraviolet light and
`subsequently thermally processing the same.
`In accordance with the present invention in a sixth aspect
`a semiconductor device manufacturing method includes in
`step 4 the step of illuminating a surface of the patterned
`resist in a dry air with a deep ultraviolet light and subse(cid:173)
`quently thermally processing the patterned resist.
`In accordance with the present invention in a seventh
`aspect a semiconductor device manufacturing method pro(cid:173)
`vides step 4 by thermally processing the patterned resist in
`a dry air.
`
`4
`In accordance with the present invention in an eighth
`aspect a flash memory manufacturing method includes the
`steps of: forming on a surface of a semiconductor substrate
`an isolating oxide film isolating a memory cell region and a
`5 peripheral circuitry region from each other (step 1); forming
`a tunnel oxide film on a surface of the semiconductor
`substrate (step 2); forming a first polysilicon layer on the
`tunnel oxide film (step 3); patterning the tunnel oxide film
`and the first polysilicon layer as desired (step 4); forming an
`insulation film on the first polysilicon layer (step 5); forming
`on the insulation film a patterned resist having an end
`positioned on the isolating oxide film and covering only the
`memory cell region (step 6); with the patterned resist used
`as a mask, dry-etching and thus removing the insulation film
`and the first polysilicon layer that overlie the peripheral
`15 circuitry region (step 7); partially removing a surface of the
`patterned resist (step 8); with the patterned resist used as a
`mask, removing the tunnel oxide film overlying the periph(cid:173)
`eral circuitry region (step 9); removing the patterned resist
`(step 10); forming on the semiconductor substrate and on the
`20 peripheral circuitry region a gate oxide film for a peripheral
`transistor (step 11); forming a second polysilicon layer on
`the semiconductor substrate (step 12); forming on the sec(cid:173)
`ond polysilicon layer an oxide film used as an etching mask
`(step 13); forming a control gate in the memory cell region
`25 and forming a transistor gate for the peripheral circuitry
`(step 14); and patterning the insulation film and the first
`polysilicon layer and forming a floating gate (step 15).
`In accordance with the present invention, partially remov-
`30 ing a surface layer of a patterned resist allows removal of an
`altered surface layer of the patterned resist.
`In accordance with the present invention in a ninth aspect
`a flash memory includes a semiconductor substrate. On the
`semiconductor substrate a dummy gate region is provided.
`On the semiconductor substrate a memory cell region and a
`peripheral circuitry region are provided to sandwich the
`dummy gate region. The dummy gate region includes an
`isolating oxide film formed on the semiconductor substrate.
`On the isolating oxide film a first conductive layer is
`40 provided having an end closer to the peripheral circuitry
`region that recedes towards the memory cell region. On the
`first conductive layer an insulation layer is provided having
`an end closer to the peripheral circuitry region that recedes
`towards the memory cell region. On the isolating oxide film
`45 a second conductive layer is provided covering the first
`conductive layer and the insulation layer.
`In accordance with the present invention in a tenth aspect
`a semiconductor device manufacturing method in the first or
`fourth aspect uses a polysilicon film as the conductive layer
`50 and dry-etches the conductive layer with a chloride-type gas.
`In accordance with the present invention in an eleventh
`aspect, a flash memory manufacturing method in the eighth
`aspect at step 6 uses a chlorine gas to dry-etch the patterned
`resist.
`In accordance with the present invention in a twelfth
`aspect a semiconductor device manufacturing method
`include the steps of: initially forming on a semiconductor
`substrate an insulation film and a conductive layer succes(cid:173)
`sively (step 1); forming a second insulation film (step 2);
`60 forming a patterned resist on the second insulation film (step
`3); with the patterned resist used as a mask, dry-etching the
`second insulation film and the conductive layer (step 4);
`partially removing a surface layer of the patterned resist
`(step 5); and with the patterned resist used as a mask, etching
`65 the insulation film (step 6).
`In accordance with the present invention in a thirteenth
`aspect a semiconductor manufacturing method provides step
`
`IPR2014-00108
`Exhibit MX027-1003, p. 15
`
`

`

`US 6,458,655 Bl
`
`5
`5 using an 0 2 plasma etch to partially remove a surface of
`the patterned resist.
`In accordance with the present invention in a fourteenth
`aspect a semiconductor device manufacturing method
`includes step 4 using an 0 2 mixed gas to dry-etch the second 5
`insulation film and the conductive layer and thus provides
`step 5 in the sequence of dry-etching the conductive layer.
`In accordance with the present invention in a fifteenth
`aspect a semiconductor device manufacturing method
`includes the steps of: initially forming on a semiconductor
`substrate an insulation film and a conductive layer succes(cid:173)
`sively (step 1); forming a second insulation film (step 2);
`forming a patterned resist on the conductive layer (step 3);
`with the patterned resist used as a mask, dry-etching the
`conductive layer (step 4); joining together an altered surface
`layer of the patterned resist and a normal layer of the
`patterned resist underlying the surface layer thereof and thus
`preventing the altered surface layer and the normal layer
`from being removed (step 5); and with the patterned resist
`used as a mask, etching the insulation film (step 6).
`In accordance with the present invention in a sixteenth
`aspect a semiconductor device manufacturing method
`includes in step 5 the step of illuminating a surface of the
`patterned resist in a N2 ambient with a deep ultraviolet light
`and subsequently thermally processing the patterned resist.
`In accordance with the present invention in a seventeenth
`aspect a semiconductor device manufacturing method
`includes in step 5 the step of illuminating a surface of the
`patterned resist in dry air with a deep ultraviolet light and
`subsequently thermally processing the patterned resist.
`In accordance with the present invention in an eighteenth
`aspect a semiconductor manufacturing method provides step
`5 thermally processing the patterned resist in a dry air.
`In accordance with the present invention in a nineteenth 35
`aspect a flash memory manufacturing method includes the
`steps of: initially forming on a surface of a semiconductor
`substrate an isolating oxide film isolating a memory cell
`region and a peripheral circuitry region from each other
`(step 1); forming a tunnel oxide film on a surface of the 40
`semiconductor substrate (step 2); forming a first polysilicon
`layer on the tunnel oxide film (step 3); patterning the tunnel
`oxide film and the first polysilicon layer as desired (step 4);
`forming an insulation film on the first polysilicon layer (step
`5); forming on the insulation film a patterned resist having 45
`an end positioned on the isolating oxide film and covering
`only the memory cell region (step 6); with the patterned
`resist used as a mask, dry-etching and thus removing the
`insulation film and the first polysilicon layer that overlie the
`peripheral circuitry region (step 7); using 0 2 plasma to etch 50
`and thus partially remove a surface layer of the patterned
`resist (step 8); with the patterned resist used as a mask,
`removing the tunnel oxide film overlying the peripheral
`circuitry region (step 9); removing the patterned resist (step
`10); forming on the semiconductor substrate and on the 55
`peripheral circuitry region a gate oxide film for a peripheral
`transistor (step 11); forming a second polysilicon layer on
`the semiconductor substrate (step 12); forming on the sec(cid:173)
`ond polysilicon layer an oxide film used as an etching mask
`(step 13); forming a control gate. in the memory cell region 60
`and forming a transistor gate for the peripheral circuitry
`(step 14); and patterning the insulation film and the first
`polysilicon layer and forming a floating gate (step 15).
`In accordance with the present invention in a twentieth
`aspect a flash memory manufacturing method is character- 65
`ized in that in step 7 the insulation film and the first
`polysilicon layer are dry-etched with an 0 2 mixed gas and
`
`6
`that in step 8 the patterned resist's surface layer is partially
`removed in the dry-etching sequence.
`In accordance with the present invention in a twenty-first
`aspect a flash memory manufacturing method includes the
`steps of: initially forming on a surface of a semiconductor
`substrate an isolating oxide film isolating a memory cell
`region and a peripheral circuitry region from each other
`(step 1); forming a tunnel oxide film on a surface of the
`semiconductor substrate (step 2); forming a first polysilicon
`10 on the tunnel oxide film (step 3); patterning the tunnel oxide
`film and the first polysilicon layer, as desired (step 4);
`forming an insulation film on the first polysilicon layer (step
`5); forming on the isolation film a patterned resist having an
`end positioned on the isolating oxide film and covering only
`15 the memory cell region (step 6); with the patterned resist
`used as a mask, dry-etching and thus removing the insulation
`film and the first polysilicon layer that overlie on the
`peripheral circuitry region (step 7); joining together an
`altered surface layer of the patterned resist and a normal
`20 portion of the patterned resist underlying the surface layer
`thereof and thus preventing the altered surface layer and the
`underlying normal portion from being removed (step 8);
`with the patterned resist used as a mask, removing the tunnel
`oxide film overlying the peripheral circuitry region (step 9);
`25 removing the patterned resist (step 10); forming on the
`semiconductor substrate and on the peripheral circuitry
`region a gate oxide film for a peripheral transistor (step 11);
`forming a second polysilicon layer on the semiconductor
`substrate (step 12); forming on the second polysilicon layer
`30 an oxide film used as an etching mask (step 13); forming a
`control gate in the memory cell region and forming a
`transistor gate for the peripheral circuitry (step 14); and
`patterning the insulation film and the first polysilicon layer
`and forming a floating gate (step 15).
`In accordance with the present invention in a twenty(cid:173)
`second aspect a flash memory manufacturing method
`includes step 8 illuminating a surface of the patterned resist
`in a N2 ambient with a deep ultraviolet light and thermally
`processing the patterned resist.
`In accordance with the present invention in a twenty-third
`aspect a flash memory manufacturing method includes step
`8 illuminating a surface of the patterned resist in a dry air
`with a deep ultraviolet light and thermally processing the
`patterned resist.
`In accordance with the present invention in a twenty(cid:173)
`fourth aspect a flash memory manufacturing method
`includes step 8 thermally processing the patterned resist in
`a dry air.
`In accordance with the present invention in a twenty-fifth
`aspect an SRAM manufacturing method includes the steps
`of: initially forming an isolating oxide film on a surface of
`a semiconductor substrate (step 1); depositing a gate oxide
`film on the semiconductor substrate (step 2); depositing a
`first polysilicon layer on the gate oxide film (step 3); forming
`a patterned resist having an opening extending from an
`active region to the isolating oxide film (step 4); with the
`patterned resist used as a mask, dryetching and thus remov(cid:173)
`ing the first polysilicon layer (step 5); partially removing a
`surface layer of the patterned resist (step 6); again with the
`patterned resist used as a mask, removing the gate oxide film
`at a bottom of the patterned resist (step 7); removing the
`patterned resist (step 8); forming a second polysilicon layer
`(step 9); forming of resist a pattern providing a gate elec(cid:173)
`trode of an access transistor, a pattern providing a gate
`electrode of a driver transistor and a pattern providing a gate
`electrode of a transistor for peripheral circuitry (step 10);
`
`IPR2014-00108
`Exhibit MX027-1003, p. 16
`
`

`

`US 6,458,655 Bl
`
`8
`method according to a fifth embodiment of the present
`invention, as shown at first to third steps thereof, respec(cid:173)
`tively.
`FIG. 5 is a cross section of a semiconductor device
`5 manufactured by a flash memory manufacturing method
`according to a tenth embodiment of the present invention.
`FIGS. 6-10 are cross sections of a semiconductor device
`manufactured by a flash memory manufacturing method
`according to the tenth embodiment of the present invention,
`10 as shown at first to fifth steps thereof, respectively.
`FIG. 11 is a cross section of a conventional flash memo(cid:173)
`ry's memory cell.
`FIGS. 12-15 are cross sections of a semiconductor device
`manufactured by a conventional flash memory manufactur-
`15 ing method, as shown at first to fourth steps thereof, respec(cid:173)
`tively.
`FIGS. 16 and 17 are cross sections of a semiconductor
`device manufactured by a conventional semiconductor
`device manufacturing method, showing a disadvantage
`thereof, as shown at first and second steps thereof, respec(cid:173)
`tively.
`FIG. 18 is a cross section of a semiconductor device for
`illustrating a method according to a third embodiment of the
`present invention
`FIGS. 19-21 are cross sections of a semiconductor device
`manufactured by a method according to a seventh embodi(cid:173)
`ment of the present invention, as shown at first to third steps
`thereof, respectively.
`FIG. 22 is an equivalent circuit diagram of a high resis(cid:173)
`tance load type SRAM memory cell.
`FIGS. 23-25 are cross sections of a semiconductor device
`manufactured by a method according to an eleventh embodi(cid:173)
`ment of the present invention, as shown at first to third steps
`thereof, respectively.
`
`20
`
`7
`with the patterned resist used as a mask, dry-etching the first
`and second polysilicon layers (step 11); removing the pat(cid:173)
`terned resist (step 12); doping only an n region with an n
`dopant (step 13); and thermally processing a resultant prod(cid:173)
`uct (step 14).
`In accordance with the present invention in a twenty-sixth
`aspect an SRAM manufacturing method includes step 6
`using an 0 2 plasma etch and thus partially remove a surface
`of the patterned resist.
`In accordance with the present invention in a twenty(cid:173)
`seventh aspect an SRAM manufacturing method includes in
`step 5 using an 0 2 mixed gas to dry-etch the first polysilicon
`layer and in step 6 partially removing a surface layer of the
`patterned resist in the dry-etching sequence.
`In accordance with the present invention in a twenty(cid:173)
`eighth aspect an SRAM manufacturing method includes the
`steps of: initially forming an isolating oxide film on a surface
`of a semiconductor substrate (step 1); depositing a gate
`oxide film on the semiconductor substrate (step 2); depos-
`iting a first polysilicon layer on the gate oxide film (step 3);
`forming a patterned resist having an opening extending from
`an active region to the isolating oxide film (step 4); with the
`patterned resist used as a mask, dryetching and thus remov(cid:173)
`ing the first polysilicon layer (step 5); joining together an 25
`altered surface layer of the patterned resist and a normal
`portion of the patterned resist underlying the altered surface
`layer thereof and thus preventing the altered surface layer
`and the normal portion from being removed (step 6); again
`with the patterned resist used as a mask, removing the gate 30
`oxide film at a bottom of the pattern (step 7); removing the
`patterned resist (step 8); forming a second polysilicon layer
`(step 9); forming of resist a pattern providing a gate elec(cid:173)
`trode of an access transistor, a pattern providing a gate
`electrode of a driver transistor and a pattern providing a gate 35
`electrode of a transistor for peripheral circuitry (step 10);
`with the patterned resist used as a mask, dry-etching the first