IPR2014-00108
`U.S. Patent No. 7,151,027
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`
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`Attorney Docket No
`110900-0004-656
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`___________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`___________________________________
`
`MACRONIX INTERNATIONAL CO., LTD., MACRONIX ASIA LIMITED,
`MACRONIX (HONG KONG) CO., LTD. and MACRONIX AMERICA, INC.
`Petitioners
`
`v.
`
`SPANSION LLC
`Patent Owner
`
`___________________________________
`
`Case No. IPR2014-00108
`Patent Number 7,151,027
`
`Before KRISTEN L. DROESCH, JUSTIN T. ARBES, and
`RICHARD E. RICE, Administrative Patent Judges.
`
`
`PATENT OWNER’S PRELIMINARY RESPONSE
`UNDER 37 C.F.R. § 42.107
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`
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`

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`IPR2014-00108
`U.S. Patent No. 7,151,027
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`Attorney Docket No
`110900-0004-656
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`TABLE OF CONTENTS
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`B. 
`
`C. 
`
`Introduction .................................................................................................................... 1 
`I. 
`Summary of the ’027 Patent ......................................................................................... 4 
`II. 
`III.  Claim Construction ....................................................................................................... 7 
`A. 
`“interface between a memory array and a periphery” (Claims 1, 8) .......... 8 
`B. 
`“poly-2 layer” (Claims 1, 8) .............................................................................. 9 
`C. 
`“stacked gate etch” (Claims 3, 9) ................................................................... 10 
`D. 
`“second gate etch” (Claims 4, 10) ................................................................. 13 
`IV.  There is No Reasonable Likelihood Petitioner Would Prevail on Its Contention
`that Yuzuriha, Alone or in Any Proposed Combinations, Discloses the Recited
`“Etching” Limitations and “Same Height” Limitations of Claims 3, 7, and 8-14
`(Grounds 1-3) ............................................................................................................... 15 
`A. 
`Yuzuriha Fails to Disclose the Required “Etching” Limitations of Claims
`3 and 8-14 (Grounds 1-3) ............................................................................... 15 
`Yuzuriha Fails to Render Claims 7 and 14 Obvious in View of
`Nakagawa (Ground 3) ..................................................................................... 20 
`Yuzuriha Fails to Render Claims 11 and 12 Obvious in View of Shukuri,
`and Fails to Render Claims 13 and 14 Obvious in View of Nakagawa
`(Grounds 2-3) ................................................................................................... 23 
`There is No Reasonable Likelihood Petitioner Would Prevail on Its Contention
`that Shukuri, Alone or in Any Proposed Combinations, Discloses the Recited
`“Etching” Limitations and” Same Height” Limitations of Claims 3, 7, and 8-14
`(Grounds 4-5) ............................................................................................................... 24 
`A. 
`Shukuri Fails to Disclose the Required “Etching” Limitations of Claims
`3 and 8-13 (Grounds 4-5) ............................................................................... 24 
`Shukuri Fails to Render Claims 7 and 14 Obvious in View of Nakagawa
`(Ground 5) ........................................................................................................ 27 
`VI.  There is No Reasonable Likelihood Petitioner Would Prevail on Its Contention
`that Nakagawa, Alone or in Any Proposed Combinations, Discloses the
`“Interface” Limitations and “Same Height” Limitations of Claims 1-14
`(Grounds 6-7) ............................................................................................................... 28 
`A.  Nakagawa Fails to Disclose “Forming…At an Interface Between a
`Memory Array and a Periphery of Said Memory Device” (Ground 6) .. 29 
`
`V. 
`
`B. 
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`IPR2014-00108
`U.S. Patent No. 7,151,027
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`B. 
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`Attorney Docket No
`110900-0004-656
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`Nakagawa Fails to Disclose the “Same Height” Limitation of Claims 7
`and 14 (Ground 6) ........................................................................................... 31 
`Nakagawa Fails to Render Claims 5, 11, and 12 Obvious In View of
`Shukuri (Ground 7) ......................................................................................... 32 
`VII.  Conclusion .................................................................................................................... 33 
`
`
`
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`C. 
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`ii
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`IPR2014-00108
`U.S. Patent No. 7,151,027
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`Attorney Docket No
`110900-0004-656
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`TABLE OF AUTHORITIES
`
`
`CASES
`
`Page(s)
`
`In re Suitco Surface, Inc.,
`603 F.3d 1255 (Fed. Cir. 2010) .......................................................................................... 7
`
`Phillips v. AWH Corp.,
`415 F.3d 1303 (Fed. Cir. 2005) .......................................................................................... 7
`
`STATUTES
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`35 U.S.C. § 314 ................................................................................................................ 2, 4, 27
`
`OTHER AUTHORITIES
`
`37 C.F.R. § 42.100(b) ................................................................................................................ 7
`
`37 C.F.R. § 42.107 ..................................................................................................................... 1
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`37 C.F.R. § 42.107(c) ................................................................................................................. 8
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`37 C.F.R. § 42.108(c) ................................................................................................................. 2
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`77 Fed. Reg. 48680, 48694 (Aug. 14, 2012) ........................................................................... 2
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`
`
`
`
`
`
`iii
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`IPR2014-00108
`U.S. Patent No. 7,151,027
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`Attorney Docket No
`110900-0004-656
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`
`EX2001
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`
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`
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`EXHIBITS
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`Second Joint Submission Regarding Proposed Construction of
`Disputed Terms, In re Flash Memory Chips and Products Containing
`Same, Inv. No. 337-TA-893
`
`iv
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`

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`IPR2014-00108
`U.S. Patent No. 7,151,027
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`Attorney Docket No
`110900-0004-656
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`Pursuant to 37 C.F.R. § 42.107, Patent Owner Spansion LLC submits this
`
`Preliminary Response to the above-captioned Petition for Inter Partes Review of U.S.
`
`Patent No. 7,151,027 (“Pet.,” Paper 1).
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`I.
`
`Introduction
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`On its face, Petitioner’s 1 submission fails to provide the Board with basic
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`evidence required to institute an inter partes review. If the Board nonetheless institutes
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`trial on any of the challenged claims, Patent Owner will address in detail in its
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`§ 42.120 Response the numerous substantive errors and shortcomings that underlie all
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`of Petitioner’s asserted grounds and purported evidence. In this paper, however,
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`where Patent Owner is not permitted to submit expert testimony (Rule § 42.107(c)),
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`Patent Owner addresses only the meaning of certain of the challenged claims’
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`pertinent terms and the single issue made pertinent by Rule § 42.107: Petitioner’s
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`threshold failures—even judged solely from Petitioner’s papers—to demonstrate a
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`reasonable likelihood of success on the majority of its asserted invalidity challenges.
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`The challenged patent, U.S. Patent No. 7,151,027 (“the ’027 Patent”), relates to
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`methods for reducing the area of the interface between the memory array and
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`periphery in memory devices, which also increases manufacturing yield by reducing
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`the risk of potentially damaging stringer spacers during the fabrication process. See
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`1 Macronix International Co., Ltd., Macronix Asia Limited, Macronix (Hong Kong)
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`Co., Ltd., and Macronix America, Inc. are collectively referred to herein as “Petitioner.”
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`
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`1
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`IPR2014-00108
`U.S. Patent No. 7,151,027
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`MX027-1001 at 1:7-9; 1:66-2:12. The ’027 Patent has two independent claims and
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`Attorney Docket No
`110900-0004-656
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`twelve dependent claims. Independent Claims 1 and 8 are directed to methods of
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`fabricating a memory device including steps to fabricate a polysilicon structure at the
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`interface between a memory array and a periphery. Dependent Claims 2-7 and 9-14
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`add additional limitations to those methods such as certain etch steps, addition of a
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`dielectric layer, including, but not limited to an ONO layer, and the forming of
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`sidewall spacers on the polysilicon structure at the interface. MX027-1001 at 6:1-8:4.
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`To justify institution of an inter partes review, Petitioner’s papers must make a
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`prima facie showing that, as a factual and legal matter for each asserted ground, it has a
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`reasonable likelihood of proving at least one challenged claim unpatentable. See, e.g.,
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`37 C.F.R. § 42.108(c); 35 U.S.C. § 314; 77 Fed. Reg. 48680, 48694 (Aug. 14, 2012).
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`But it is apparent even from Petitioner’s own arguments and evidence that it cannot
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`meet that burden the majority of its asserted challenges.
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`As addressed in more detail below, Petitioner’s asserted “Yuzuriha” reference,
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`U.S. Patent No. 6,458,655, fails to disclose at least the “etching” limitations and “same
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`height” limitations recited in Claims 3, 7, and 8-14. Petitioner’s proposed
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`combinations with U.S. Patent No. 6,559,012 (“Shukuri”) for the alleged obviousness
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`of dependent Claims 11 and 12 in Ground 2, and U.S. Patent No. 6,359,304
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`(“Nakagawa”) for the alleged obviousness of dependent Claims 7, 13-14 in Ground 3,
`
`do not cure this deficiency. Therefore, Petitioner’s papers on their face fail to
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`
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`2
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`IPR2014-00108
`U.S. Patent No. 7,151,027
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`demonstrate a reasonable likelihood of success on its anticipation or obviousness
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`Attorney Docket No
`110900-0004-656
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`grounds as to Claims 3, 7, and 8-14 based on Yuriziha and no inter partes review should
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`be instituted for these claims on Grounds 1-3.
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`Likewise, Shukuri fails to disclose at least the “etching” limitations and “same
`
`height” limitations recited in Claims 3, 7 and 8-14. Petitioner’s proposed combination
`
`with Nakagawa for the alleged obviousness of dependent Claims 7 and 14 in Ground
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`5 does not cure this deficiency at least because Nakagawa also fails to disclose at least
`
`the “same height” limitation. Thus, Petitioner’s submission shows no reasonable
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`likelihood of success with respect to at least Claims 3, 7 and 8-14 on its Grounds 4
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`and 5, and no inter partes review should be instituted on those bases.
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`Finally, acknowledging that Nakagawa does not disclose, inter alia, the
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`“interface” limitation recited in each of independent Claims 1 and 8, Petitioner resorts
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`to obviousness and attempts to fill in this gap with conclusory assertions that are
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`contradicted by Nakagawa and Petitioner’s own testimony in this proceeding. This
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`failed attempt simply underscores that the inventive aspects of the challenged claims
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`were not known or obvious at the time of the claimed invention. And Petitioner’s
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`proposed combination with Shukuri for the alleged obviousness of dependent Claims
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`5, 11 and 12 in Ground 6 does not attempt to address this deficiency. Again,
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`Petitioner fails to show on the face of its papers a reasonable likelihood of success on
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`
`
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`3
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`

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`IPR2014-00108
`U.S. Patent No. 7,151,027
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`its obviousness Grounds 6-7, and, again, no inter partes review should be instituted on
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`Attorney Docket No
`110900-0004-656
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`this basis.
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`The very purpose of the § 314 threshold is to avoid the empty, wasteful
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`exercise Petitioner asks this Board to commence, and Petitioner should be denied trial
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`on these unsupported grounds because the Petition on its face fails to show a
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`reasonable likelihood of success.
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`II.
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`Summary of the ’027 Patent
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`As discussed in the ’027 Patent, “[o]ne important goal of the semiconductor
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`industry is to reduce the size of memory devices. In reducing the size of operational
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`components (e.g., a memory array) and periphery components, an important
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`consideration is the interface between the operational components and periphery
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`components.” MX027-1001 at 1:18-23. This arrangement is illustrated in Figure 2 of
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`the ’027 patent, where a memory device 200 includes the periphery components,
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`labeled 210, the memory array, labeled 220, and a portion of the interface, labeled 230.
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`MX027-1001 at FIG 2.
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`4
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`IPR2014-00108
`U.S. Patent No. 7,151,027
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`Attorney Docket No
`110900-0004-656
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`Memory devices contain millions of components made up of complex
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`structures fabricated by the repeated deposition of layers on a silicon substrate, or
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`wafer.
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` MX027-1001 at 1:13-18.
`
` Typical fabrication methods common
`
`in
`
`semiconductor fabrication prior to the invention of the ’027 Patent for forming
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`memory devices
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`typically form
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`the operational components and periphery
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`components separately. Id. at 1:25-26. In other words, when the periphery
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`components were formed, only the periphery was etched (i.e., the memory was
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`masked, or protected from being etched), and when the memory array was formed,
`5
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`IPR2014-00108
`U.S. Patent No. 7,151,027
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`only the memory array was etched (i.e., the periphery was masked, or protected from
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`Attorney Docket No
`110900-0004-656
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`being etched). For various reasons, by using these different processes, a number of
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`steps having different heights at the interface were created. Id. at 1:24-31. Figure 1 in
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`the ’027 Patent depicts what a step at the interface may look like using these prior art
`
`methods. Id. at FIG 1.
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`Figure 1 shows interface 100 and substrate 110 etched leaving structures 115
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`and 120. Notably, structure 120 is higher than structure 115—a difference that is
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`difficult to control because of the different processes being used. MX027-1001 at
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`
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`1:34-42.
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`6
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`

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`IPR2014-00108
`U.S. Patent No. 7,151,027
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`Attorney Docket No
`110900-0004-656
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`As the ’027 Patent further describes, a common occurrence during the
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`formation of sidewall spacers was the formation of potentially damaging stringer
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`spacers at these steps. Id. at 1:47-51. These stringer spacers 130 may be easily peeled
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`from the device and displaced to other locations on the device, resulting in yield loss
`
`of performance by the memory array. Id. at 1:45-53; FIG 1.
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`The successful invention described and claimed in the ’027 Patent provides a
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`solution to this problem by providing methods for forming a polysilicon structure at
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`the interface between the memory array and the periphery where steps with different
`
`heights may be formed. See id. at 2:57-3:2. In so doing, the methods of the ’027
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`Patent reduce the formation of stringer spacers and allow for a reduction in the
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`number of processing steps, cycle time, cost and yield loss. See id.
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`III. Claim Construction
`Petitioner concedes, as it must, that for purposes of inter partes review “[a] claim
`
`in an unexpired patent shall be given its broadest reasonable construction in light of
`
`the specification of the patent in which it appears.”2 37 C.F.R. § 42.100(b); see (Pet. 4).
`
`While claim terms “are generally given their ordinary and customary meaning,” which
`
`is “the meaning that the term would have to a person of ordinary skill in the art in
`
`question at the time of the invention,” see, e.g., Phillips v. AWH Corp., 415 F.3d 1303,
`
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`2 Petitioner further acknowledges that a different standard is applicable to other
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`proceedings. (Pet. 4).
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`7
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`IPR2014-00108
`U.S. Patent No. 7,151,027
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`1312-13 (Fed. Cir. 2005); (Pet. 4), the construction must also be consistent with the
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`Attorney Docket No
`110900-0004-656
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`specification, and the claim language should be read in light of the specification as it
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`would be interpreted by one of ordinary skill in the art. See, e.g., In re Suitco Surface, Inc.,
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`603 F.3d 1255, 1260 (Fed. Cir. 2010). While reserving further discussion of claim
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`construction as may be appropriate for its § 42.120 Patent Owner Response3 if any
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`trial is instituted, Patent Owner notes here as a preliminary matter some of
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`Petitioner’s more egregious violations of these basic principles of claim construction.
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`“interface between a memory array and a periphery” (Claims 1, 8)
`
`A.
`Independent claim 1 (and its dependent claims 2-7) and claim 8 (and its
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`dependent claims 9-14) recite, inter alia, “forming a…layer above a substrate at an
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`interface between a memory array and a periphery of said memory device.”4 Purporting to
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`“further clarify” this element, Petitioner improperly attempts instead to re-write this
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`claim limitation and eliminate the term “an interface” by replacing it with “an area.”
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`See (Pet. 4-5) (proposing to construe this limitation as “an area between an array of
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`memory cells and a periphery”). But Petitioner cannot eliminate a word from the
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`claims simply because it does not like what it means. Indeed, the only support in the
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`specification Petitioner cites to actually refers to “interface area” and not simply
`
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`3 Again, unlike this preliminary response, Patent Owner’s § 42.120 response may
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`present supporting expert testimony. Cf., e.g., 37 C.F.R. §42.107(c).
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`4 Unless noted, all emphases are added.
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`8
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`

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`IPR2014-00108
`U.S. Patent No. 7,151,027
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`“area.” (Pet. 5) (citing MX027-1001 at FIG 2; 3:15-16). Petitioner’s own expert—
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`Attorney Docket No
`110900-0004-656
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`who does not actually provide his own analysis of this term, but instead concedes he was
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`“provided” with the constructions from “[a]ttorney” which he “applied when
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`rendering [his] opinions” (MX027-1002 at ¶ 38 5 )—refers to “interface area”
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`throughout his opinions. See, e.g., id. at ¶ 13 (“More particularly, the ’027 Patent is
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`intended to reduce the interface area of a memory device...”); at ¶ 20 (“[T]he interface
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`structure remains in the interface area between the memory core and periphery.”).
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`Petitioner’s attempt to read out “interface” altogether from the claim limitation is
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`entirely unsupported and erroneous, and should be rejected.
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`“poly-2 layer” (Claims 1, 8)
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`B.
`The term “poly-2” appears in each of independent claims 1 and 8 of the ’027
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`Patent and, consistent with the specification, should be construed to mean “a
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`polysilicon layer deposited later in time than a first polysilicon layer.” In the co-
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`5 Patent Owner’s citations to MX027-1002 are to Petitioner’s “Corrected Declaration
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`of Dhaval J. Brahmbhatt,” filed on February 19, 2014, pursuant to Petitioner’s
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`Motion to Expunge and Replace Declaration of Dhaval J. Brahmbhatt (Exhibit 1002)
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`(Paper 10). To the extent Petitioner’s Motion is denied, references to paragraphs 48
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`and higher in Exhibit MX027-1002 should be reduced by one in order to match the
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`originally filed version of Exhibit MX027-1002.
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`9
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`IPR2014-00108
`U.S. Patent No. 7,151,027
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`pending ITC Proceeding6 involving the same patent and parties, both parties have
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`Attorney Docket No
`110900-0004-656
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`agreed to this construction, which is supported by the specification of the ’027 Patent.
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`See EX2001 at 13; see also MX027-1001 at 5:11-20 (“At step 410, a first polysilicon
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`layer (e.g., poly-1) is formed… At step 430, a second polysilicon layer (e.g., poly-2) is
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`formed…”).
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`“stacked gate etch” (Claims 3, 9)
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`C.
`The term “stacked gate etch” appears in each of claims 3 and 9 of the ’027
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`Patent and, consistent with the specification, should be construed to mean “a type of
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`process that etches poly-1 and poly-2 layers, used to form individual transistor
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`structures from the polysilicon layers.” The ’027 specification states, for example, that
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`a “stacked gate etch” is a process that etches poly-1 and poly-2 layers: “At step 440,
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`the poly-1 layer and the poly-2 layer are etched proximate to the memory array. In
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`one embodiment, the etching is accomplished by performing a stacked gate etch.”
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`MX027-1001 at 5:22-25. Elsewhere, the ’027 specification states, that “a known
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`process (such as a stacked gate etch) is used to etch a portion of poly-l 310a,
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`dielectric material 315, and poly-2 320.” MX027-1001 at 4:27-30. The specification
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`further describes that “[t]his etch is used to form individual transistors of from [sic]
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`the polysilicon layers.” Id. at 4:30-31.
`
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`6 In re Flash Memory Chips and Products Containing Same, Inv. No. 337-TA-893, filed
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`August 1, 2013, before the U.S. International Trade Commission (“ITC Proceeding”).
`
`
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`10
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`IPR2014-00108
`U.S. Patent No. 7,151,027
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`Attorney Docket No
`110900-0004-656
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`Petitioner’s proposed construction (“etching step that etches at least a portion
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`of a stacked gate”) (Pet. 5) on the other hand, is unsupported by the specification.
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`Nothing in the specification describes “etching a portion of a stacked gate.” Indeed,
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`the resulting claim limitation would be nonsensical to a person of ordinary skill in the
`
`art in light of the specification. As described above, a person of ordinary skill in the
`
`art would understand that the invention as described and claimed in the ’027 Patent is
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`one in which the stacked gate etch would etch at least poly-2 and poly-1 layers thereby
`
`enabling the formation of a stacked gate (i.e., the etch would be “used to form
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`individual transistor structures from the polysilicon layers”). Petitioner’s construction,
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`on the other hand, describes a process etch step that etches (i.e., removes) a portion of
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`a stacked gate (i.e., an existing stacked gate is etched). Not only is this not described
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`in the specification, but it would not make sense to remove portions of a stacked gate.
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`Petitioner’s construction is refuted by Petitioner’s own description of the ’027 Patent
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`(using figures highly annotated by Petitioner7), which acknowledges that the “stacked
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`gate etch” is used to “etch a portion of poly-1 (310a), shown in green, dielectric (315),
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`shown in red, and poly-2 (320), shown in yellow, proximate to the memory array” and
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`7 Unless otherwise noted, all annotated figures in color hereinafter have been
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`reproduced from the Petition and all coloring and colored elements (e.g., red text,
`
`arrows, etc.) in figures were added by Petitioner.
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`11
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`IPR2014-00108
`U.S. Patent No. 7,151,027
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`that “[t]his etch forms ‘individual transistors from the polysilicon layers.’” See (Pet. 8)
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`Attorney Docket No
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`and Petitioner’s annotated figures 3D & 3E:
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`
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`Notably, in the ITC Proceeding, the ITC staff rejected Petitioner’s construction
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`and concluded instead that Patent Owner correctly construed “stacked gate etch” to
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`mean “a type of process that etches poly-1 and poly-2 layers, used to form individual
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`transistor structures from the polysilicon layers.” See EX2001 at 7. Petitioner’s
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`position is unsupported and erroneous, and Patent Owner’s proposed construction—
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`confirmed by the clear language of the specification—should be adopted.
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`12
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`IPR2014-00108
`U.S. Patent No. 7,151,027
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`D.
`The term “second gate etch” appears in each of claims 4 and 10 of the ’027
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`Attorney Docket No
`110900-0004-656
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`“second gate etch” (Claims 4, 10)
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`Patent and, consistent with the specification, should be construed to mean “a process
`
`that etches poly-2 layer.” The ‘027 specification states, for example, that “a known
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`process (such as a second gate etch) is used to etch a portion of poly-2 320.”
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`MX027-1001 at 4:39-41. The specification also describes, with respect to Figure 4,
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`that “[a]t step 450, the poly-2 layer is etched proximate to the periphery, such that
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`an interface structure including a portion of the poly-1 layer and a portion of the poly-
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`2 layer remains at the interface. In one embodiment, the etching is accomplished by
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`performing a second gate etch.” Id. at 5:24-29.
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`Again, similar to Petitioner’s proposed construction of the term “stacked gate
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`etch,” Petitioner’s proposed construction for “second gate etch” is unsupported by
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`the specification. Indeed, Petitioner’s construction of “second gate etch” to mean “an
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`etching step that etches at least a portion of a second gate” (Pet. 5) would likewise
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`describe a process etch step that etches a portion of a second gate (i.e., an existing
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`second gate is etched). This, again, is not described in the specification, nor would it
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`make sense to etch a portion of a second gate. Petitioner’s construction is further
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`refuted by Petitioner’s own description of the ’027 Patent, which acknowledges that
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`the “second gate etch” is “used to etch a portion of the poly-2 (320), shown in yellow,
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`13
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`IPR2014-00108
`U.S. Patent No. 7,151,027
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`proximate to the periphery, thus forming an ‘interface structure’ (360).” See (Pet. 9)
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`Attorney Docket No
`110900-0004-656
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`and Petitioner’s annotated Figures 3E & 3F:
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`
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`The ITC staff in the ITC Proceeding similarly rejected Petitioner’s construction
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`and concluded instead that Patent Owner correctly construed “second gate etch” to
`
`mean “a process that etches poly-2 layer.” See EX2001 at 7. Petitioner’s position is
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`unsupported and erroneous, and Patent Owner’s proposed construction—confirmed
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`by the clear language of the specification—should be adopted.
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`14
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`IPR2014-00108
`U.S. Patent No. 7,151,027
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`IV. There
`is No Reasonable Likelihood Petitioner Would Prevail
`on Its Contention
`that Yuzuriha, Alone or
`in Any Proposed
`Combinations, Discloses the Recited “Etching” Limitations and “Same
`Height” Limitations of Claims 3, 7, and 8-14 (Grounds 1-3)
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`Attorney Docket No
`110900-0004-656
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`Petitioner advances Yuzuriha as the base reference in each of its asserted
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`grounds 1-3. As discussed below, Yuzuriha fails to disclose at least the “etching”
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`limitations and “same height” limitations of Claims 3, 7, and 8-14—a failure that is
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`apparent even on the limited record available at this preliminary stage, and is fatal to
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`every one of Petitioner’s arguments.
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`A.
`
`Yuzuriha Fails to Disclose the Required “Etching” Limitations of
`Claims 3 and 8-14 (Grounds 1-3)
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`Independent claim 8 recites, inter alia, “etching said poly-1 layer and said poly-2
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`layer proximate to said memory array.” The plain language of the claim, therefore,
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`requires that both the “poly-1 layer and [] poly-2 layer” are etched in one step.
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`Similarly, Claim 3 (which depends from Claim 1) recites “etching said poly-2 layer
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`proximate to said memory array is accomplished by performing a stacked gate etch.”
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`As detailed above in Section III(C), a “stacked gate etch” is properly defined as “a
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`type of process that etches poly-1 and poly-2 layers, used to form individual transistor
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`structures from the polysilicon layers”—in other words, like Claim 8, Claims 3 and 9
`
`require that both the poly-18 and poly-2 layer be etched in one step.9
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`8 As discussed above in Section III(B), and as Petitioner agreed in the ITC Proceeding,
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`the recitation of poly-2 in claim 3 confirms that both poly-2 and poly-1 are present, as
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`15
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`IPR2014-00108
`U.S. Patent No. 7,151,027
`
`
`Attorney Docket No
`110900-0004-656
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`As even Petitioner acknowledges, this process, “such as a ‘stacked gate etch’
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`can be used to etch a portion of poly-1 (310a), shown in green, dielectric (315), shown
`
`in red, and poly-2 (320), shown in yellow, proximate to the memory array.” (Pet. 8)
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`and Petitioner’s annotated Figures 3D & 3E:
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`
`
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`“poly-2” is properly construed as “a polysilicon layer deposited later in time than a
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`first polysilicon layer.”
`
`9 As discussed above in Section III(C), Petitioner’s attempt to advance the
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`construction, “etching step that etches at least a portion of a stacked gate,” is wholly
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`unsupported. Petitioner’s assertion of this convoluted definition is also a tacit
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`acknowledgement that, without it, Petitioner’s prior art fails to disclose the elements
`
`of Claims 3 and 9.
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`16
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`IPR2014-00108
`U.S. Patent No. 7,151,027
`
`
`Attorney Docket No
`110900-0004-656
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`
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`
`
`Even assuming, arguendo, 10 that Yuzuriha otherwise discloses the claimed
`
`etching elements, Yuzuriha fails to disclose a process that etches the poly-1 layer and
`
`poly-2 layer in one step as required by Claims 3 and 8-9. According to the Petitioner
`
`(which has added numerous annotations to the figures from Yuzuriha shown below),
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`Yuzuriha discloses a step where poly-2 is etched and subsequently “another etching
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`step is performed to etch the poly-1 layer (10) (shown in green) proximate to the
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`memory array.” (Pet. 11-12) (citing MX027-1003 at 12:28-30; 12:56-59) & Petitioner’s
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`annotated Figures 8-10 from Yuzuriha:
`
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`10 As noted supra, Patent Owner will, if any trial is instituted, provide a full response
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`to Petitioner’s erroneous arguments and purported evidence in its § 42.120 Response.
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`17
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`IPR2014-00108
`U.S. Patent No. 7,151,027
`
`
`Attorney Docket No
`110900-0004-656
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`18
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`IPR2014-00108
`U.S. Patent No. 7,151,027
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`Attorney Docket No
`110900-0004-656
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`
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`See also MX027-1003 at 4:1-27; FIG. 5. As can be seen in Petitioner’s heavily
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`annotated Figures 8-10, the process that etches the alleged poly-2 layer (colored in
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`yellow by Petitioner) does not etch the alleged p