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`PNY Technologies, Inc.
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`EXHIBIT 1004
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`PNY Exhibit 1004
`Inter Partes Review of
`US Patent No. 7,518,879
`
`

`

`(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2006/0002096 A1
`
` Wang et al. (43) Pub. Date: Jan. 5, 2006
`
`
`US 20060002096A1
`
`(54) SYSTEM AND METHOD FOR PROVIDING A
`FLASH MEMORY ASSEMBLY
`
`(52) US. Cl.
`
`........................ 361/752; 361/759; 439/761;
`439/689; 439/718
`
`(76)
`
`Inventors: Kuang-Yu Wang, Saratoga, CA (US);
`Charles C. Lee, Sunnyvale, CA (US);
`Horng-Yee Chou, Palo Alto, CA (US)
`
`(57)
`
`ABSTRACT
`
`correspondence Address:
`SAWYER LAW GROUP LLP
`P'O' BOX 51418
`P310 Alto, CA 94303 (US)
`.
`(21) Appl. No"
`(22)
`Filed:
`
`10/882’539
`Jun. 30, 2004
`
`Publication Classification
`
`(51)
`
`Int. Cl.
`H05K 5/03
`H01R 13/502
`
`(2006.01)
`(2006.01)
`
`The present invention relates to a method and system for
`providing a flash memory assembly. The flash memory
`assembly includes a connector and a printed circuit board
`(PCB) coupled to the connector. The center of the PCB is
`positioned substantially at the center of the connector. An
`electronic component is coupled to one side of the PCB. In
`another aspect of the present invention, a second electronic
`component is coupled to a second side of the PCB. In
`another aspect of the present invention, the electronic com-
`ponents and the PCB are protected by covers joined using
`interference fitting or ultrasonic joining. In another aspect of
`the present invention, a cap protects the connector. The cap
`can be removably coupled to the connector.
`
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`PNY EXHIBIT 1004
`
`

`

`Patent Application Publication
`
`Jan. 5, 2006 Sheet 1 0f 18
`
`US 2006/0002096 A1
`
`
`
`84
`
`82
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`80
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`

`

`Patent Application Publication
`
`Jan. 5, 2006 Sheet 2 0f 18
`
`US 2006/0002096 A1
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`CBW (31 bytes)
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`

`

`Patent Application Publication
`
`Jan. 5, 2006 Sheet 3 0f 18
`
`US 2006/0002096 A1
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`Patent Application Publication
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`Jan. 5, 2006 Sheet 4 0f 18
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`US 2006/0002096 A1
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`Patent Application Publication
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`Jan. 5, 2006 Sheet 5 0f 18
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`Patent Application Publication
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`Jan. 5, 2006 Sheet 8 0f 18
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`Patent Application Publication
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`Patent Application Publication
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`Jan. 5, 2006 Sheet 10 0f 18
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`

`US 2006/0002096 A1
`
`Jan. 5, 2006
`
`SYSTEM AND METHOD FOR PROVIDING A
`FLASH MEMORY ASSEMBLY
`
`capable of being easily adapted to eXisting technology. The
`present invention addresses such a need.
`
`RELATED CO-PENDING PATENT
`APPLICATIONS
`
`[0001] The present invention is related to a co-pending
`US. application Ser. No. 10/789,333, filed on Mar. 10, 2004,
`and entitled “System and Method for Controlling Flash
`Memory.”
`
`FIELD OF THE INVENTION
`
`[0002] The present invention relates to memory systems,
`and more particularly to a system and method for providing
`a flash memory assembly.
`
`BACKGROUND OF THE INVENTION
`
`flash memory technology becomes more
`[0003] As
`advanced, flash memory is replacing traditional magnetic
`hard disks as storage media for mobile systems. Flash
`memory has significant advantages over magnetic hard
`disks, such as having high-gravity resistance and low power
`dissipation. Because of the smaller physical sizes of flash
`memory, they are also more conducive to mobile systems.
`Accordingly,
`the flash memory trend has been growing
`because of its compatibility with mobile systems and the
`low-power feature.
`
`[0004] New generation personal computer (PC) card tech-
`nologies have been developed that combine flash memory
`with architecture that is compatible with the Universal Serial
`Bus (USB) standard. This has further fueled the flash
`memory trend because the USB standard is easy to imple-
`ment and is popular with PC users. In addition to replacing
`hard drives, flash memory is also replacing floppy disks
`because flash memory provides higher storage capacity and
`faster access speeds than floppy disks.
`
`[0005] While flash memory is physically small and con-
`venient to carry around, the trade off is that it has limited
`storage capacity. It has a significantly higher storage capac-
`ity than floppy disks but a smaller storage capacity than hard
`disks. Nonetheless, the key features of flash memory are low
`power and mobility.
`
`[0006] Flash memory is typically implemented in an
`assembly, which includes a flash memory device mounted
`onto a printed circuit board and coupled to a USB connector.
`The USB connector plugs into a host receptacle. Such a
`general configuration is well known. Because of its smaller
`size, flash memory can be conveniently carried in briefcases,
`backpacks, purses, pockets, etc.
`
`[0007] A potential problem with flash memory being so
`mobile is that
`it
`is susceptible to breakage when being
`transported. A conventional solution is to protect the flash
`memory with a cover or housing. The housing must be
`sufficiently robust. However, since an advantage of flash
`memory is mobility, it is important that it remain light and
`compact.
`
`[0008] Accordingly, what is needed is an improved system
`and method for implementing flash memory. The system and
`method should be able to comply with the USB standard,
`should sufficiently protect a flash memory device when
`being transported, and should be simple, cost effective and
`
`SUMMARY OF THE INVENTION
`
`[0009] A flash memory assembly is disclosed. The flash
`memory assembly comprises a connector and a printed
`circuit board (PCB) coupled to the connector. The center of
`the PCB is positioned substantially at
`the center of the
`connector. An electronic component is coupled to one side
`of the PCB. In another aspect of the present invention, a
`second electronic component is coupled to a second side of
`the PCB. In another aspect of the present invention, the
`electronic components and the PCB are protected by covers
`joined using interference fitting or ultrasonic joining. In
`another aspect of the present invention, a cap protects the
`connector. The cap can be removably coupled to the con-
`nector.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`[0010] FIG. 1 is a block diagram of a conventional flash
`memory system coupled with a host system.
`
`[0011] FIG. 2 is a block diagram of a flash memory
`system, which can be used to implement the flash memory
`system of FIG. 1.
`
`[0012] FIG. 3A is a block diagram of a flash memory
`system including a flash memory controller and a flash
`memory in accordance with the present invention.
`
`[0013] FIG. 3B is a block diagram showing in more detail
`the write look-up table, the read look-up table, the physical
`usage table, and the recycling first-in-first-out unit of FIG.
`3A in accordance with the present invention.
`
`[0014] FIGS. 4A and 4B are side-view and exploded
`perspective-view diagrams of a conventional flash memory
`assembly, which can be used to implement the flash memory
`controller of FIG. 2.
`
`[0015] FIG. 4C is a blow-up perspective-view diagram of
`the USB connector of FIGS. 4A-4B.
`
`[0016] FIG. 5 is a side-view diagram of a flash memory
`assembly in accordance with another embodiment of the
`present invention.
`
`[0017] FIG. 6 is a side-view diagram of a balanced flash
`memory assembly in accordance with the present invention.
`
`[0018] FIG. 7 is side-view diagram of an unbalanced flash
`memory assembly.
`
`[0019] FIG. 8 is a side-view diagram showing a balanced
`flash memory assembly in accordance with another embodi-
`ment the present invention.
`
`[0020] FIG. 9 is a top-view diagram of the flash memory
`assembly of FIG. 5A in accordance the present invention.
`
`[0021] FIG. 10 is a partial top-view diagram illustrating
`an alignment notch, which can be used in lieu of an
`alignment hole in accordance with another embodiment of
`the present invention.
`
`[0022] FIG. 11 is a front-view diagram of a balanced flash
`memory assembly in accordance with the present invention.
`
`[0023] FIG. 12 is a partial front-view diagram a flash
`memory assembly illustrating an interface between a top
`
`

`

`US 2006/0002096 A1
`
`Jan. 5, 2006
`
`cover and a bottom cover in accordance with another
`
`embodiment of the present invention.
`
`[0024] FIG. 13 is a partial front-view diagram a flash
`memory assembly illustrating an interface between a top
`cover and a bottom cover in accordance with another
`
`embodiment of the present invention.
`
`[0025] FIG. 14 is a partial front-view diagram of a flash
`memory assembly using a snap-together mechanism to join
`a top cover and a bottom cover in accordance with the
`present invention.
`
`[0026] FIG. 15 is a partial front-view diagram of a flash
`memory assembly using a snap-together mechanism to join
`a top cover and a bottom cover in accordance with another
`embodiment of the present invention.
`
`[0027] FIG. 16 is a partial front-view diagram of a flash
`memory assembly using ultrasonic joining to join a top
`cover and a bottom cover in accordance with the present
`invention.
`
`[0028] FIG. 17 is a partial front-view diagram of a flash
`memory assembly using ultrasonic joining to join a top
`cover and a bottom cover in accordance with another
`
`embodiment of the present invention.
`
`[0029] FIG. 18 is a side-view diagram of a flash memory
`assembly including a cap that protects a USB connector in
`accordance with the present invention.
`
`[0030] FIG. 19 is a side-view diagram of a flash memory
`assembly including a cap that protects a USB connector in
`accordance with another embodiment of the present inven-
`tion.
`
`[0031] FIG. 20A is a side-view diagram of a flash memory
`assembly including a cap that protects a USB connector in
`accordance with another embodiment of the present inven-
`tion.
`
`[0032] FIG. 20B is a perspective-view diagram of the
`USB connector of FIG. 30A in accordance with the present
`invention.
`
`[0033] FIG. 21 is a side-view diagram of a flash memory
`assembly including a cap that protects a USB connector in
`accordance with another embodiment of the present inven-
`tion.
`
`[0034] FIG. 22 is a partial side-view diagram of a flash
`memory assembly including a cap that protects a USB
`connector in accordance with another embodiment of the
`
`present invention.
`
`[0035] FIGS. 23A-C are side-view diagrams of a flash
`memory assembly including a cap that protects a USB
`connector in accordance with another embodiment of the
`
`present invention.
`
`[0036] FIGS. 24A-C are side-view diagrams of a flash
`memory assembly including a cap that protects a USB
`connector in accordance with another embodiment of the
`
`present invention.
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`[0037] The present invention relates to memory systems,
`and more particularly to a system and method for providing
`
`a flash memory assembly. The following description is
`presented to enable one of ordinary skill in the art to make
`and use the invention and is provided in the context of a
`patent application and its requirements. Various modifica-
`tions to the preferred embodiment and the generic principles
`and features described herein will be readily apparent to
`those skilled in the art. Thus, the present invention is not
`intended to be limited to the embodiment shown but is to be
`
`accorded the widest scope consistent with the principles and
`features described herein.
`
`[0038] A system and method in accordance with the
`present invention for providing a flash memory assembly are
`disclosed. The flash memory assembly is configured to
`accommodate multiple flash memory components on both
`sides of a printed circuit board, while maintaining a thin and
`compact size. Also,
`the flash memory assembly includes
`features that increase the durability of the flash memory
`assembly when being handled or transported. To more
`particularly describe the features of the present invention,
`refer now to the following description in conjunction with
`the accompanying figures.
`
`[0039] Although the present invention disclosed herein is
`described in the context of assemblies for USB connectors
`
`and flash memory components, the present invention may
`apply to assemblies for other types of connectors and other
`types of integrated circuit devices and still remain within the
`spirit and scope of the present invention.
`
`[0040] FIG. 1 is a block diagram of a conventional flash
`memory system 50 coupled with a host system 52. The flash
`memory system 50 includes a flash memory controller 60
`and a flash memory 62. In operation, the host system 52
`sends write and read requests to the flash memory controller
`60. Data is written to and read from the flash memory 62.
`The host system 52 provides resources to process write and
`read transactions, and erase operations via the flash memory
`controller 60.
`
`[0041] FIG. 2 is a block diagram of a flash memory
`system 70, which can be used to implement
`the flash
`memory system 50 of FIG. 1. The flash memory system 70
`includes a flash memory controller 72, a flash memory array
`74, read-only memory (ROM) firmware 76, random-access
`memory (RAM) 78, a central processing unit (CPU) 80, a
`communication protocol controller 82, and a connector 84
`for connecting to a host system.
`
`Flash Memory System
`
`[0042] FIG. 3A is a block diagram of a flash memory
`system 100 in accordance with the present invention. Addi-
`tional embodiments of the flash memory system 100 is
`described in a co-pending US. application Ser. No. 10/789,
`333, filed on Mar. 10, 2004, and entitled “System and
`Method for Controlling Flash Memory,” and is herein incor-
`porated by reference.
`
`[0043] The flash memory system 100 is adapted to couple
`to a host system 52. In this specific embodiment, the host
`system 52 is a USB host system. The host system 52 can be
`any personal computer or any other type of computer
`system. The operating system of the host system 52 can be
`Windows or MacOS but is not limited to these operating
`systems. In this specific embodiment,
`the flash memory
`system 100 complies with the USB mass-storage class
`
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`standard. The USB specification can be revision 1.1 or 2.0
`and above. The flash memory system 100 can be used as a
`mass storage device. The advantage of being used as a mass
`storage device is that it is a low-power device, it is easy to
`carry, and it has storage capacity larger than a traditional
`floppy disk.
`
`[0044] The flash memory system 100 includes a USB
`interface to the host system 52, where the USB interface
`comprises a device transceiver 120 and a serial interface
`engine (SIE) 122. The transceiver 120 converts analog
`signals to digital streams and includes a phase lock loop
`(PLL) circuit for generating a precision clock for latching
`serially received data. For USB 2.0, the PLL functionality
`can be sensitive and thus useful due to its operating at 480
`MHZ. The SIE 122 provides serial and parallel data conver-
`sion, packet decoding/generation, cyclic redundancy code
`(CRC) generation/checking, non-return-to-zero (NRZI)
`encoding/decoding, and bit stuffing. A USB serial standard
`is implemented in this block.
`
`[0045] A bulk-only transport (BOT) unit 130 receives
`command block wrappers (CBW)
`(typically 31 bytes),
`which includes command decoding/direction. The CBW is
`also the source for a sector transfer length register 132 and
`a logical block address (LBA) register 134.
`
`[0046] A sector first-in-first-out (FIFO) 140 provides data
`buffering. During a write operation, a FIFO-not-empty inter-
`rupt signal 142 triggers a microprocessor interrupt routine at
`an interrupt handler 148 of a processor 150. The interrupt
`routine informs the host system 52 that data has been
`successfully received. In the mean time, the processor 150
`begins the writing process. When the microprocessor 150
`knows that sector data has been correctly received,
`the
`microprocessor 150 responds back to the host 52 that the
`write is complete. In the mean time, the firmware executes
`the write process.
`
`[0047] The processor 150 executes firmware stored in a
`read only memory (ROM) 152, responds to requests from
`the host system 52, and accesses the flash memory 112. In
`a specific embodiment,
`the processor 150 utilizes SCSI
`protocols to interface with the flash memory 112. While the
`specific type of processor will depend on the specific appli-
`cation, in a specific embodiment, the processor 150 is an
`8-bit or a 16-bit processor.
`
`[0048] Awrite look-up table (LUT) 170, a read LUT 172,
`and a physical usage table (PUT) 180 provide an index
`showing the mapping of the flash memory device 112. The
`write and read LUTs 170 and 172 facilitate write and read
`
`transactions, respectively, between the host system 52 and
`the flash memory device 112. The write and read LUTs 170
`and 172 translate logical block addresses (LBAs) provided
`by the host system 52 to physical block addresses (PBAs) of
`the flash memory device 112. The PUT 180 performs
`physical sector mapping and provides a bitmap indicating
`programmed sectors, i.e., sectors to which data has already
`been written.
`
`[0049] A recycling FIFO 190 recycles blocks of obsolete
`sectors so that they can be reprogrammed, i.e., written to
`with new data. The recycling FIFO 190 is used with one
`write pointer 192 and two read pointers 194 and 196
`assigned for block-valid-sector copy and erase operations.
`The recycling operations are executed in the background,
`
`immediately after, and independently from write transac-
`tions to not interfere with the servicing of write transactions
`by the flash memory system 100.
`
`[0050] For optimal ASIC implementation, the write and
`read LUTs 170 and 172, the PUT 180, and the recycling
`FIFO 190 are implemented with volatile static random
`access memory (SRAM). The flash memory device 112 can
`be implemented using one or more devices, each having one
`or more flash arrays.
`
`[0051] FIG. 3B is a block diagram showing in more detail
`the write look-up table 170, the read look-up table 172, the
`physical usage table 180, the recycling first-in-first-out unit
`190, and the write and read pointers 192, 194, and 196 of
`FIG. 3A in accordance with the present invention.
`
`[0052] The write LUT 170 provides an index for the flash
`memory during write transactions and translates logical
`block addresses (LBAs) provided by the host system to
`PBAs of the flash memory. The write LUT 170 contains
`LBAs. For ease of illustration, only four LBAs per LUT are
`shown and only one LBA 302 is described. Each LBA 302
`includes block-offset bits (bit5 to bit0). The block-offset bits
`correspond to a particular sector in a block.
`
`[0053] Each LBA 302 is associated with a PBA 304. In
`this specific example, a PBA is 32-bits long. Also, each LEA
`is associated with a sector number field 306 typically having
`64 more bits, which indicate with the sector data is valid or
`not.
`
`[0054] The write LUT 170 records only the starting LBA
`for a particular write transaction. For example, if a particular
`write transaction requires two or more blocks, the write LUT
`170 records the starting LBA.
`
`[0055] The read LUT 172 provides an index for the flash
`memory during read transactions and translates LBAs pro-
`vided by the host system to PBAs of the flash memory. The
`read LUT 172 is structured similarly to the write LUT 170
`and has the same fields as the write LUT 170.
`
`[0056] After the completion of each write transaction, the
`read LUT 172 is updated to reflect the changes to the write
`LUT 170 such that the write and read LUTs 170 and 172
`
`become identical. Once the read LUT is updated, it can be
`used as an index for read transactions.
`
`to maintain block address consis-
`In operation,
`[0057]
`tency, and achieve write efficiency,
`the write process is
`segregated into two phases. Once the exact addresses are
`calculated from the write LUT 170, the new data sectors are
`immediately written into the flash memory and a confirma-
`tion is returned to the firmware routine. If the next transac-
`tion is a read, the PBA from the read LUT 172 will be used
`to get the correct data stored in the flash memory, if the read
`address is different from the last write address. In the mean
`
`time, valid sector copy from the old block to the new block
`will be done in the background to maintain data coherency.
`
`[0058] The PUT 180 performs physical sector mapping
`and provides a bitmap indicating programmed sectors, i.e.,
`sectors to which data has already been written. Whenever a
`write transaction occurs, the PUT 180 records the usage
`information indicating the programmed sectors. This facili-
`tates write transactions in that the processor of the flash
`memory controller can determine from the PUT 180 which
`
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`sectors are available for programming or reprogramming. A
`bit map of the PUT 180 is a recording of all sectors used.
`
`[0059] A recycling FIFO 190 recycles blocks of obsolete
`and redundant sectors and the recycling process occurs after
`each successful write transaction. Whenever a block having
`an obsolete or redundant sector is encountered, information
`regarding that block is placed in the recycling FIFO 190.
`Such information indicates which sectors are obsolete and
`
`which sectors are redundant. The recycling FIFO 190 per-
`forms valid-sector copy and non-valid block erase opera-
`tions. Non-valid blocks are blocks that contain obsolete or
`
`redundant sectors. The recycling FIFO 190 uses a write
`pointer 192 and read pointers 194 and 196. The copy and
`erase operations are performed in the background,
`i.e.,
`independently from write transactions to not interfere with
`the write transactions.
`
`[0060] Each time a write transaction occurs, the obsolete
`block is placed into the Recycling FIFO. The write pointer
`192 is incremented and the recycling FIFO not-empty flag
`becomes “1.” The copying process begins when the normal
`write process is finished. The erasing and recycling process
`begin when all the necessary copying is finished.
`
`Flash Memory Assembly
`
`[0061] FIGS. 4A-4C are diagrams of a flash memory
`assembly 400, which can be used to implement the flash
`memory controller 110 of FIG. 2. FIG. 4A is a side-view
`diagram of the flash memory assembly 400. The flash
`memory assembly 400 comprises a printed circuit board
`(PCB) 402, a flash memory device 403, a universal serial bus
`(USB) connector 404, a top cover 406, and a bottom cover
`408. The flash memory device 403 and USB connector 404
`are typically soldered to the PCB 402. The flash memory
`device 403 represents a flash memory system, which
`includes flash memory components such as a flash memory
`controller, a flash memory array, etc. While the flash
`memory components of the flash memory system can be
`distinct separate devices, the flash memory system is rep-
`resented as the flash device 403 for ease of illustration.
`
`[0062] FIG. 4B is an exploded perspective-view diagram
`of the flash memory assembly 400 of FIG. 4A in accordance
`with the present invention. Referring to FIGS. 4A and 4B
`together, the PCB assembly 420 includes the combination of
`the PCB 402, the flash memory device 403, and the USB
`connector 404. In other words, the PCB assembly 420 is the
`flash memory assembly 400 without covers. FIG. 4A illus-
`trates the “unbalanced” nature of the flash memory assembly
`400. As shown, the PCB 402 attaches to one side (lower
`portion) of the USB connector 404, hence the term “unbal-
`anced.”
`
`[0063] The flash memory assembly 400 includes align-
`ment pins 412, 414, 416, and 418, which help in aligning and
`engaging the bottom cover 408, the PCB 402, and the top
`cover 406. Alignment holes 422, 424, 426, and 428 reside at
`least partially inside the perimeter of the PCB 402 to allow
`the alignment pins 412-418 to penetrate through. The align-
`ment pins 412-418 are integrated in the bottom cover 408
`and are received in alignment receptacles, which are inte-
`grated in the top cover 406. Alignment receptacles 432 and
`434 (FIG. 4A) receive the alignment pins 412 and 414,
`respectively. Alignment receptacles, which receive Is the
`alignment pins 416 and 418 also present but are hidden from
`
`view. The combination of the alignment pins, holes, and
`receptacles provide a secure coupling for the components of
`the flash memory assembly 400. The pins 412-418 can
`alternatively be integrated into the top cover 406, and the
`corresponding receptacles can be integrated into the bottom
`cover 408.
`
`[0064] FIG. 4C is a blow-up perspective-view diagram of
`the USB connector 404 of FIGS. 4A-4B, where USB
`connector pins 420 are exposed.
`
`[0065] FIG. 5 is a side-view diagram of a flash memory
`assembly 500 in accordance with another embodiment of the
`present invention. The flash memory assembly 500 includes
`a PCB 502, a USB connector 504, a top cover 506, a bottom
`cover 508, and flash memory components 510 and 511. An
`engagement mechanism comprising alignment pins 512 and
`514 helps in assembly alignment and engagement of the
`bottom cover 508, the PCB 502, and the top cover 506.
`Alignment holes 522 and 524 reside at least partially inside
`the perimeter of the PCB 502 to allow the alignment pins
`512 and 514 to penetrate through. The alignment pins 512
`and 514 are integrated in the bottom cover 508 and are
`respectively received in alignment receptacles 532 and 534,
`which are integrated in the top cover 506. Two additional
`alignment pins (configured similarly to the alignment pins
`416 and 418 of FIG. 4B) and corresponding alignment holes
`and alignment receptacles are also present but are hidden
`from view. The combination of the alignment pins, holes,
`and receptacles provide a secure coupling for the compo-
`nents of the flash memory assembly 500. Similar to what has
`been previously described, the alignment pins can be inte-
`grated into the top cover, while the corresponding recep-
`tacles can be integrated into the bottom cover.
`
`[0066] The centerline in the thickness direction of the PCB
`502 attaches substantially symmetrically to the middle por-
`tion of the USB connector 504, hence the term “balanced.”
`A benefit the balanced positioning of the PCB 502 relative
`to the USB connector 504 is that it can accommodate flash
`
`memory components on both sides of the PCB 502 without
`having to modify the same and/or size of the covers. As
`shown, the flash memory component 510 is situated on the
`top side of the PCB 502 and the flash memory component
`511 is situated on the bottom side of the PCB 502. As such,
`the flash memory assembly 500 can have a higher memory
`capacity than can similarly-dimensioned conventional flash
`memory assemblies, which have flash memory components
`only on the top side of the PCB. Since the flash memory
`assembly 500 has a balanced configuration, it can accom-
`modate more flash memory components, hence achieve
`increased memory capacity, without having to increase the
`physical size of the assembly.
`
`[0067] FIGS. 6-8 compare the balanced configuration
`with the unbalanced configuration. FIG. 6 is a side-view
`diagram of a balanced flash memory assembly 600 in
`accordance with the present invention. FIG. 7 is a side-view
`diagram of an unbalanced flash memory assembly 700
`representing a conventional design. Referring to both FIGS.
`6 and 7 together, the balanced flash memory assembly 600
`can accommodate flash memory components 610 and 611 on
`both sides of the PCB 612 without a significance increase,
`if any,
`in cover size (thickness). The unbalanced flash
`memory assembly 700 can also accommodate the flash
`memory components 710 and 711 on both sides of the PCB
`
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`712. However, the thickness of the USB housing (i.e., top
`cover 724 and bottom cover 726) ne