`
`INNOLUX CORP. V. PATENT OF SEMICONDUCTOR ENERGY
`
`LABORATORY CO., LTD.
`
`|PR2013-00066
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`Quicthew
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`00-41
`lo ‘5" m "
`
`__________,
`Introduction
`Emlsslve
`Transmisslve
`Flexible
`Systems
`Addressmg
`Components
`
`Reflectlve
`Projectionm
`Characterizallon
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`Addressing Schemes
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`
`Module 33: Introduction to Addressing
`Schemes
`Module 34: Passive Matrix Addressing
`Module 35: Direct Drive Addressing
`Module 36: Active Matrix Addressing
`
`
`
`Module 36: Active Matrix Addressing
`
`36.1. Basics of Active Matrix Addressing Technology
`Addressing displays with direct drive or passive means cannot provide the resolution or gray scale of high
`performance displays. The active matrix substrate enables high resolution and controllable gray scale. The figure
`below shows the first schematic of an active matrix substrate. Many more schematics and a more in depth
`understanding will follow. The circuit below shows the TFT circuit and cross section
`
`The figure above depicts two pixels of a row of pixels, with the row and column electrodes, and the ground is from
`the top cover plate (unstructured ITO). The figure shows what is known as n-channel field effective transistors, or
`
`
`
`FETs, created using thin film technology. The primary function of the FETs is to act as a non-linear switch at each
`pixel. To render a gate conductive, a positive gate pulse, Vg, is used. The FETs in the other rows are blocked by
`referencing the rows to ground. The video information is fed in through the columns and the conducting TFTs
`simultaneously. The video voltage Vd, which creates the desired gray levels, charges the liquid crystal capacitor,
`CLC, and an additional thin film storage capacitor to a voltage Vd. This is a one row at a time operation. During the
`time when the capacitor is charging, the next capacitor in the succeeding line is grounded and therefore
`connected in parallel to CLC. This can introduce distortion in the waveforms.
`To render an image, the pixel switches must charge N rows in a given frame interval, Tf, therefore the individual
`row address time is
`
` = Tf / N
`Tr
`Now we can look at the voltage across the liquid crystal.
`During the row address time, Tr, the storage capacities are charged with the time constant
`
` represents the 'on' resistance of the TFT. The inequality enforces the condition that the voltage across
`where Ron
`the liquid crystal is only 1% below the desired voltage Vd
` at the end of Tr. After the time Tr, the transistor is
`blocked, but still maintains a finite resistance, Roff.
`
`
`After Tf the row is addressed again and the new image is rendered. During this time, the discharge of the
`
`capacitors should be minimal to provide an output luminance of the pixel as constant as possible, providing a
`
`flicker free image. The time constant for Toff of the discharge is given by the expression:
`
`
`
`thereby ensuring only a 1% drop at Tf. By combining expressions for Ton
`derived.
`
` and Toff, the following equation can be
`
`
`
`As an example, consider an NTSC display with N = 484 rows, we would require
`
`In practice the achievable value of the off current is 10-12A = pA, the value of the on current is therefore
` 10-6 A = 1µA
`Ion
`
`to establish the inequality constant.
`The voltage across the pixel has to be free of dc in order to avoid the effects of ionic migration which can cause a
`degradation in performance and reduce the overall lifetime of the liquid crystals displays. A dc offset can polarize
`ionic impurities with the liquid crystal thereby creating an internal field in the opposite direction of the applied field.
`It is for this reason the liquid crystal fluids used in active matrix applications must be very high resistivity. To solve
`this problem the polarity on VLC is alternated each time.
`Active matrix addressing, which will be presented in more detail following this section, improves resolution and
`gray scale performance - consider a liquid crystal display below which exhibits a linear threshold behavior to about
`the 3V range before the luminance saturates.
`
`To obtain 256 gray levels for example, the voltage step is 11.7 mV / gray level.
`Active matrix displays offer tremendous image quality and high resolution, and do not have the tendency to flicker
`as CRTs. A more in-depth explanation will now be considered.
`
`
`
`36.2. Active Matrix Addressing
`Before looking at how to address an active matrix circuit it is useful to understand them at the component
`level. We will first look at amorphous silicon (a-Si) and then poly-silicon (poly-Si).
`
`
`36.2.1. Properties of a-Si and poly-Si thin Film Transistors
`The figure below shows:
`i. The symbol of a metal insulator-semiconductor field effect transistor (MIS-FET)
`ii. The cross section of the bottom gate TFT
`iii. The cross section of a top gate TFT
`In the figure ( i ), the TFT with voltage and currents are MIS-FETs which are primarily utilized as the bottom
`gate. In figures ( ii ) and ( iii ) are usually used used as to p gate transistor
`The order on the substrate is as follows:
`the metallic bottom gate in ii is depointed
`gate dielectric
`a-Si semiconductor
`metal drain
`source electrodes
`the protective layer
`The drain can be Al, Mo, Cr; the source can be AI, Mo, Al; the gate can be Al, Mo, Crl the date dielectric
`; and the semiconductor is either a-Si or poly-Si.
`can be SiNx, SiO2
`
`(i)
`
`
`
`(ii)
`
`(iii)
`
`The top gate shown in ( iii ) has an inverted sequence of layers. The primary difference to the MIS-FET is
`the semiconductor it is amorphous. This is because the film deposition process cannot provide crystalline
`layers. Thermal or laser annealing can be used to introduce crystal growth. This type of annealing usually
`results in crystal regions separated by grain boundaries - these polycrystalline layers can be used for poly-
`Si TFTs.
`Looking at figure ( i ) above, the operation of a a-Si TFT is as follows:
`separation of charge in the capacitor between the gate electrode and the electrode formed by the
`drain and source, and the distribution of the potential along the upper surface of the semiconducting
`channel
`the charge separation is induced by the gate-source voltage VG
`the voltage between the drain and source, VO, causes the electric field parallel to the surface of the
`n-channel of the a-Sil this transports the negative charge to the drain
`the drain current follow the same established law for FETs, which is
`
`
`
`where VTh
`
` is the threshold voltage
`
` = 0 VG
`
`ID
`
` V
`
`Th
`
`where µ is the electron mobility, w stands for the width of the channel, and l for the length of the channel.
`The gate capacitance is simply
`
`where d is the thickness of the gate dielectric. The threshold voltage is given by the following expression
`
`where e is the charge of an electron, n0
`is the thickness of the channel.
`An alternative set of equations can also be written, where the sequence of the last two equations is
`inversed
`
` is the charge density within the semiconducting channel, and dHL
`
`In practice the channel has a finite sheet resistance resulting in an off-current
`
`The region of transition is modeled by equations
`
`
`
`The region of saturation is modeled by the equations
`
`The inherent assumption in the equations is known as Shokley's gradual channel approximation
`
`
`electric field within the channel direction from drain to source >> field perpendicular to it
`
`
`
` ...more
`
`
`To get a more intuitive feel for these equations, the are graphically illustrated below. Using the following
`notation to simplify the presentation
`
`which has units of V2.
`
`
`
`The transition region above is parabollic in the downward directions, with the vortex at
`
`The boarder is sketch in as a dashed line and the entire transition region is shaded.
`Using similar nomenclature, the input characteristics are shown graphically below.
`
`
`
`Note that for the saturation region, I is independent of VD
`
`
`The figure also shows that in the saturation regions VG
`We can also represent the input characteristics using
`
` VD
`
` VD)
`; I is linear in VG ( I
` + VTh
` on the y-axis as shown below.
`
`
`
`For VG
`
` VD
`
` + VTh, a linear relationship exists as shown above
`
`where
`
` provides VTh
`The mobility can be extracted from the above graph. Data points on the linear line for
`the intersection with the x-axis and the slope M which enables the following expression for mobility
`
` as
`
`The figure below shows the drain current as a function of gate voltage. Such a plot enables one to
`determine the properties of an a-Si TFT at low currents. Here the y-axis is a logarithmic scale and the solid
`line is the data. The dashed curve is derived from the equations, assuming saturation. The V between
`the two curves in the figure is just the difference between the saturation curve and the data at the 10-10 A
`value. If V is small, this indicates better blocking properties of the TFT.
`
`For purposes in displays, the following parameters are sufficient:
`µ (derived from saturation regime)
` (threshold voltage)
`VTh
`V (or Ioff) (derived from low current regime)
`TFT Parameters
`µ
`
`Typical Values
`~1 cm2 / V.s
`
`
`
`These are just some ball-park number.
`
`VTh
`V
` Ioff
`
`~1V
`~2.5 V
`10-12 A (at -3.5)
`
`NEXT: TFT in LCDs
`
`
`
`36.3. TFT in LCDs
`The following sections will outline static operation of a TFT and then its degeneric operation
`
`
`36.3.1. Static Operation
`First, the operation of the TFT as switches in the LCDs applications enable voltage to the columns to charge a
`storage capacitor. The circuit is shown here
`
`
`
`
`
`
`The charging of the storage capacities
`
`at a pixel must occur with a response time given be
`
`
`
`CLC + Cs
`
`The on-resistance Ron, of the TFT can be expressed as:
`
` (areal charge density). The are density is basically the
`which can also be expressed in terms of µ (mobility),
` of a channel of width
`density in a unit are with the thickness dHL
` and length
`, given by the following
`expression
`
` defines the level of gray, on that pixel and imposes a constraint on the time constant Tf,
` + Cs
`The charge on Chc
`resulting in the following expression
`
`The figure below shows schematic for the TFT pixel for a positive voltage charging CLC
`(right).
`
` (left) and a negative one
`
`
`
`The parasitic capacitance is rather complicated. The TFT is embedded in its own voltage dependent parasitic
` is the capacitance and resistance of the liquid crystal layer, with
`
`capacitance.: CGS, CGD, and CDS; CLC
` and RLC
`the lower electrode being at ground; CS is an additional thin film capacitance enhancing that of the liquid crystal
`
` + CS. CS is not connected to ground as is CLC, but rather to the next gate line, saving the ground line.
`CLC
`In the figure below, from the two columns, the parasitics Cc1e
` and Cc2e
` below couple into Vp
` which is VLC
`
`
`
` shown above render the appropriate
` and Vr2
`The rows r1 and r2 are gate lines, and carry the gate pulses Vr1
`TFTs conductive during the row address time Tr
` with voltage Vg
` and block it with voltage V0.
`The figure below shows the gate impulses and their effect on the pixel voltage Vp. When the TFTs are conductive
`during the row address time Tr with voltage Vg, and block it with V0
` during the remainder of Tf. The video signal
`on column 1 is positive during one frame time Tf and negative during the following frame time. This is to provide a
`dc free pixel voltage to minimize ionic effects of the liquid crystal.
`
`NEXT: Ionic Impurities
`
`
`
`36.4. Ionic Impurities
`
` ...more
`
`
`Capacitance voltage dividers transmit the steps of the gate voltage onto VLC, where they result in changes
` must me known and maintained, take 256 gray
`of gray levels. To give you an idea of how precisely VLC
`scales and a 5V swing in voltage then 51mV defines each gray level.
`
` reaches a desired value VV1 within Tr, followed by the
`Investigating the above gate impulse figure, VLC
`negative step -(Vg-V0) of the row pulse, that is the falling edge of Vr1 at time = Tr, which reaches VLC
`
`through the capacitive voltage divider CGS and CLC
`
` + CS as a step-change VLC.
`
`The negative video voltage in the above figure - VV@, the identical negative step Vg-V0 of the row pulse
` in the above expression.
`Vr1 again lowers VLC
` by VLC
` - 60 fF and Vg-V0
` - 80fF, Cs
` for typical values: CGS = 20pF, CLC
`An example would be to determine VLC
`
`- 8V resulting in VLC
` = 1V, This would correspond to 30 gray shades requiring a compensation of VLC.
`
`
`
` to ascertain the effect of mobility and channel size. The
`We can also manipulate the expression for VLC
`charge within the channel during the presence of a gate pulse is
`
` is the electron charge.
` is the overlays between the drain a source with the gate and
`where
`After the drop to zero of the gate pulse, a voltage drop follows because a part of K of the negative charge is
`distributed mainly onto the larger capacitance CLC
` and Cs. The voltage drop is
`
`which can be expressed using subsequent equation:
`
`This is an important result since |VLC| can be decreased by a large mobility of small channel length, or a
`small overlap
`.
` by VLC. It can change the position of gray
`Now, consider the practical implications of the shift in VLC
`levels and introduce a dc offset on the pixel voltage. Both of these present a problem. To overcome both of
`these problems, the potential on the backplane can be lowered by VLC
` which is depicted in the left
`figure.
`Another way to overcome this problem is to use a compensated pulse, shown in the figure below. The lines
`are now addressed with the row voltage Vri, then row 2 is addressed
`
`The TFT addressing with a compensation impulse
`Now the falling edge of Vr2 has increased by Vcom
` to Vg
` - V0
` + Vcom, V0
` < 0 resulting in a VLC
`
` as
`
`
`
`A step Vcom
`CLC
`
` in the compensated impulse of r1 goes through the capacitive voltage driven Cs
`
`
`
` and CGS +
`
` as depicted in the figure.
` of row r2
`onto VLC
`Therefore, for the compensation of VLC, the following requirement must hold VLC
`identically zero
`
` + Vcom
`
` must be
`
`By solving the above equation
`
`As an example, take the following values to arrive at a ball park number for Vcom. Substituting Vg-V0 = 8V,
` = 4 Volts.
`
`CGS = 20 fF and Cs
` = 60 fF, the value of Vcom
`To obtain the values of the row voltage Vg in the on-state and V0
`1. by switching the voltage of the back plane by VLC
`2. by a compensating impulse Vcom
`Therefore by introducing the voltage source Vfp = VLC, both correction methods are satisfied.
`In the on-state, the following condition must hold
`
` in the off state, there are two approaches:
`
`and from the previous figure
`
` + VFP
`Vg = VG + VLC
`
`
`for a positive voltage VLC. For the negative voltage VLC, the transition operates with the source and drain
`interchanged. This is made possible by the symmetry of the TFT
`
`
`Vg = VG + Vcl
`
`where the video voltage on the column is
`
`for positive Vcl, and
`
` = VG + Vcl
`
` in the expression Vg
`for negative Vcl
`The voltage across the pixel in the conducting state is
`
`
`
` - VFP
`VLC = Vcl
` in the above equation spans the complete linear regime of
` are chosen such that VLC
`where Vmin
` and Vmax
`the luminescence voltage curve of an LCD for example.
`In the worst case scenario,
`
`where
`
`results in
`
`for positive voltage and
`
`for negative ones.
`For a non-selected pixel, the value of V0 can be derived. Starting with the requirement
`
`VG < VTh
`
`or in the worst case scenario
`
`For the holding charge, the above equation has to be considered after the steps of all voltages have
`influenced their effect VLC, where it occurs. This voltage can be expressed as:
`
`where
`
` can be expressed as
`
` is simply the voltage across CLC
`be derived from earlier equations to be
`
` = Vcl + VFB
`
` before the drop caused by the row voltage. The largest drop can
`
`The worst case scenario is
`
`The row address signals determined by row voltage Vg in the on state, V0 in the off state, and either the
`sheet in potential of the front plate VFP or the compensation pulse. In terms of overall performance of the
`display, both the adjustments of the backplane and compensation pulse are equivalent. In practice the
`
`
`
`shifted front plate potential is exercised in applications. It is simpler since gate line drives independent of
`the TFT specific and pixel specific compensation scheme.
`
`In addition to the falling flanks of the row addressed signals coupling to VLC, the rising ones also do. This
`advertise influence, which can result in jitter, can be eliminated by introducing a second line to ground
` arising from the falling flank
`connected to Cs
` in the above figure. It does not eliminate the influence on VLC
`of the gate impulse. It does however eliminate the need to feed in the compensation impulse. The only
`correction left is the shift in the potential in the back plane.
`In larger displays with a higher resistance of the lines, current for charging and reverse charging the
`storage capacitor flow into the gate line. This can be solved by alternating the sign of neighboring column
`signals.
` of the parasitic
` and Vc2
`Further capacitive coupling in the above figure feed into the video signals Vc1
`capacitances
` causing the pixel voltage to change by
` onto CLC
` + Cs
`
`
` (V) depend on the
` (V) and CLC
` is virtually impossible as Vc1, Vc2, CSD
`An absolute correction to VLC
`video voltage. A substantial decrease of VLC
` is achieved by alternating the sign of Vc1 and Vc2. This can
`be accomplished line by line after each frame , from column to column, or a combination thereof.
`
`
`
`The capacitive coupling can be significantly reduced by replacing the stepwise edge of the row pulse by
`one that declines more gradually. As this will obviously increase the addressing time, the previous speed
`can only be restored by overlapping two consecutive gate pulses. By rounding off the upper portion of the
`of the flank and implement a very steep increase and decline, the same phenomena can be observed. The
`gate line represents an RC-line, including the crossover capacitances of the rows and columns. The
`stepwise response of a homogenous RC-line at the termination of the line is expressed by the following
`expression:
`
` respectivelywhere the total resistance and capaciting is denoted as RTOT and CTOT
`
`
`The step response exhibits a delay and a decrease of the rise time T0 from 10 % to 90% of the final values
`
`to T0 ~ 0.9 RTOT CTOT. The delay and reduced rise time limit resolution, r, for a display with a diagonal
`dimension D, given by the relationship
`
`where
`
` is the sheet resistance of the row and
`
` typically
`
`.
`
`NEXT: Dynamic Switching of TFTs
`
`
`
`
`
`36.5. Dynamic Switching of TFTs
`In the previous section, the steady state solutions were derived. In this section we will provide the desired
`voltages at any instant in time.
`Starting with the node equation
`
`where i = C.V. Expressing the above equation in terms of C and V,
`
`In the transition region, argued in the static section
` = VC
`
`VG = Vr - VLC
` and VD
`We can rearrange the above equation to reduce its notation
`
` - VLC
`
`where the following notation is defined.
`
`In most cases the following simplifying assumption can be made:
`
` is the resistance of the liquid crystal. Now we can perform a non-linear transformation to the
`where RLC
`above differential equation
`
`which provides a first order linear differential equation with constant coefficients given by the expression
`
`
`
`To conserve the dimension ability of this differential equation is:
`
`where a is the constant of integration. Using the following initial condition
`
`which results in the following form for a
`
`substituting the constant of integration back into the general solution yields the following solution:
`
`where q simplifies the notation
`
` - VTh - Vc
`
`q = Vr
` is the time right before the end of the charge, which gives the pixel voltage to which
`The time at
` occurs immediately
` has been charged. The stepwise change VLC
` due the falling flank of Vr
`CLC
`afterwards reducing
`.
` to a negative voltage is governed by the node equation
`Charging CLC
` + Cs
`
`with the same considerations as charging with a positive voltage, the equations are very similar.
`
`where
`
`Again transforming the equation and simplifying the solution becomes
`
`
`
`Now these two voltages can be used to derive Vg for the on state and V0 for the off state of the TFT.
`The primary requirement for VLC
` (t) is that it reaches Vc
` within the time Tr, and determines the correct
`gray level for the remainder of the frame time Tf. This can be expressed by the following notation which
`expresses reaching Vc
` within Tr.
` (t) must be equivalent at
`
` and
`
`VLC
`
`and
` and Tf +
` +
`VLC(t) must be equivalent at t = Tf
` ( Tf +
`) = - VLC
` +
`) = - VLC
` ( Tf
` (
`VLC(
`) = VLC
`)
`Inserting these conditions into our solutions for VLC(t), results in the following simplification
`
`
`
`and
`
` charging to Vc
`
` charging to -Vc
`
`
`In practice, we need to replace Ø with a small number so we rewrite the above conditions as:
`
`where steady state is reached from below
`
` Vc
`
` > 0 positive charging
`
` Vc < 0 negative charging
`
`where the steady state us reached from above
`We can take the natural logarithm of the above equation to obtain
`
`
`
`The time constants for charging to + Vc
`
` and - Vc
`
` are given by the expressions
`
` when VC < 0, the relationship between
`
` and
`
`-
`
` is :
`t
`
`Also, for the CGS = CGD
`
`
`
` <
`t
`-
`The largest time constant is encountered when Vc
`
` = Vmax
`
` for
`
`
`t
`
`where
`
`the worst case scenario is:
`
`where Vr
`
` = Vg
`
` for Vr
`
` > 0 to arrive at this case
`
`
`
` ( VLC) is shown above. The low
`The voltage dependence non-linear response of the capacitance CLC
`value
` is reached when electric field is perpendicular to the nematic director and the high value
` is reached when the electric field is parallel to the director for a positive dielectric constant material.
`
`
`
`
`
`Module 40: Indium Tin Oxide (ITO) In2O3/SnO2
`
`
`
`40.1. Introduction
`Indium Tin Oxide, In2O3/SnO2 is used as a thin coating polymer based substrates to produce a
`transparent optical film. The substrate used as a film can be Polyethylene Terephtalate (PET).
`
`Interest in indium tin oxide began as far back as 1907 when transparent conductive cadmium oxide (CdO)
`films were made known. Continuous interest exists in developing this technology as well as the techniques
`by which transparent conductive films are fabricated. Various types of non-stoichiometric and doped films
`of oxides of tin, indium cadmium, zinc and other alloys exhibit high transmission, but indium-tin-oxide is
`found to be one of the best alloys for this technology due to its high transmission efficiency of 95% and
`conductivity of 1.0e4 W-1cm-1.
`
`40.2. Applications of ITO
`There’s a wide array of uses and applications that incorporate ITO. Some of these applications include
`transparent heating elements of aircraft and car windows, antistatic coatings over electronic instrument
`display panels, heat reflecting mirrors, antireflection coatings and high temperature gas sensors. Electro-
`optic devices incorporating ITO include CCD arrays, liquid crystal displays, and transparent electrodes for
`various display devices. Current applications that incorporate ITO include solar cells, light emitting and
`photo-diodes, photo-transistors and lasers.
`
`
`
`40.3. Physical structure and ITO Properties
`Transparent conducting coating: technique used to make thin conductive layers on films include Electron
`beam evaporation and sputtering, and magnetron sputtering technique for roll coating on polymer
`substrates. ITO is realized by doping of In2O3 with Sn. Sn takes the place of In3+ atoms from the cubic
`
`
`
`bixbyte structure of indium oxide. Tin and oxygen forms an interstitial bond and exits as Sn) or Sn02-,
`forming a valence of +2 or +4. The valence state influences the conductivity of the ITO. A lower valence
`state reduces the carrier concentration; holes are created and traps electrons. If Sn02 exits, Sn4+ acts as
`an n-type donor releasing electrons to the conduction band.
`Reported values for the bandgap of ITO films range from 3.75 to 4.06 eV. This wide bandgap
`semiconductor results in high optical transmittance. The optical transmittance is also affected by surface
`roughness and optical inhomogeneity on the film’s surface.
`
`
`40.4. Physical Properties of Solid ITO Material
`Molecular Weight
`Varies with composition
`Melting Point
`~1900° C
`Light yellow to gray, depending on degree
`Color
`of oxidation
`Crystal Density
` ~7.14 g/cc
`
`
`40.5. Some ITO Specs:
`Chemical Formula
`In2O2/Sno2
`Typical Average Particle Size 14nm
`Specific Surface Area (BET) 40 - 80m2/g
`99.5 +%
`Purity
`Yellow-Greento Blue-Green
`Color
`Bulk Density
`0.20 grams/cm3
`True Density
`7.1 grams/cm3
`Refractive Index (@ 500nm) 2.0
`
`
`
`40.6. ITO Film Properties:
`In order to achieve good optical and electronic properties for ITO film, the deposition parameters must be
`carefully chosen and the composition of material to be used during the evaporation process carefully
`chosen.
`1. High density of charge carriers for the deposited films is needed to achieve good conduction.
`(Charge carriers are free electrons and O2 vacancies)
`2. High conductivity (low sheet resistance) must be balanced against high transmission in visible region.
`Sheet Resistance (W/)
`% Transmission (visible)
`<10
`>80
`Visible
`<100
`>90
`Visible
`<30
`>80
`Infrared
`Films will behave as metals to long wavelength light, and will become reflecting at longer wavelengths. The
`
`
`
`index of refraction n ~1.05 near visible, and is almost independent of deposition parameters chosen.
`Deposition parameters include partial pressure of O2, substrate temperature, and deposition rate.
`
`
`40.7. Deposition Techniques:
`Various deposition techniques exist for ITO deposition. One of the most common forms is sputtering, then
`thermal evaporation. Other methods that can result in ITO deposition include Spray Pyrolysis and Screen
`Printing. Choosing a deposition technique is dependent upon the quality and reproducibility of the ITO film,
`homogeneity over a wide cross section, capacity, and cost.
`
`
`
`40.8. Sputtering
`Sputtering, or transition of molecule from some target material to a substrate usually consists of 90% hot
`pressed In2O3 and 10% SnO2 compound targets. Molecules are knocked out of a target material by
`accelerating ions (d.c. field or r.f, or ion beams) from some excited plasma and condensing it unto the
`substrate. Hence the name origin of d.c., r.f., and ion-beam sputtering. Some parameters that affect the
`sputtering quality include sputtering pressure, pre-conditioning, and film thickness.
`
`R = r / t
`r = Resistivity
`t = Thickness
`R = Resistance
`
`
`40.9. Thermal Evaporation
`
`
`
`As suggested by name, this deposition technique vaporizes a solid through high temperature heating of the
`material and recondensing the material unto a cooler substrate. A high temperature of 300 °C to 450 °C is
`achieved by resistively heating or by firing an electron or ion beam at the material. Here 95% In-5%Sn alloy
`(by wt.) is used as the source. For reactive thermal evaporation technique, the film depends on oxygen
`partial pressure and film thickness, deposition rate, substrate temperature and tin concentration. Such high
`temperatures are needed during the evaporation process in order to enhance the conductivity and
`transmittance of the film.
`Spray Pyrolysis.
`A very attractive deposition technique, Spray Pyrolysis does not requite a vacuum and deposits at a very
`fast rate (> 1000A/sec). The spraying of ITO from an alcoholic solution of anhydrous indium chloride (InCl3)
`and tin chloride (SnCl4.5H2O) with nitrogen carrier gas, is all done inside a furnace held at 400 °C. The
`parameters needed to achieve qualify deposition include positioning of the substrate and the chemical
`composition of the spray solution. This technique has yielded resistivities of 1.0e-3 Wcm for a 4300 A thick
`ITO film, with > 90% transmission at 550 nm.
`
`
`
`40.10. Screen Printing
`The deposition technique is necessary for large-scale applications and thick layers of ITO such as liquid
`crystal displays, blackwall contacts, and antireflection coatings for solar cells. ITO layer thickness range
`from 10 to 30 mm with post deposition crystallization temperature up to 600 °C. The resistivity values are
`greater than 4.0e-4Wcm, with a much lower transmission <80%.
`
`
`40.11. Summary of electrical and optical properties of typical ITO films deposited for various
`techniques
`
`Deposition
`Technique
`r.f. Sputtering
`r.f. Sputtering
`r.f. Sputtering
`Magnetron
`Sputtering
`d.c. Sputtering
`Reactive
`Evaporation
`Ion Beam
`Sputtering
`Spray Pyrolysis
`
`
`Thickness
`[A]
`7000
`5000
`4000
`
`Hall Mobility
`mH[cm2V-1s-1]
`35
`12
`25
`
`Carriers N
`[cm-3]
`6e20
`12e20
`3e20
`
`Resistivity r
`[
`cm]
`3e-4
`4e-4
`8e-4
`
`800
`
`1000
`
`2500
`
`600
`
`3000
`
`26
`
`35
`
`30
`
`26
`
`45
`
`6e20
`
`9e20
`
`5e20
`
`2e20
`
`5e20
`
`4e-4
`
`2e-4
`
`4e-4
`
`12e-4
`
`3e-4
`
`Transmittance
`Tr [%]
`
`90
`95
`-
`
`85
`
`85
`
`91
`
`-
`
`85
`
`Ref.
`No.
`[5]
`[6]
`[7]
`
`[8]
`
`[9]
`
`[10]
`
`[11]
`
`[12]
`
`40.12. Why use Polyethylene Terephthalate (Why PET?)
`Although not the only resort as substrate for ITO, PET’s superb properties makes it one of the best
`substrates to use with ITO as films in the display industry. PET serves as substrates in lightweight and
`portable display devices, digital cameras/camcorders, mobile phones, touch sensors. PET and
`polycarbonate are the two most widely used substrates in flexible display applications due to their superior
`
`
`
`optical properties.
`
`40.13. What’s limiting PET?
`One of the limiting factor to using PET or polycarbonate as substrates for flexible displays is their inferior
`mechanical property. Although both have great optical properties, it’s performance for future flexible
`applications is limiting. Polyimide is a high performance-engineering polymer with a Young’s modulus of 5
`GPa, quite robust for flexible roll-to-roll fabrication.
`
`
`40.14. Other Polymer Substrate Types:
`ITO can be successfully deposited on PET, Polycarbonate, Polytetrafluoroephthalate (Teflon) and
`thermoplastic Polymethylmethacrylate (Perspex, plexi-glass).
`
`
`38.15. Applications for ITO-coated substrates include:
`Touch panel
`Electrodes for LCD and electrochromic displays
`Flexible displays
`Automotive and aircraft display systems and windows
`Gas sensors
`Antistatic window coatings
`Heat reflecting coatings to increase light bulb efficiency
`Wear resistant layers on glass
`
`
`
`40.16. What’s the Industry Standard?
`For practical applications the standard for good performance require include:
`-Range between 80 W/sq to 500 W/sq for a corresponding thickness in ITO layer of 5-150 nm.
`
`
`40.17. Issues to be Resolved!
`Before flexible displays and devices become the dominant technology, surpassing glass-based substrates,
`the temperature sensitivity required for deposition during the fabrication process needs to be resolved.
`Furthermore, the ITO layer deteriorates in-service due to mechanical deformation of the substrates, which
`is accelerated with increasing temperature and applied stress.
`
`40.18. Shrinkage Studies of ITO/PET
`Thermal mechanical analysis of ITO/PET with temperature was performed to measure the mechanical
`properties of film with temperature and to determine the shrinkage characteristics of film with temperature.
`
`
`
`Analysis showed that shrinkage is highly temperature dependent and reaches 4% strain (0.04) at 180°C,
`which is near the threshold stain at which cracking occurs in the ITO layer, thus having a high impact on
`ITO resistance. If shrinkage is greater than 2%, it may cause cracking in the ITO causing the resistance to
`increase.
`
`Reflection of ITO coated PET
`In order to obtain lower and higher resistance ITO films, one needs to change the thickness of the ITO film.
`Particularly to obtain a very low resistance, the ITO thickness has to be increased which can lead to higher
`absorption in the product due to its absorption edge at the blue light (band gap is 3.75ev). Depending on
`the thickness, the transmission of ITO varies in the visible region of the light spectrum. ITO has a refractive
`index of approximately 2 in the visible range and the commonly used flexible substrate (PET) has a
`refractive index of approximately 1.66. There is an optical interference from the reflections of surfaces
`between ITO/air, ITO/substrate and substrate/air on the backside as seen in Figure 1.
`Adding multiple layers of ITO coatings can improve the quality and performance of the ITO film.
`Improvements include:
`Enhancing mechanical durability (adhesion, abrasion)
`Improving environmental