`
`Attorney Docket No. 0756-8108
`
`Confirmation No.: 4620
`
`Examiner: Michael Lebentritt
`
`Group Art Unit: 2829
`
`In re Patent Application of:
`
`Hongyong ZHANG et al.
`
`Serial No.: 11/898,833
`
`Filed: September 17, 2007
`
`For: ELECTRO-OPTICAL DEVICE AND
`
`THIN FILM TRANSISTOR AND
`
`METHOD FOR FORMING THE
`
`SAME
`
`TERMINAL DISCLAIMER
`
`Honorable Commissioner of Patents
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`Dear Sir:
`
`I, Dr. Shunpei Yamazaki, having a place of business at Semiconductor Energy
`
`Laboratory Co., Ltd., 398 Hase Atsugi-shi, Kanagawa-ken, 243 Japan, state that I am
`
`authorized to sign on behalf of the assignee of this invention and that the Assignment
`
`referred to below has been reviewed and certify that, to the best of my knowledge and
`
`belief, the entire right, title and interest in the above-identified application is in the name
`
`of Semiconductor Energy Laboratory Co., Ltd. by virtue of an Assignment recorded in
`
`the U.S. Patent and Trademark Office at Reel 6166, Frames 0166-0168.
`
`Semiconductor Energy Laboratory Co., Ltd. hereby disclaims, except as provided
`
`below,
`
`the terminal part of the statutory term of any patent granted on the instant
`
`application, which would extend beyond the expiration date of the full statutory term
`
`defined in 35 U.S.C. 154 to 156 and 173, as presently shortened by any terminal
`
`disclaimer, of prior U.S. Patent Nos. 6,124,155 and 6,797,548. Semiconductor Energy
`
`Laboratory Co., Ltd. hereby agrees that any patent so granted on the instant application
`
`shall be enforceable only for and during such period that
`
`it and U.S. Patent Nos.
`
`Exhibit 1013, page 1
`
`
`
`- 2 -
`
`Application Serial No. 11/898,833
`Attorney Docket No. 0756-8108
`
`6,124,155 and 6,797,548 are commonly owned. This agreement runs with any patent
`
`granted on the instant application and is binding upon the grantee, its successors or
`assigns.
`
`In making the above disclaimer, Semiconductor Energy Laboratory Co., Ltd.
`
`does not disclaim the terminal part of any patent granted on the instant application that
`
`would extend to the expiration date of the full statutory term as defined in 35 U.S.C. 154
`
`to 156 and 173 of U.S. Patent Nos. 6,124,155 and 6,797,548, as presently shortened by
`
`any terminal disclaimer,
`
`in the event
`
`that
`
`they later expire for
`
`failure to pay a
`
`maintenance fee, are held unenforceable, are found invalid by a court of competent
`
`jurisdiction, are statutorily disclaimed in whole or terminally disclaimed under 35 CFR
`
`1.321, have all claims cancelled by a reexamination certificate, are reissued, or are in
`
`any manner terminated prior to the expiration of their full statutory term as presently
`
`shortened by any terminal disclaimer.
`
`I hereby declare that all statements made herein of my own knowledge are true
`
`and that all statements made on information and belief are believed to be true; and
`
`further that these statements were made with the knowledge that willful false statements
`
`and the like so made are punishable by fine or imprisonment, or both, under Section
`
`1001 of Title 18 of the United States Code and that such willful false statements may
`
`jeopardize the validity of the application or any patent issuing thereon.
`
`OS/If/Zd/f/
`
`Date ~~Title: President
`
`Company Name: Semiconductor Energy Laboratory Co., Ltd.
`
`Exhibit 1013, page 2
`
`
`
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`Attorney Docket No. 0756-8108
`
`) Confirmation No.: 4620
`
`) Examiner: Michael Lebentritt
`
`) Group Art Unit: 2829
`
`) ) ) ) )
`
`In re Patent Application of:
`
`Hongyong ZHANG et al.
`
`Serial No.: 11/898,833
`
`Filed: September 17, 2007
`
`For: ELECTRO-OPTICAL DEVICE AND
`
`THIN FILM TRANSISTOR AND
`
`METHOD FOR FORMING THE
`
`SAME
`
`AMENDMENT
`
`Honorable Commissioner of Patents
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`Dear Sir:
`
`In response to the Official Action dated November 6, 2009, please consider the
`
`following amendments and remarks in connection with the above-identified application.
`
`Amendments to the Claims are reflected in the listing of claims, which begins
`
`on page 2 of this paper.
`
`Remarks begin on page 17 of this paper.
`
`Exhibit 1013, page 3
`
`
`
`- 2 -
`
`Application Serial No. 11/898,833
`Attorney Docket No. 0756-8108
`
`The listing of claims will replace all prior versions, and listings, of claims in the
`application:
`
`Listing of Claims:
`
`(Currently Amended) A method of manufacturing a display device including a
`1.
`thin film transistor, the method comprising the steps of:
`forming a gate electrode over a glass substrate;
`forming a gate insulating film comprising silicon nitride [[on]] over said gate
`electrode;
`
`forming a first semiconductor film comprising amorphous silicon over said gate
`electrode with said gate insulating film interposed therebetween;
`
`forming an N-type semiconductor film on said first semiconductor film;
`patterning said first and N-type semiconductor films using a first photomask;
`forming a conductive layer on at least the patterned N-type semiconductor film;
`etching a portion of said conductive layer to form source and drain electrodes
`using a resist formed by a second photomask;
`
`etching a portion of the patterned N-type semiconductor film to form source and
`drain regions by dry etching using said resist wherein a channel forming region is
`
`formed in said first semiconductor film between said source and drain regions; and
`forming a passivation film over said glass substrate to cover at least said source
`and drain electrodes, said channel forming region, a part of a surface of said source
`region not covered by said source electrode and a part of a surface of said drain region
`not covered by said drain electrode after removing said resist
`wherein each of the source and drain regions has a bottom surface in contact
`with the first semiconductor film, each of the source and drain electrodes has a bottom
`surface in contact with corresponding one of the source and drain regions, and a
`distance between opposed ends of
`the bottom surfaces of
`the source and drain
`
`Exhibit 1013, page 4
`
`
`
`- 3 _.
`
`Application Serial No. 11/898,833
`Attorney Docket No. 0756-8108
`
`electrodes is larger than a distance between opposed ends of the bottom surfaces of
`the source and drain regions.
`
`(Original) The method of manufacturing a display device including a thin film
`2.
`transistor according to claim 1 wherein said N-type semiconductor film contains
`
`phosphorous.
`
`(Original) The method of manufacturing a display device including a thin film
`3.
`transistor according to claim 1 further comprising a step of overetching said conductive
`layer using said resist so that a distance between said source and drain regions is
`shorter than a distance between said source and drain electrodes wherein said
`
`overetching of said conductive layer is performed by wet etching.
`
`(Original) The method of manufacturing a display device including a thin film
`4.
`transistor according to claim 1 wherein each of said source region and said drain region
`
`partly overlaps said gate electrode.
`
`5.
`
`(Original) The method of manufacturing a display device including a thin film
`
`transistor according to claim 1 further comprising a step of irradiating at
`channel forming region with a laser for crystallization.
`
`least said
`
`(Original) The method of manufacturing a display device including a thin film
`6.
`transistor according to claim 1 wherein said passivation film comprises silicon oxide.
`
`(Original) The method of manufacturing a display device including a thin film
`7.
`transistor according to claim 1 wherein said channel forming region comprises intrinsic
`
`amorphous silicon.
`
`Exhibit 1013, page 5
`
`
`
`- 4 -
`
`Application Serial No. 11/898,833
`Attorney Docket No. 0756-8108
`
`8.
`
`(Original) The method of manufacturing a display device including a thin film
`
`transistor according to claim 1 wherein said passivation film is formed so as to cover a
`portion of said glass substrate where said thin film transistor is not formed.
`
`9.
`
`(Currently Amended) A method of manufacturing a display device including a
`
`thin film transistor, the method comprising the steps of:
`
`forming a gate electrode over a glass substrate;
`
`forming a gate insulating film comprising silicon nitride on said gate electrode;
`
`forming a first semiconductor film over said gate electrode with said gate
`
`insulating film interposed therebetween;
`
`forming an N-type semiconductor film on said first semiconductor film;
`
`patterning said first and N-type semiconductor films using a first photomask;
`
`forming a conductive layer on at least the patterned N-type semiconductor film;
`
`etching a portion of said conductive layer to form source and drain electrodes
`using a resist formed by a second photomask;
`
`etching a portion of the patterned N-type semiconductor film to form source and
`
`drain regions by dry etching without removing said resist wherein a channel forming
`
`region is formed in said first semiconductor film between said source and drain regions;
`
`and
`
`forming a passivation film over said glass substrate to cover at least said source
`
`and drain electrodes, said channel forming region, a part of a surface of said source
`
`region not covered by said source electrode and a part of a surface of said drain region
`
`not covered by said drain electrode after removing said resist
`
`wherein an upper portion of each of said source and drain regions extend
`
`beyond a lower portion of each of said source and drain electrodes so that a distance
`
`between the source and drain regions is shorter than a distance between the source
`and drain electrodes.
`
`Exhibit 1013, page 6
`
`
`
`- 5 -
`
`Application Serial No. 11/898,833
`Attorney Docket No. 0756-8108
`
`10. (Original) The method of manufacturing a display device including a thin film
`
`transistor according to claim 9 wherein said N-type semiconductor film contains
`phosphorous.
`
`11. (Original) The method of manufacturing a display device including a thin film
`
`transistor according to claim 9 further comprising a step of overetching said conductive
`
`layer using said resist so that a distance between said source and drain regions is
`
`than a distance between said source and drain electrodes wherein said
`shorter
`overetching of said conductive layer is performed by wet etching.
`
`12. (Original) The method of manufacturing a display device including a thin film
`
`transistor according to claim 9 wherein each of said source region and said drain region
`
`partly overlaps said gate electrode.
`
`13.
`
`(Original) The method of manufacturing a display device including a thin film
`
`transistor according to claim 9 further comprising a step of irradiating at
`
`least said
`
`channel forming region with a laser for crystallization.
`
`14.
`
`(Original) The method of manufacturing a display device including a thin film
`
`transistor according to claim 9 wherein said passivation film comprises silicon oxide.
`
`15.
`
`(Original) The method of manufacturing a display device including a thin film
`
`transistor according to claim 9 wherein said channel forming region comprises intrinsic
`
`amorphous silicon.
`
`Exhibit 1013, page 7
`
`
`
`- 6 -
`
`Application Serial No. 11/898,833
`Attorney Docket No. 0756-8108
`
`16.
`
`(Original) The method of manufacturing a display device including a thin film
`
`transistor according to claim 9 wherein said channel
`
`forming region comprises
`
`microcrystalline silicon.
`
`17.
`
`(Currently Amended) A method of manufacturing a display device including
`
`a thin film transistor, the method comprising the steps of:
`
`forming a gate electrode over a glass substrate;
`
`forming a gate insulating film comprising silicon nitride on said gate electrode;
`forming a first semiconductor film comprising amorphous silicon over said gate
`
`electrode with said gate insulating film interposed therebetween;
`forming an N-type semiconductor film on said first semiconductor film;
`
`patterning said first and N-type semiconductor films using a first photomask;
`
`forming a conductive layer on at least the patterned N-type semiconductor film;
`
`etching a portion of said conductive layer to form source and drain electrodes
`
`by dry etching using a resist formed by a second photomask;
`etching a portion of the patterned N-type semiconductor film to form source and
`drain regions using said resist wherein a channel forming region is formed in said first
`
`semiconductor film between said source and drain regions;
`
`forming a passivation film over said glass substrate to cover at least said source
`
`and drain electrodes and said channel forming region after removing said resist; and
`
`forming a pixel electrode over said passivation film wherein said pixel electrode is
`
`electrically connected to said source electrode or said drain electrodeJ.
`wherein an upper portion of each of said source and drain regions extend
`
`beyond a lower portion of each of said source and drain electrodes so that a distance
`
`between the source and drain regions is shorter than a distance between the source
`
`and drain electrodes.
`
`Exhibit 1013, page 8
`
`
`
`- 7 -
`
`Application Serial No. 11/898,833
`Attorney Docket No. 0756-8108
`
`18.
`
`(Original) The method of manufacturing a display device including a thin film
`
`transistor according to claim 17 wherein said channel forming region comprises intrinsic
`
`amorphous silicon.
`
`19. (Original) The method of manufacturing a display device including a thin film
`
`transistor according to claim 17 wherein said passivation film is formed so as to cover a
`
`portion of said glass substrate where said thin film transistor is not formed.
`
`20.
`
`(Currently Amended) A method of manufacturing a semiconductor displ'ay
`
`device comprising the steps of:
`
`forming a gate electrode over a glass substrate;
`
`forming a gate insulating film comprising silicon nitride on said gate electrode;
`
`forming a first semiconductor film over said gate electrode with said gate
`
`insulating film interposed therebetween;
`
`forming an N-type semiconductor film on said first semiconductor film;
`
`patterning said first and N-type semiconductor films using a first photomask;
`
`forming a conductive layer on at least the patterned N-type semiconductor film;
`
`etching a portion of said conductive layer to form source and drain electrodes
`
`using a resist formed by a second photomask;
`
`etching a portion of the patterned N-type semiconductor film to form source and
`
`drain regions by dry etching without removing said resist wherein a channel forming
`
`region is formed in said first semiconductor film between said source and drain regions;
`
`and
`
`forming a passivation film over said glass substrate to cover at least said source
`
`and drain electrodes and said channel forming region after removing said resist; and
`
`forming a pixel electrode over said passivation film wherein said pixel electrode is
`
`electrically connected to said source electrode or said drain electrodeJ.
`
`Exhibit 1013, page 9
`
`
`
`- 8 -
`
`Application Serial No. 11/898,833
`Attorney Docket No. 0756-8108
`
`wherein each of the source and drain regions has a bottom surface in contact
`with the first semiconductor film. each of the source and drain electrodes has a bottom
`surface in contact with corresponding one of the source and drain regions. and a
`distance between opposed ends of
`the bottom surfaces of the source and drain
`electrodes is larger than a distance between opposed ends of the bottom surfaces of
`
`the source and drain regions.
`
`(Original) The method of manufacturing a display device including a thin film
`21.
`transistor according to claim 20 wherein said channel forming region comprises intrinsic
`
`amorphous silicon.
`
`(Original) The method of manufacturing a display device including a thin film
`22.
`transistor according to claim 20 wherein said channel
`forming region comprises
`
`microcrystalline silicon.
`
`(Currently Amended) A method of manufacturing a display device including
`23.
`a thin film transistor over a glass substrate, the method comprising steps of:
`forming a resist on a conductive layer wherein said conductive layer is formed on
`an N-type semiconductor film, said N-type semiconductor film is formed on a first
`semiconductor film, and said first semiconductor film is formed over a gate electrode
`with a gate insulating film comprising silicon nitride interposed therebetween;
`
`etching a portion of said conductive layer to form source and drain electrodes
`using said resist;
`etching a portion of said N-type semiconductor film to form source and drain
`regions without removing said resist wherein a channel forming region is formed in said
`
`first semiconductor film between said source and drain regions; and
`forming a passivation film over said glass substrate to Gover at least said source
`and drain electrodes and said channel forming region after removing said resistJ,
`
`Exhibit 1013, page 10
`
`
`
`- 9 -
`
`Application Serial No. 11/898,833
`Attorney Docket No. 0756-8108
`
`wherein each of the source and drain regions has a bottom surface in contact
`with the first semiconductor film, each of the source and drain electrodes has a bottom
`surface in contact with corresponding one of the source and drain regions, and the
`
`conductive layer is overetched using said resist so that a distance between opposed
`ends of the bottom surfaces of the source and drain electrodes is larger than a distance
`
`between opposed ends of the bottom surfaces of the source and drain regions.
`
`(Original) The method of manufacturing a display device including a thin film
`24.
`transistor according to claim 23 wherein said channel forming region comprises intrinsic
`amorphous silicon.
`
`(Original) The method of manufacturing a display device including a thin film
`25.
`transistor according to claim 23 wherein said channel
`forming region comprises
`. microcrystalline silicon.
`
`(Original) The method of manufacturing a display device including a thin film
`26.
`transistor according to claim 23 wherein said conductive layer is formed over at least a
`portion of said glass substrate where said N-type semiconductor film is not formed.
`
`(Currently Amended) A method of manufacturing a display device including
`27.
`a thin film transistor over a glass substrate, the method comprising steps of:
`forming a resist on a conductive layer wherein said conductive layer is formed on
`an N-type semiconductor film, said N-type semiconductor film is formed on a first
`semiconductor film comprising amorphous silicon, and said first semiconductor film is
`formed over a gate electrode with a gate insulating film comprising silicon nitride
`interposed therebetween;
`etching a portion of said conductive layer to form source and drain electrodes
`using said resist;
`
`Exhibit 1013, page 11
`
`
`
`- 10-
`
`Application Serial No. 11/898,833
`Attorney Docket No. 0756-8108
`
`etching a portion of said N-type semiconductor film to form source and drain
`
`regions using said resist wherein a channel
`
`forming region is formed in said first
`
`semiconductor film between said source and drain regions; and
`forming a passivation film over said glass substrate to cover at least said source
`
`and drain electrodes and said channel forming region after removing said resist
`wherein each of the source and drain regions has a bottom surface in contact
`
`with the first semiconductor film, each of the source and drain electrodes has a bottom
`
`surface in contact with corresponding one of the source and drain regions. and the
`
`conductive layer is overetched using said resist so that a distance between opposed
`
`ends of the bottom surfaces of the source and drain electrodes is larger than a distance
`
`between opposed ends of the bottom surfaces of the source and drain regions.
`
`28.
`
`(Original) The method of manufacturing a display device including a thin film
`
`transistor according to claim 27 wherein said channel forming region comprises intrinsic
`
`amorphous silicon.
`
`29.
`
`(Original) The method of manufacturing a display device including a thin film
`
`transistor according to claim 27 wherein said passivation film is formed so as to cover a
`
`portion of said glass substrate where said thin film transistor is not formed,
`
`30.
`
`(Original) The method of manufacturing a display device including a thin film
`
`transistor according to claim 27 wherein said conductive layer is formed over at least a
`portion of said glass substrate where said N-type semiconductor film is not formed.
`
`31.
`
`(Currently Amended) A method of manufacturing a display device including
`
`a thin film transistor over a glass substrate, the method comprising steps of:
`
`forming a resist on a conductive layer wherein said conductive layer is formed on
`
`an N-type semiconductor film, said N-type semiconductor film is formed on a first
`
`Exhibit 1013, page 12
`
`
`
`- 11 -
`
`Application Serial No. 11/898,833
`Attorney Docket No. 0756-8108
`
`semiconductor film comprising amorphous silicon, and said first semiconductor film is
`
`formed over a gate electrode with a gate insulating film comprising silicon nitride
`
`interposed therebetween;
`etching a portion of said conductive layer to form source and drain electrodes
`
`using said resist;
`etching a portion of said N-type semiconductor film by dry etching to form source
`
`and drain regions without removing said resist wherein a channel
`
`forming region is
`
`formed in said first semiconductor film between said source and drain regions; and
`
`forming a passivation film over said glass substrate to Gover at least said source
`
`and drain electrodes and said channel forming region after removing said resistJ.
`wherein an upper portion of each of said source and drain regions extend
`
`beyond a lower portion of each of said source and drain electrodes so that a distance
`
`between the source and drain regions is shorter than a distance between the source
`
`and drain electrodes.
`
`(Original) The method of manufacturing a display device including a thin film
`32.
`transistor according to claim 31 wherein said channel forming region comprises intrinsic
`
`amorphous silicon.
`
`33.
`
`(Original) The method of manufacturing a display device including a thin film
`
`transistor according to claim 31 wherein said passivation film is formed so as to cover a
`
`portion of said glass substrate where said thin film transistor is not formed.
`
`34.
`
`(Original) The method of manufacturing a display device including a thin film
`
`transistor according to claim 31 wherein said conductive layer is formed on said N-type
`
`semiconductor film so as to extend beyond a side edge of said N-type semiconductor
`
`film to contact an insulating surface over said glass substrate.
`
`Exhibit 1013, page 13
`
`
`
`- 12 -
`
`Application Serial No. 11/898,833
`Attorney Docket No. 0756-8108
`
`35.
`
`(Currently Amended) A method of manufacturing a display device including
`
`a thin film transistor over a glass substrate, the method comprising steps of:
`
`forming a resist on a conductive layer wherein said conductive layer is formed on
`
`an N-type semiconductor film, said N-type semiconductor film is formed on a first
`semiconductor film comprising amorphous silicon, and said first semiconductor film is
`
`formed over a gate electrode with a gate insulating film comprising silicon nitride
`
`interposed therebetween;
`
`etching a portion of said conductive layer to form source and drain electrodes
`
`using said resist;
`
`etching a portion of said N-type semiconductor film by dry etching to form source
`and drain regions using said resist wherein a channel forming region is formed in said
`
`first semiconductor film between said source and drain regions; and
`
`forming a passivation film over said glass substrate to Gover at least said source
`
`and drain electrodes and said channel forming region after removing said resist...
`
`wherein an upper portion of each of said source and drain regions extend
`
`beyond a lower portion of each of said source and drain electrodes so that a distance
`
`between the source and drain regions is shorter than a distance between the source
`
`and drain electrodes.
`
`36.
`
`(Original) The method of manufacturing a display device including a thin film
`
`transistor according to claim 35 wherein said channel forming region comprises intrinsic
`
`amorphous silicon.
`
`(Original) The method of manufacturing a display device including a thin film
`37.
`transistor according to claim 35 wherein said passivation film is formed so as to cover a
`
`portion of said glass substrate where said thin film transistor is not formed.
`
`Exhibit 1013, page 14
`
`
`
`- 13 -
`
`Application Serial No. 11/898,833
`Attorney Docket No. 0756-8108
`
`38.
`
`(Original) The method of manufacturing a display device including a thin film
`
`transistor according to claim 35 wherein said conductive layer is formed on said N-type
`
`semiconductor film so as to extend beyond a side edge of said N-type semiconductor
`
`film to contact an insulating surface over said glass substrate.
`
`39.
`
`(Currently Amended) A method of manufacturing a display device including
`
`a thin film transistor over a glass substrate, the method comprising steps of:
`
`forming a resist on a conductive layer wherein said conductive layer is formed on
`
`an N-type semiconductor film, said N-type semiconductor film is formed on a first
`
`semiconductor film, and said first semiconductor film is formed over a gate electrode
`
`with a gate insulating film comprising silicon nitride interposed therebetween;
`
`etching a portion of said conductive layer to form source and drain electrodes
`using said resist;
`
`etching a portion of said N-type semiconductor film to form source and drain
`regions without removing said resist wherein a channel forming region is formed in said
`
`first semiconductor film between said source and drain regions; and
`forming a passivation film over said glass substrate to cover at least said source
`
`and drain electrodes, said channel forming region, a part of a surface of said source
`
`region not covered by said source electrode and a part of a surface of said drain region
`
`not covered by said drain electrodeJ,
`wherein a first portion of each of the source and drain regions extend beyond a
`
`lower portion of each of the source and drain electrodes so that a distance between the
`
`source and drain regions is shorter than a distance between the source and drain
`
`electrodes, and a thickness of the source and drain regions in at least a part of the first
`portion is substantially the same as a thickness of at least a part of a second portion of
`
`each of the source and drain regions covered by the source and drain electrodes.
`
`Exhibit 1013, page 15
`
`
`
`- 14 -
`
`Application Serial No. 11/898,833
`Attorney Docket No. 0756-8108
`
`40.
`
`(Original) The method of manufacturing a display device including a thin film
`
`transistor according to claim 39 wherein said channel forming region comprises intrinsic
`amorphous silicon.
`
`(Original) The method of manufacturing a display device including a thin film
`41.
`transistor according to claim 39 wherein said channel
`forming region comprises
`microcrystalline silicon.
`
`(Original) The method of manufacturing a display device including a thin film
`42.
`transistor according to claim 39 wherein said conductive layer is formed on said N-type
`semiconductor film so as to extend beyond a side edge of said N-type semiconductor
`film to contact an insulating surface over said glass substrate.
`
`(Currently Amended) A method of manufacturing a display device including
`43.
`a thin film transistor over a glass substrate, the method comprising steps of:
`
`forming a resist on a conductive layer wherein said conductive layer is formed on
`an N-type semiconductor film, said N-type semiconductor film is formed on a first
`
`semiconductor film, and said first semiconductor film is formed over a gate electrode
`with a gate insulating film comprising silicon nitride interposed therebetween;
`etching a portion of said conductive layer to form source and drain electrodes
`using said resist;
`
`etching a portion of said N-type semiconductor film to form source and drain
`regions using said resist wherein a channel
`forming region is formed in said first
`semiconductor film between said source and drain regions; and
`forming a passivation film over said glass substrate to cover at least said source
`and drain electrodes, said channel forming region, a part of a surface of said source
`region not covered by said source electrode and a part of a surface of said drain region
`
`not covered by said drain electrode....
`
`Exhibit 1013, page 16
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`- 15 -
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`Application Serial No. 11/898,833
`Attorney Docket No. 0756-8108
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`wherein a first portion of each of the source and drain regions extend beyond a
`
`lower portion of each of the source and drain electrodes so that a distance between the
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`source and drain regions is shorter than a distance between the source and drain
`
`electrodes, and a thickness of the source and drain regions in at least a part of the first
`
`portion is substantially the same as a thickness of at least a part of a second portion of
`
`each of the source and drain regions covered by the source and drain electrodes.
`
`44.
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`(Original) The method of manufacturing a display device including a thin film
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`transistor according to claim 43 wherein said channel forming region comprises intrinsic
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`amorphous silicon.
`
`45.
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`(Original) The method of manufacturing a display device including a thin film
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`transistor according to claim 43 wherein said channel
`
`forming region comprises
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`microcrystalline silicon.
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`46.
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`(Original) The method of manufacturing a display device including a thin film
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`transistor according to claim 43 wherein said conductive layer is formed over at least a
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`portion of said glass substrate where said N-type semiconductor film is not formed.
`
`47.
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`(New) The method of manufacturing a display device including a thin film
`
`transistor according to claim 1 wherein the passivation film is in direct contact with a
`
`surface of the channel forming region.
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`48.
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`(New) The method of manufacturing a display device including a thin film
`
`transistor according to claim 9 wherein the passivation film is in direct contact with a
`
`surface of the channel forming region.
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`Exhibit 1013, page 17
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`- 16 -
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`Application Serial No. 11/898,833
`Attorney Docket No. 0756-8108
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`49.
`
`(New) The method of manufacturing a display device including a thin film
`
`transistor according to claim 39 wherein the passivation film is in direct contact with a
`surface of the channel forming region.
`
`(New) The method of manufacturing a display device including a thin film
`50.
`transistor according to claim 43 wherein the passivation film is in direct contact with a
`surface of the channel forming region.
`
`(New) The method of manufacturing a display device including a thin film
`51.
`transistor according to claim 9 wherein an upper surface of at least a part of the upper
`portion of each of the source and drain regions is substantially parallel with an upper
`surface of the first semiconductor layer.
`
`(New) The method of manufacturing a display device including a thin film
`52.
`transistor according to claim 17 wherein an upper surface of at least a part of the upper
`portion of each of the source and drain regions is substantially parallel with an upper
`surface of the first semiconductor layer.
`
`(New) The method of manufacturing a display device including a thin film
`53.
`transistor according to claim 31 wherein an upper surface of at least a part of the upper
`portion of each of the source and drain regions is substantially parallel with an upper
`
`surface of the first semiconductor layer.
`
`(New) The method of manufacturing a display device including a thin film
`54.
`transistor according to claim 35 wherein an upper surface of at least a part of the upper
`portion of each of the source and drain regions is sUbstantially parallel with an upper
`surface of the first semiconductor layer.
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`Exhibit 1013, page 18
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`Application Serial No. 11/898,833
`Attorney Docket No. 0756-8108
`
`REMARKS
`
`The Official Action mailed November 6, 2009, has been received and its contents
`carefully noted. This response is filed within three months of the mailing date of the
`
`Official Action and therefore is believed to be timely without extension of time. Due to
`inclement weather, the Patent Office was officially closed on at least February 8-11,
`2010, thus, under the provisions outlined in MPEP § 510 and 37 C.F.R. § 1.9(h), the
`time period for response without an extension of time is extended to the day of the
`reopening of the Patent Office. Since the present response is filed on or before the
`reopening of the Patent Office, the Applicant respectfully submits that this response is
`being timely filed.
`the Information
`The Applicant notes with appreciation the consideration of
`Disclosure Statements filed on April 2, 2008; June 3, 2008; August 20, 2008; and
`September 30,2009.
`to the above
`Claims 1-46 were pending in the present application prior
`amendment. Claims 1, 9, 17, 20, 23, 27, 31, 35, 39 and 43 hav