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`Exhibit 1009, page 1
`
`1r
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`Exhibit 1009, page 1
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`

`

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`
`Library of Congress Cataloging-in—Publication Data
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`'
`Van Zant, Peter.
`Microchip fabrication : a practical guide to semiconductor
`processing / by Peter Van Zant. — 2nd ed.
`p.
`cm.
`ISBN 0-07—067194-X
`1. Semiconductors—Design and construction.
`TK7871.85.V36
`1990
`621.381’52—d020
`
`I. Title.
`
`89-36002
`CIP
`
`Copyright © 1990 by McGraw-Hill, Inc. Printed in the United
`States of America. Except as permitted under the United States
`Copyright Act of 1976, no part of this publication may be reproduced
`or distributed in any form or by any means, or stored in a data base
`or retrieval system, without the prior written permission of the
`publishers.
`
`34567890 DOCDOC 95432
`
`ISBN D-D?-Ub?l=l'-l-X
`
`The sponsoring editor for this book was Daniel A. Gonneau, the
`editing supervisor was David E. Fogarty, the designer was Naomi
`Auerbach, and the production supervisor was Suzanne W. Babeuf. This
`book was set in Century Schoolbook. It was composed by the McGraw-
`Hill Professional and Reference Division composition unit.
`
`Printed and bound by R. R. Donnelley & Sons Company.
`
`
`Information contained in this work has been obtained by McGraW-
`Hill, Inc., from sources believed to be reliable. However, neither
`McGraw-Hill nor its authors guarantees the accuracy or complete-
`ness of any information published herein and neither McGraw-
`Hill nor its authors shall be responsible for any errors, omissions,
`or damages arising out of use of this information. This work is
`published with the understanding that McGraw-Hill and its au-
`thors are supplying information but are not attempting to render |
`engineering or other professional services. If such services are
`required, the assistance of an appropriate professional should be
`sought.
`
`
`
`For more information about other McGraw-Hill materials,
`call 1-800-2-MCGRAW in the United States. In other
`countries, call your nearest McGraw-Hill office.
`
`
`
`Exhibit 1009, page 2
`
`Exhibit 1009, page 2
`
`

`

`Photolithography—Developing to Final Inspection
`
`221
`
`
`
`tholes
`
`Bridglng
`
`IncompleteDevelop
`
`NoReSIst
`
`c
`.9.4
`«5
`
`EEm
`
`._.
`
`CoO
`
`
`
`_‘
`‘
`Bridge
`At Develop Inspect
`
`After Etch
`
`Figure 9.14 Bridged conduction lines.
`
`from an overexposure, poor mask definition, or a resist film that is too
`thick.
`
`Etch
`
`l
`
`l
`
`‘
`
`
`
`
`At the completion of the develop inspect step, the mask (or reticle) pat-
`tern is defined in the photoresist layer and is ready for etch. During
`the etch step the image will be permanently transferred into the sur-
`. face layer on the wafer. The goal is an exact transfer of the image into
`the resist layer. The degree of exactness is dependent on several fac-
`tors which will be explored as a preparation for discussion of the dif—
`
`I
`
`1
`
`‘
`
`l
`
`1;
`
`‘ll
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`Exhibit 1009, page 3
`
`Exhibit 1009, page 3
`
`

`

`
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`222
`
`Chapter Nine
`
`Resist
`Layer
`
`Wafer
`
`I
`
`_
`
`_-
`
`—:
`
`_
`
`Figure 9.15
`
`Incomplete etch.
`
`ferent etch methods. The factors affecting image transfer are incom-
`plete etch, overetching, undercutting, and selectivity.
`
`Incomplete etch
`
`Incomplete etch is a situation in which a portion of the surface layer
`still remains in the pattern hole or on the surface (Fig. 9.15). The
`causes of incomplete etch are too short an etch time, the presence of a
`surface layer that slows the etching, or an uneven surface layer that
`results in incomplete etch in the more thickly coated portions of the
`wafer. If wet-chemical etching is used, a lowered temperature or weak
`etch solution will cause incomplete etch. If dry plasma etching is used,
`a wrong gas mixture or an improperly operated system can cause the
`same effect.
`
`Overetch and undercutting
`
`The opposite condition to incomplete etch is overetch. In any etch pro-
`cess there is always some degree of overetch planned into the process.
`This is necessary to ensure complete removal of the thickest portions
`of the the layer and to allow for the etch to break through any slow-
`etching layers on the top surface.
`The ideal etch leaves vertical sidewalls in the layer (Fig. 9.16). Etch
`techniques that produce this ideal result are said to be anisotropic.
`However, the etching chemical dissolves the top of the sidewall for a
`longer time than the bottom of the hole. The result is a hole wider at
`the top than the bottom with a sloped sidewall. Etching techniques
`that produce this result are called isotropic. This action of the etching
`chemical is called undercutting (Fig. 9.17) since the surface layer is
`undercut below the resist edge. Circuit layout designers take under-
`cutting into account when planning the circuit. Adjacent patterns
`must be separated a certain distance to prevent shorting. The amount
`of undercutting must be calculated when the pattern is designed.
`An ongoing goal of the etch step is the control of undercutting to an
`acceptable level. Severe undercutting (or overetch) takes place when
`the etch time is excessive, the etch temperature is too high, or the etch
`mixture is too strong. Undercutting is also present when the adhesion
`bond between the photoresist and the wafer surface is weak. This is a
`constant worry, and the purpose of the dehydration, prime, soft bake,
`
`
`
`
`
`
`
`Exhibit 1009, page 4
`
`Exhibit 1009, page 4
`
`

`

`Photolithography—Developing to Final Inspection
`
`223
`
`iim
`Normal
`
`EOver Etch
`
`;
`[
`
`‘
`Resist
`
`Layer
`
`Wafer
`
`Anisotropic Etch
`
`Isotropic Etch
`
`Figure 9.16 Anisotropic and isotropic
`etch.
`
`Over Etch and Resist Lining
`
`9.17 Degrees of
`Figure
`undercutting.
`
`W
`
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`
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`11“ I
`i
`i
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`ill ‘
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`
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`i
`'
`
`and hard bake steps is to prevent this type of failure. Failure of the
`resist bond at the edge of the etch hole can result in severe undercut—
`ting. Ifthe bond is very poor, the resist can lift from the wafer surface,
`
`causing catastrophic undercutting.
`
`Selectivity
`
`Another goal of the etch step is the preservation of the surface under—
`lying the etched layer. If the underlying surface of the wafer is par-
`tially etched away, the physical dimensions and electrical perfor-
`mance of the devices are changed. The property of the etch process
`that relates to preservation of the surface is selectivity. High selectiv-
`ity implies little or no attack of the underlying surface. In wet etching
`techniques an etchant acid that will not attack the underlying mate-
`rial is chosen.
`
`‘
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`
`Wet Etching
`
`For over 30 years the traditional method of etching has been by im-
`
`mersion techniques using wet etchants. The procedure is similar to
`the preoxidation clean-rinse-dry process (Chap. 7) and immersion de-
`velopment. The emergence of feature sizes less than 3 mm has seen the
`shift from wet to dry etching techniques. However, keep in mind that
`within a circuit whose smallest dimensions are 3 pm or less, there are
`still mask levels with dimensions well above that level. In many cases
`dry etching is employed for small dimensions and wet etching for the
`larger ones.
`For wet etching, the wafers are loaded into an etch—resistant boat and
`immersed in a tank of the etchant. After a predetermined time in the
`etch tank they are processed through the rinsing and drying steps.
`
`
`
`Exhibit 1009, page 5
`
`Exhibit 1009, page 5
`
`

`

`
`
`224
`
`Chapter Nine
`
`Etching uniformity and process control are enhanced by the addition
`of heaters and agitation devices, such as stirrers or ultrasonic waves,
`to the immersion tanks.
`
`is simple in concept, a high-
`Although the basic equipment
`production wet “bench” can be very sophisticated,9 incorporating
`microprocessor control of the timers and heaters. Many systems
`have walking beams or robots for the automatic placement of the
`wafer holders in the etch, rinse, and dry subsystems. The etch tanks
`of the traditional manual systems are filled by hand, a dangerous
`and possibly contaminating practice. Newer systems have plumb-
`ing to allow the filling of the tanks from reserve tanks by remote
`control.
`
`The worry about etchant contamination of the wafers is being ad-
`dressed by point—of-use filters. These are special filters fitted to auto-
`matic chemical dispensing systems to filter-clean the chemicals just
`prior to filling the immersion tank. This placement catches particu-
`late contamination from the chemicals, the pumps, and the tubing sys-
`tems.
`
`Wet etchants are selected for their ability to uniformly remove the
`top wafer layer without attacking the underlying material (good se-
`lectivity).
`Etch time variability is introduced by temperature variations as the
`boat and wafers come to temperature equilibrium in the tank and the
`continued etching action as the wafers are transferred to a rinse tank.
`Generally, the process is set at the shortest time compatible with uni-
`form etching and high productivity. The maximum time is limited to
`the amount of time the resist will continue to adhere to the wafer sur-
`face.
`
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`Some devices require the etching of a trough or trench into the sil—
`
`icon surface. The etch formula is adjusted to make the etch rate de-
`
`pendent on the orientation of the wafer. (111)-oriented wafers etch at
`
`a 45° angle, while (100)-0riented wafers etch with a “flat” bottom.3
`
`
`Silicon wet etching
`
`Silicon layers are typically etched with a solution of nitric and HF ac-
`ids mixed in water. The formula becomes an important factor in con-
`trol of the etch. In some ratios, the etch has an exothermic reaction
`with the silicon. Exothermic reactions are those that produce heat,
`which, in turn, speeds up the etch reaction, which, in turn, creates
`more heat, and so on, resulting in an uncontrollable process. Some—
`times acetic acid is mixed in with the other ingredients to control the
`exothermic reaction.
`
`Exhibit 1009, page 6
`
`Exhibit 1009, page 6
`
`

`

`
`
`
`
`Photolithography—Developing to Final inspection
`
`225
`
`Other orientations result in different-shaped trenches'lrolysilicon
`films are also etched with the same basic formula.
`
`Silicon dioxide wet etching
`
`The most common etched layer is a thermally grown silicon dioxide.
`The basic etchant is hydrofluoric acid (HF). HF has the advantage of
`dissolving silicon dioxide without attacking silicon. However,
`full—
`strength HF has an etch rate of about 300 A/s at room temperature.4
`This rate is too fast for a controllable process (a 3000-13; layer would
`etch in only 10 s).
`In practice, the HF (assay of 49%) is mixed with water or ammo-
`nium fluoride and water. The ammonium fluoride (NH4F) acts as a
`buffer to the unwanted generation of hydrogen ions which accelerate
`the etch rate. These solutions are known as buffered oxide etches or
`BOEs. They are mixed in different strengths to create reasonable etch
`times for the particular oxide thickness (Fig. 9.18). Some BOE formu-
`las include a wetting agent (surfactant such as Triton X—100 or equiv-
`alent) to reduce the surface tension of the etch, allowing it to uni4
`formly penetrate into smaller openings.
`
`Aluminum film wet etching
`
`Selective etching solutions for aluminum and aluminum alloy layers
`are based on phosphoric acid. An unfortunate by-product of the reac-
`tion of aluminum and phosphoric acid are tiny bubbles of hydrogen, as
`
`1200
`
`400'. —L . —l_ _._ temperature for BOEs.
`15
`20
`25
`so
`Temperature, °C
`
`
`
`Etchrate,A/mm
`
`goo . Figure 9.18 Etch rate versus
`Exhibit 1009, page 7
`
`Exhibit 1009, page 7
`
`

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`226
`
`Chapter Nine
`
`shown in the reaction in Fig. 9.19. These bubbles cling to the wafer
`surface and block the etch action. The result is either bridges of alu-
`minum that can cause electrical shorts between adjacent leads or
`spots of unwanted aluminum, called snowballs, left on the surface.
`Neutralization of this problem is accomplished by use of an aluminum
`etching solution that contains phosphoric acid, nitric acid, acetic acid,
`water, and wetting agents. A typical solution of the active ingredients
`(less wetting agent) is 16:1:1:2.
`In addition to the special formulas, a typical‘aluminum etch process
`will include wafer agitation by stirring or moving the wafer boat up
`and down in the solution. Sometimes ultrasonic or megasonic waves
`are used to collapse and move the bubbles around.
`
`Deposited oxide wet etching
`
`One of the final layers on a wafer is a silicon dioxide passivation film
`deposited over the aluminum metallization pattern. These films are
`known as vapox or silox films. While the chemical composition of the
`films is that of silicon dioxide, the same as thermally grown silicon
`dioxide, they require a different etch solution. The difference is in the
`selectivity required of the etchant.
`The usual etchant for silicon dioxide is a BOE solution. Unfortu-
`
`nately, the BOE attacks the underlying aluminum pads, causing
`bonding problems in the packaging process. This condition is called
`brown, or stained, pads. The preferred etchant for this layer is a solu-
`tion of ammonium fluoride and acetic acid mixed in a ratio of 1:2.
`
`Silicon nitride wet etching
`
`Another compound favored for the passivation layer is silicon nitride.
`It is possible to etch this layer with wet chemical means, but it is not
`as easy as for the other layers. The chemical used is hot (180°C) phos—
`
`
`
`Brldge
`
`Snowball
`
`Figure 9.19 Hydrogen bubble
`blockage of etchant.
`
`
`
`
`
`Hydrogen Bubble
`
`
`Exhibit 1009, page 8
`
`Exhibit 1009, page 8
`
`

`

`
`
`Photolithography—Developing to Final Inspection
`
`227
`
`COMMON
`ETCHANT
`HF & NHiF
`(1 : 8)
`HF & NHJF
`(1 : 8)
`Acetic Acid
`& NH4F(2 : 1)
`HVPO-i
`' 16
`HNO‘
`1
`Acetic
`1
`H20 2 2
`Wetting Agent
`HKPOJ
`‘
`HNOJ I 50
`H20 2 20
`
`SiO:
`
`SiO:
`
`SiO:
`(Vapox)
`Aluminum
`
`SiiNi
`POLYSi
`
`ETCH
`TEMP
`Room
`
`Room
`
`Room
`
`RATE
`3 [MIN
`700
`
`700
`
`1000
`
`METHOD
`Dip & wetting agent predip
`
`Dip & wetting agent predip
`
`Dip
`
`40 — 50°C
`
`2000
`
`a) Dip & agitation
`b) Spray
`
`150 — 180°C 80
`Room
`1000
`
`HF I 3
`
`
`
`Figure 9.20 Summary of wet etching process.
`
`phoric acid. Since the acid evaporates rapidly at this temperature, the
`etch must be done in a closed reflux container equipped with a cooled
`lid to condense the vapors. The major problem is that photoresist lay-
`ers do not stand up to the etchant temperature and aggressive etch
`rate. Consequently, a layer of silicon dioxide or some other material is
`required to block the etchant. These two factors have led to the use of
`dry etching techniques for silicon nitride.
`
`Wet spray etching
`
`Wet spray etching offers several advantages over immersion etch-
`ing. Primary is the added definition gained from the mechanical
`pressure of the spray.5 Spray etching also minimizes contamination
`from the etchants. From a process control point of view, spray etch
`is more controllable since the etchant can be instantly removed
`from the surface by switching the system to a water rinse. Single-
`wafer spinning-chuck spray systems offer considerable process uni-
`formity advantages.
`Disadvantages to spray etching are system cost, safety consider-
`ations associated with caustic etchants in a pressurized system, and
`the requirement of etch-resistant materials to prevent the deteriora-
`tion of the machine. On the plus side, spray systems are usually en—
`closed, which adds to worker safety. Figure 9.20 is a table of common
`semiconductor films and their common etchants.
`
`Dry EtCh
`
`The limits of wet etching for VLSI-size patterns has been mentioned
`in the previous section. For review they are
`
`
`
`Exhibit 1009, page 9
`
`Exhibit 1009, page 9
`
`

`

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`2' ”
`,.
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`
`228
`
`Chapter Nine
`
`Wet etching is limited to pattern sizes of 3 um.
`
`Wet etching is isotropic, resulting in sloped sidewalls.
`
`QPPP?‘ Wet processes represent a contamination potential.
`
`A wet etch process requires rinse and dry steps.
`The wet chemicals are hazardous and/0r toxic.
`
`6. Failure of the resist-wafer bond causes undercutting.
`
`These considerations have led to the use of dry etch processes for the
`definition of small feature sizes on advanced circuits. Figure 9.21 is an
`overview of the dry etching techniques used.
`Dry etching is a generic term that refers to the etching techniques in
`which gases are the primary etch medium, and the wafers are etched
`without wet chemicals or rinsing. The wafers enter and exit the sys—
`tem in a dry state.
`
`Barrel plasma etching
`
`The term dry etching is sometimes used to refer to plasma etching,
`although there are two other dry etching techniques—ion milling and
`reactive ion etch. Plasma etching, like wet etching, is a chemical pro-
`cess but uses plasma energy to drive the reaction. Comparison of sili-
`con dioxide etching in the two systems illustrates the differences. In
`wet etching of silicon dioxide, the fluorine in the BOE etchant is the
`ingredient that dissolves the silicon dioxide, converting it to water-
`rinsable components. The energy required to drive the reaction comes
`from the internal energy in the BOE solution or from an external
`heater.
`A plasma etcher requires the same elements: a chemical etchant
`and an energy source. Physically, a plasma etcher consists of a cham-
`ber, vacuum system, gas supply, and a power supply (Fig. 9.22). The
`wafers are loaded into the chamber and the pressure inside is reduced
`
`Etch
`
`Wet
`
`Imersion
`
`Spray
`
`Plasma
`
`Barrel
`
`Figure 9.21 Guide to etch methods.
`
`Dry
`
`Ion
`Milling
`
`Planar
`
`Reaction
`Ion Etch
`(R.l.E.)
`
`Exhibit 1009, page 10
`
`Exhibit 1009, page 10
`
`

`

`
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`”Nan... ...
`
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`298
`
`Chapter Twelve
`
`Transistor
`
`Diode
`
`Resistor
`
`Capacitor
`
`
`
`
`
`1. EPI aria CollectOr
`2. Isolation
`3. Surface Oxide
`
`4. Collector Contact
`5. Base
`6. Emitter
`
`7. Metaiization
`8. Passivation Layer
`9. Buried Layer
`
`Figure 12.1 Cross section of bipolar circuit showing epitaxial layer
`and isolation.
`
`ers are deposited layers that function in the devices as either semicon-
`ductors, insulators, dielectrics, or conductors. The growth is illus-
`trated by a comparison of an MOS transistor circa 1972 to its 1980s
`version (Fig. 12.2).
`Not surprisingly, the growth in the number and kind of deposited
`films has resulted in a number of new deposition techniques. Where
`the process engineer of the 1960s had a choice of only atmospheric
`chemical vapor deposition (CVD), today’s engineer has many more op-
`tions (Fig. 12.3). (Chapter 12 will detail the basics of film deposition,
`as well as the techniques used and the films deposited by these impor—
`tant processes. The uses of the particular films, while indicated in this
`chapter, are detailed in Chaps. 16 and 17.)
`
`Film Parameters
`
`The particular films incorporated into device structures are examined
`in “Low-Pressure Chemical Vapor Deposition,” p. 308. While each
`film material has a set of specific parameters, there are several gen-
`eral criteria that all films must meet for semiconductor use. Most of
`the criteria come about from the choice of source chemistries used and
`the system design and operating parameters.
`Thickness control is of paramount importance, especially as the
`films are getting thinner. Epitaxial films have shrunk from 5-um lev-
`els to submicron thicknesses. Surface flatness is as important as the
`thickness. In Chap. 10 the effect of steps and surface roughness on im-
`age formation was detailed. Deposited films must be flat and as
`smooth as the material will allow to minimize steps, cracking, and
`subsurface reflections.
`
`
`
`Exhibit 1009, page 11
`
`Exhibit 1009, page 11
`
`