United States Patent
`Kwasnick et aI.
`
`[19]
`
`[75]
`
`[54] THIN FILM TRANSISTOR STRUCfURE
`WITH IMPROVED SOURCE/DRAIN
`CONTACfS
`Inventors: Robert F. Kwasnick; George E.
`Possin, both of Schenectady, N.Y.;
`David E. Holden, Grenoble, France;
`Richard J. Saia, Schenectady, N.Y.
`[73] Assignee: General Electric Company,
`Schenectady, N.Y.
`[21] Appl. No.: 825,218
`Jan. 24, 1992
`[22] Filed:
`
`[63]
`
`[51]
`
`[52]
`
`[58]
`[56]
`
`Related U.S. Application Data
`Continuation of Ser. No. 593,419, Oct. 5, 1990, aban(cid:173)
`doned.
`Int. a.s .••.•••.•••••••...••• HOIL 27/01; HOlL 27/13;
`HOlL 29/78
`U.S. a
`257/766; 257/383;
`257/770; 257/57
`357/4,23.7,41,2
`
`Field of Search
`References Cited
`U.S. PATENT DOCUMENTS
`3/1987 Holmberg et al.
`4,651,185
`
`357/71
`
`FOREIGN PATENT DOCUMENTS
`60-183770 9/1985 Japan
`1-114080 5/1989 Japan
`
`357/23.7
`357/23.7
`
`OTHER PUBLICAnONS
`B. Gorowitz, R. J. Saia, E. W. Balch, "Methods of
`Metal Patterning and Etching for VLSI", General
`Electric Co., Technical Information Series Mar. 1987;
`see pp. 22-25, also published in VLSI Electronics Mi(cid:173)
`crostructure Science (N. Einspruch, S. Cohen, G. Gil(cid:173)
`denblat, Eds) vol. 15, chap. 4, p. 159 (1987).
`R. J. Saia, B. Gorowitz, "The Reactive Ion Etching of
`Molybdenum and Bilayer Metallization Systems, Con-
`
`10
`
`\
`
`111111111111111111111111111111111111111111111111111111111111111111111111111
`USOO5l98694A
`Patent Number:
`Date of Patent:
`
`[11]
`
`[45]
`
`5,198,694
`Mar. 30, 1993
`
`taining Molybdenum", Journal of the Electrochemical
`Society, vol. 135, pp. 2795-2802 (1988) (See p. 2797 for
`discussion of one step Mo-Cr etching).
`Y. Kwo, J. Crowe, "Slope Control of Molybdenum
`Lines Etched With Reactive Ion Etching", J. Vac. Sci
`Technical, pp. 1529-1532 (May/Jun. 1990) (See p. 1529
`for discussion of Mo etching).
`R. Kwasnick, G. Possin, R. Saia, "Reactive Ion Etched
`Mo/Cr Source-Drain Metallization For Amorphous
`Silicon Thin Film Transistors", Materials Res. Soc.
`Symposium Abstracts Apr. 1991.
`
`Primary Examiner-Andrew J. James
`Assistant Examiner-Donald L. Monin
`Attorney, Agent, or Firm-Donald S. Ingraham; Marvin
`Snyder
`
`[57]
`ABSTRACT
`Minimum line spacing is reduced and line spacing uni(cid:173)
`formity is increased in thin mm transistors by employ(cid:173)
`ing source/drain metallization having a first relatively
`thin layer of a first conductor and a second relatively
`thick layer of a second conductor. The second conduc(cid:173)
`tor is selected to be one which may be preferentially
`etched in the presence of the first conductor whereby
`the first conductor acts as an etch stop for the etchant
`used to pattern the second conductor portion of the
`source/drain metallization. This etching is preferably
`done using dry etching. Dry etching typically provides
`substantially better control of line width than wet etch(cid:173)
`ing. The etching of the second conductor can be done
`with a dry etch process which etches the photoresist at
`substantially the same rate as the second conductor
`whereby the second conductor is provided with a side(cid:173)
`wall slope of substantially 45' which improves the qual(cid:173)
`ity of passivation provided by subsequent deposition of
`a conformal passivating layer.
`
`8 Claims, 11 Drawing Sheets
`
`14
`
`16
`
`28
`
`12
`
`Exhibit 1008, page 1
`
`

`

`u.s. Patent
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`Mar. 30, 1993
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`
`Mar. 30, 1993
`Mar. 30, 1993
`
`Sheet 2 of 11
`Sheet 2 of 11
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`5,198,694
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`Mar. 30, 1993
`Mar. 30, 1993
`
`Sheet 3 of 11
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`Mar. 30,
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`Mar. 30, 1993
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`U.S. Patent
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`

`

`THIN FILM TRANSISTOR STRUcruRE WITH
`IMPROVED SOURCEIDRAIN CONTAcrs
`
`This application is a continuation of application Ser.
`No. 07/593,419, flled Oct. 5, 1990, now abandoned.
`
`BACKGROUND OF THE INVENTION
`Field of the Invention
`The present invention relates to the field of thin-film
`transistors and more particularly to the field of thin-fllm 35
`transistor metallization.
`
`1
`
`5,198,694
`
`RELATED APPLICAnONS
`The present application is related to application Ser.
`No. 07/593,425, flled Oct. 5, 1990, entitled "Device 10
`Self-Alignment by Propagation of a Reference Struc(cid:173)
`ture's Topography", by Coy Wei, et al.; application Ser.
`No. 07/593,423, flled Oct. 5, 1990, now abandoned
`entitled, "Positive Control of the SourcelDrain-Gate
`Overlap in Self-Aligned TFTs Via a Top Hat Gate 15
`Electrode Configuration", by Coy Wei, et al.; applica(cid:173)
`tion Ser. No. 07/593,421, ftled Oct. 5, 1990, now U.S.
`Pat. No. 5,132,745, entitled, "Thin Film Transistor Hav(cid:173)
`ing an Improved Gate Structure and Gate Coverage by
`the Gate Dielectric" by R. F. Kwasnick, et al.; applica- 20
`tion Ser. No. 07/510,767, fJ1ed Apr. 17, 1990, entitled
`"Method for Photolithographically Forming a Self(cid:173)
`Aligned Mask Using Back Side Exposure and a Non(cid:173)
`Specular Reflecting Layer", by G. E. Possin, et al.; and
`application Ser. No. 07/499,733, flled Mar. 21, 1990, 25
`entitled "Method for Fabricating a Self-Aligned Thin(cid:173)
`Film Transistor Utilizing Planarization and Back-Side
`Photoresist Exposure", by G. E. Possin, et aI., flled
`Mar. 21, 1990, each of which is incorporated herein by
`reference.
`
`2
`spacing is a reduction in the current provided by the
`transistor in response to a given set of gate and source(cid:173)
`to-drain voltages. This reduction in current can de·
`crease the speed of a liquid crystal display or increase
`5 the noise in an imaging device. Consequently, there is a
`need for improved thin-fllm transistor structures and
`methods of processing them which reduce, minimize or
`eliminate significant variations in the source-to-drain-
`electrode spacing of thin-fllm transistors across an array
`with a consequent reduction in variations in capacitance
`and current output. It is normal practice in the thin fllm
`transistor art to employ wet etchants to etch the sour(cid:173)
`ce/drain metallization because such wet etchants are
`available which are highly selective between the sour(cid:173)
`ce/drain metallization and the immediately underlying
`amorphous silicon which comprises the semiconductor
`material of the thin-fllm transistor. This use of wet etch·
`ants makes it possible to completely remove the sour-
`ce/drain metallization from the channel region of the
`transistor's semiconductor material without significant
`etching of the semiconductor material itself. Unfortu(cid:173)
`nately, use of wet etching limits the main source-to(cid:173)
`drain-electrode spacing due to linewidth loss from un·
`dercutting. Still worse, because the undercutting of the
`photoresist by the etchant is non-uniform and uncon·
`trollable, such spacings vary significantly from lot to lot
`and in different portions of the same array. A source/(cid:173)
`drain metallization structure which is photoresist de-
`30 fined with a three micron spacing can end up after com(cid:173)
`pletion of the wet etch with as much as a four five
`micron spacing. Still worse, this spacing typically varies
`across a given array.
`A layer of chromium or a layer of molybdenum is
`commonly used as the source/drain metallization for
`thin-film transistors because each of them makes good
`ohmic contact to n+ amorphous silicon. These metalli-
`BACKGROUND INFORMAnON
`zations are typically deposited by sputtering. A com·
`mon wet ~tchm:t for ~oly~enum is known. ~ PA'YN
`Amorphous silicon (a-Si) thin-film transistors (TFTs)
`are used in both display and imager applications. These 40 (phosphonc aCId, acetIc aCId, water and rutnte a~ld).
`field effect transistors (PETs) are primarily used in
`Such .wet etchant.s have the unf~rtunate charactens~lc
`array devices in which the electro-optically active por-
`for t?ID-f~m translstor~ of patternmg.molybdeD:um WIth
`tion of the devices comprises many individual pixels the
`vertIcal SIdewalls. As IS well known m the semlconduc-
`electro-optical state of which must be individually set
`tor art, vertical sidewalls make it substantially more
`or read in accordance with the display or imager nature 45 difficult to successfully passivate a structure with a
`of the device. As such, such TFTs are fabricated in
`deposited layer such as silicon dioxide or silicon nitride
`large quantities, in small sizes and in substantial densities
`as compared to the same structure with sloped side-
`on the substrates for such systems. For optimum system
`walls. Non-continuous passivation can cause damage to
`operation, everyone of the TFTs in the array should
`lower layers while etching subsequently deposited lay·
`have identical characteristics. While absolutely identi· SO ers of material.
`cal characteristics are probably unobtainable, there is
`A plasma or reactive ion etch (RIE) process can
`presently a substantial problem with excessive varia-
`provide the required uniform source/drain metal spac-
`tions in TFT characteristics across an entire array and
`ings since such processes can be anisotropic in nature.
`even more so across an entire wafer. In particular, be-
`In applications where a large area needs to be patterned,
`cause of processing variations, the thin-mm transistors 55 as in the case of an 8' X8" liquid crystal display, typical
`in one portion of an array may have significantly differ-
`RIE edge to center clearing, commonly referred to as
`ent characteristics than the thin-ftlm transistors in an-
`the "bull's eye effect", can result in excessive and non-
`other portion of the array. Such variations in character-
`uniform removal of the underlying material, which in
`istics unduly restrict the maximum operating character-
`this application is silicon. The "bull's eye effect" be·
`istics of the array (speed, signal to noise ratio, sensitivity 60 comes worse with increases in the thickness of the mate-
`and so forth). A parameter in which variation across a
`rial being etched, and with the size of the part being
`wafer is common is the spacing between the source and
`etched.
`drain electrodes of the TFTs. Such variations have a
`Due to the aforementioned problems, there is a need
`number of undesirable effects. A larger source-to-drain
`for: a) an improved thin fllm transistor structure and
`electrode spacing translates directly into a larger 65 fabrication process which provides the ability to pro-
`source-to-drain region spacing which in tum results in
`duce more uniform source/drain spacings across an
`reduced off-state capacitance for the thin film transistor.
`entire array or structure, b) the ability to produce
`Another effect of increased source-to-drain electrode
`smaller spaces between the source and drain electrodes
`
`Exhibit 1008, page 13
`
`

`

`5,198,694
`
`4
`underlying material can be lower than that which
`would be required if the first conductor were omitted
`since the uniformity of metal clearing is greater with
`thinner fUms and the time that the underlying material is
`exposed to the etching gas is shorter.
`Following etching of the first conductor, the fabrica(cid:173)
`tion of the thin mm transistor is completed in the nor(cid:173)
`mal fashion.
`The first conductor is preferably chromium, while
`the second conductor is preferably molybdenum. The
`etching gas for the second conductor (Mo) is preferably
`a mixture of SF6, Ch and 02 and the etching gas for the
`first conductor (Cr) is preferably a mixture of Ch and
`02.
`BRIEF DESCRIPTIONS OF THE DRAWINGS
`The subject matter which is regarded as the invention
`is particularly pointed out and distinctly claimed in the
`concluding portion of the speciflcation. The invention,
`however, both as to organization and method of prac(cid:173)
`tice,
`together with further objects and advantages
`thereof, may best be understood by reference to the
`following description taken in connection with the ac(cid:173)
`companying drawings in which:
`FIGS. 1-12 illustrate successive stages in the fabrica(cid:173)
`tion of a thin-mm transistor in accordance with the
`present invention.
`
`3
`in the vicinity of the channel region of a thin fUm tran(cid:173)
`sistor, c) an etching process which produces a source/(cid:173)
`drain metallization with a sloped sidewall prome so that
`subsequently deposited layers can more successfully
`passivate that structure and d) an etch process which 5
`patterns the source/drain metal without excessive and
`non-uniform removal of the underlying material.
`OBJECTS OF THE INVENTION
`Accordingly, a primary object of the present inven- 10
`tion is to provide a thin mm transistor structure which
`may be accurately and uniformly reproduced across an
`entire array or structure.
`Another object of the present invention is to provide
`a thin mm transistor fabrication process which results in 15
`closer control of source/drain region spacing.
`Another object of the present invention is to provide
`a thin mm transistor fabrication process which pro(cid:173)
`duces source/drain metallization having sloped side(cid:173)
`walls which facilitate high integrity conformal deposi- 20
`tion of overlying passivation layers.
`Another object of the present invention is to provide
`a thin mm transistor fabrication process which patterns
`the source/drain metallization without excessive and
`non-uniform removal of the underlying materials.
`
`25
`
`SUMMARY OF THE INVENTION
`The above and other objects which will become ap(cid:173)
`DETAILED DESCRIPTION
`parent from the specification as a whole including the
`FIG. 1 is a cross-section view of a substrate 12 on
`drawings, are accomplished in accordance with the 30
`which a plurality of thin-fUm transistors are to be fabri-
`present invention by providing a two layer source/-
`cated. A layer of gate metallization 18 is disposed across
`drain metallization structure in which a first relatively
`thin layer of a first conductor is disposed directly on the
`the entire upper surface of the illustrated portion of the
`substrate 12. This gate metallization preferably com-
`underlying amorphous silicon material and a second
`relatively thick layer of a second conductor which is 35 prises two separate sublayers 14 and 16, but may be a
`single layer of one conductor if desired. This gate metal-
`disposed directly on the first conductor with the second
`lization is then patterned in accordance with any of a
`conductor being one which can be preferentially etched
`in the presence of the first conductor.
`variety of known techniques to provide the structure
`In accordance with one method of fabricating such a
`illustrated in FIG. 2 where the gate metallization 18 is
`thin mm transistor, the thin mm transistor is fabricated 40 now restricted to those locations in which gate metalli-
`zation is required in the fmal structure. This patterning
`up to deposition of the source/drain metallization in a
`normal fashion. A first thin layer of a first conductor
`process may preferably be done photolithographically
`with photoresist and a wet or dry etchant in accordance
`which preferably makes good ohmic contact to the
`is deposited directly on the
`with a particular gate metallization employed and the
`semiconductor material
`semiconductor material. Thereafter, preferably without 45 practitioner's preferences. In accordance with related
`application Ser. No. 593,421, the gate metallization 18
`breaking vacuum in the deposition apparatus, a second
`thicker layer of a second conductor is deposited on the
`may preferably be a two-layer gate metallization of
`first conductor. A photoresist mask is then formed on
`molybdenum over chrome and may preferably be pat-
`top of the source/drain metallization with a pattern of
`terned by reactive ion etching to provide a sloped side-
`open areas which leaves the source/drain metallization SO wall on the gate metallization, as explained more fully in
`that application.
`exposed where it is desired to remove the source/drain
`metallization. The structure is then preferably dry
`Following patterning of the gate metallization 18, a
`gate dielectric layer 28 is deposited across the entire
`etched using reactive ion etching with an etchant gas
`which etches the second conductor much faster than it
`upper surface of the substrate and gate metal. Coverage
`etches the first conductor. The second conductor is 55 at the edges of the gate metal is improved by providing
`a sloped gate metallization in accordance with the
`overetched in the sense of the etching process being
`continued for a period oftime after it is determined that
`teachings of related application Ser. No. 07/593,421.
`the first conductor has been exposed in the openings in
`The gate dielectric is preferably 0.1 to 0.5 microns
`the mask. This overetching is to ensure the complete
`thick. Next, a layer 30 of intrinsic amorphous silicon
`removal of the second conductor in all of these open- 60 from 0.1 to 0.5 microns thick is deposited on the gate
`ings all across the wafer and particularly all across each
`dielectric layer without breaking the vacuum in the
`of the individual thin mm transistor arrays being fabri-
`deposition chamber. Next, a layer 32 of n+ amorphous
`silicon from 0.01 to 0.1 microns thick is deposited on top
`cated. Thereafter, the source gas for the reactive ion
`etching is changed to one which etches the first conduc-
`of the intrinsic silicon 30, again without breaking the
`tor. This second etchant source gas is preferably one 65 vacuum in the deposition chamber. The structure at the
`end of these steps is illustrated in FIG. 3.
`which provides etch selectivity to the underlying semi-
`conductor material. However, because the first conduc-
`Next
`the n+ amorphous silicon and the intrinsic
`tor layer is relatively thin, the etch selectivity to the
`amorphous silicon are masked and removed by etching
`
`Exhibit 1008, page 14
`
`

`

`5
`in areas outside the region where the FET will be subse(cid:173)
`quently defined. This is normally necessary to permit
`the formation of other elements such as liquid crystal
`pixels or light detecting elements adjacent to the transis(cid:173)
`tors. It also results in electrical isolation of the individ- 5
`ual FETs. A thin metal layer preferably about 500A of
`Mo may be deposited on the silicon before this masking
`and etching and subsequently removed after the etching
`of the silicon to protect the quality of the retained sili(cid:173)
`con. This etching of the silicon is preferably done with
`sloped sidewalls. The structure at the end of this step is
`illustrated in FIG. 4.
`The structure illustrated in FIG. 4 is ready for the
`deposition of the source/drain metallization for this
`thin-fJ.1m transistor. In accordance with the invention, a 15
`first relatively thin layer 34 (0.01 to 0.1 microns thick)
`of a first conductor is deposited directly on the n+
`amorphous silicon. This first conductor is preferably
`chromium but may also be nichrome, tantalum or other
`appropriate metals which make good ohmic contact to 20
`n + amorphous silicon and which preferably can be
`preferentially etched with respect to at least intrinsic
`amorphous silicon. Next, a relatively thick layer 36 of a
`second conductor is deposited on the first conductor 34.
`This second conductor is preferably molybdenum, but 25
`may also be aluminum or tungsten. This second conduc(cid:173)
`tor is preferably deposited by sputtering to a thickness
`of from 0.1 to 1 microns. One of the benefits of using
`molybdenum as this second conductor is the fact that it
`is significantly more conductive than the underlying 30
`chromium with the result that the source/drain metalli(cid:173)
`zation 38 has a higher conductivity than it would if the
`entire source/drain metallization were chromium. For
`imager applications, another advantage of the use of
`molybdenum as a second conductor is the fact that it 35
`makes good ohmic contact to n + amorphous silicon
`which is deposited on the source/drain metallization as
`part of the imager fabrication process. For non-imager
`applications, aluminum may be considered preferable to
`molybdenum because of the aluminum's higher conduc- 40
`tivity. The device structure at the end of the deposition
`of the source/drain metallization 38 is illustrated in
`FIG. 5.
`Next, a layer of photoresist 50 is formed on the upper
`surface of the source/drain metallization as shown in 45
`FIG. 6. This photoresist is then photolithographically
`patterned and developed to provide openings 52 with a
`sidewall slope of about 45· in alignment with the desired
`location of the channel region of the thin mm transistor
`and openings 54 with a sidewall slope of about 45· in SO
`those locations where the source/drain metallization is
`to be removed· in order to isolate different transistors,
`electrodes and so forth. The device structure at the end
`of this step is illustrated in FIG. 7.
`At this stage, the wafer is mounted in a reactive ion 55
`etching apparatus which is then purged and evacuated
`in accordance with normal reactive ion etching proce(cid:173)
`dures. A source gas flow of preferably 37.5 secm (stan(cid:173)
`dard cubic centimeters per minute) of sulfur hexafluo(cid:173)
`ride (SF6), 6.5 seem of Ch and 16 seem of 02 is estab- 60
`lished, introduced into the etching chamber at a pres(cid:173)
`sure of 65 mtorr and converted into a plasma state by Rf
`power. The resulting plasma etches the molybdenum in
`the openings 52 and 54. This etching is preferably car(cid:173)
`ried out until all the molybdenum is removed in center 65
`of the windows and is allowed to proceed for an addi(cid:173)
`tional 10% of that time to ensure that all of the molyb(cid:173)
`denum is removed from within the originally defined
`
`6
`windows 52 and 54. This molybdenum etching step is
`preferably carried out at a power of 0.17 Watts/cm2, to
`provide an etch rate of Mo:photoresist close to 1:1. The
`device structure at the end of this step is illustrated in
`FIG. 8. The presence of the chromium etch stop layer
`is particularly important where the etchant used for the
`molybdenum layer would etch the silicon at a compara(cid:173)
`ble or faster rate than it etches the molybdenum if that
`silicon' were exposed during the molybdenum etching.
`10 The dashed lines 52' and 54' illustrate the originalloca(cid:173)
`tion of the openings 52 and 54 respectively. It will be
`noted, that the underlying chromium is exposed sub(cid:173)
`stantially in alignment with the original window 52 or
`54 and that the overlying molybdenum has a sidewall
`slope of substantially 45 degrees and the photoresist has
`been etched back from the original edge 52' or 54' of the
`window to the top of the molybdenum slope. Next, the
`etchant gas is preferably changed to 70 secm Ch and 30
`seem 02 at a pressure of 100 mtorr to remove the ex(cid:173)
`posed chromium. This etch is preferably continued until
`all the exposed chromium appears to have been re-
`moved and is then continued for an additional 60 sec(cid:173)
`onds to ensure complete removal of the exposed chro(cid:173)
`mium. This etching step is preferably carried out at a
`power of 0.25 watts/cm2• Only at most a few hundred
`angstroms of silicon is removed during this step. The
`structure at the end of this chromium etching step is
`illustrated in FIG. 9.
`Next, the n+ amorphous silicon is etched from the
`channel region of the structure, that is in the windows
`52. During this etch, some of the intrinsic amorphous
`silicon must also be removed to ensure that all of the
`doped amorphous silicon has been removed. Since the
`n + amorphous silicon is uniform after the chromium
`etch, a short timed etch to subsequently remove the n+
`silicon 32 from over the intrinsic amorphous silicon 30
`leaves a substantially uniform intrinsic amorphous sili(cid:173)
`con layer. The structure at the end of this step is illus(cid:173)
`trated in FIG. 10.
`The photoresist is now stripped to provide the struc(cid:173)
`ture illustrated in FIG. 11 where the source/drain met(cid:173)
`allization has its desired fmal configuration as does the
`thin film transistor. A passivation layer 48, commonly
`known as a back channel passivation layer, is preferably
`conformally deposited on the entire upper surface of the
`wafer as shown in FIG. 12. This passivation layer 48
`provides excellent coverage at the edges of the source/(cid:173)
`drain metallization due to the sloped sidewall of the
`source/drain metallization and the thinness of the n+
`amorphous silicon layer which may have vertical side(cid:173)
`walls without producing an adverse affect on passiv-
`ation because of its height of only 0.02 to 0.15 microns.
`At this point, fabrication of the thin mm transistor is
`essentially complete and the process continues with
`normal processing and patterning for such structures at
`this stage. Such further steps may include opening
`contact windows to the source and drain metallizations
`and the gate metallizations as is appropriate to the over(cid:173)
`all device structure. If the device is to be an imager with
`semiconductor imaging devices disposed directly on the
`thin fl1m transistors, then the process proceeds to the
`fabrication of those devices in their normal fashion.
`While specific metals for use as the conductors have
`been identified, other metals or other non-metal con(cid:173)
`ductors may be employed as is considered desirable in
`particular structures. The important thing being that the
`second cond\lctor can be etched with an etchant which
`does not significantly etch the first conductor whereby
`
`Exhibit 1008, page 15
`
`

`

`7
`the f1l'st conductor acts as an etched stop for the etching
`of the second conductor and that the first conductor be
`sufficiently thin, if there is not a selective etchant for it
`relative to the semiconductor material disposed directly
`thereunder, that the amount of overetching required to 5
`ensure the removal of the f1l'st conductor does not unac(cid:173)
`ceptably remove the semiconductor material thereun(cid:173)
`der.
`Typically, the illustrated thin film transistor is only
`one of many such thin film transistors which are simul- 10
`taneously fabricated on the same substrate.
`While the semiconductor material
`in the just de(cid:173)
`scribed embodiment is amorphous silicon, since that is
`the material presently in typical use for thin film transis(cid:173)
`tors, it should be understood that this process is equally 15
`applicable to the use of other semiconductor materials
`or other forms of silicon. Further, while the gate dielec(cid:173)
`tric layer has been described as being silicon nitride, it
`will be understood that more than one sublayer may be
`present in the gate dielectric layer and various sublayers 20
`may have different compositions and a single layer
`dielectric may comprise Si02 or other dielectric materi(cid:173)
`als.
`Other semiconductor materials which are presently
`used in an amorphous condition are germanium and 25
`cadmium selenide. This process technique is applicable
`to those amorphous silicon semiconductor materials and
`any others as well as being applicable to polycrystalline
`_or even monocrystalline
`semiconductor materials
`where the underlying support structure supports the 30
`formation of such semiconductor layers.
`While the invention has been described in detail
`herein in accord with certain preferred embodiments
`thereof, many modifications and changes therein may
`be effected by those skilled in the art. Accordingly, it is 35
`intended by the appended claims to cover all such modi(cid:173)
`fications and changes as fall within the true spirit and
`scope of the invention.
`What is claimed is:
`1. A thin film transistor comprising:
`a substrate;
`gate metallization disposed on said substrate;
`a gate dielectric disposed on said gate metallization;
`
`40
`
`5,198,694
`
`8
`semiconductor material disposed on said gate dielec(cid:173)
`tric; and
`source and drain metallization disposed on said semi(cid:173)
`conductor material so as to form a channel region
`therebetween in said semiconductor material, said
`source and drain metallization comprising a f1l'st
`relatively thin layer of a first conductor and a sec(cid:173)
`ond relatively thick layer of a second conductor,
`said second conductor being etchable in an etchant
`to which said flI'St conductor is substantially im(cid:173)
`mune, said second conductor having sloped, dry
`etched sidewalls with substantially uniform slopes
`extending toward said channel region so as to facil(cid:173)
`itate the formation of a high integrity conformal
`back channel passivation layer;
`said f1l'st conductor comprising chromium and said
`second conductor comprising one of the group
`consisting of molybdenum and tungsten.
`2. The thin film transistor recited in claim 1 wherein:
`said flI'St conductor has sloped, dry etched sidewalls
`with a substantially uniform slope extending
`toward said channel region,
`3. The thin film transistor recited in claim 1 wherein:
`said semiconductor material is silicon.
`4. The thin film transistor recited in claim 1 wherein:
`said semiconductor material is amorphous silicon.
`S. The thin film transistor recited in claim 1 wherein:
`said semiconductor material is silicon.
`6. The thin film transistor recited in claim 5 wherein:
`said semiconductor material is amorphous silicon.
`7. The thin film transistor recited in claim 1 further
`comprising:
`a layer of dielectric material disposed on said source
`and drain metallization, said dielectric material
`forming a high integrity conformal back channel
`passivation layer over said sidewalls.
`8. The thin film transistor recited in claim 1 further
`comprising:
`a layer of dielectric material disposed on said source
`and drain metallization, said dielectric material
`forming a high integrity conformal back channel
`passivation layer over said sidewalls.
`• • • • •
`
`45
`
`50
`
`55
`
`60
`
`65
`
`Exhibit 1008, page 16
`
`