United States Patent [19]
`Mori et al.
`
`[54] THIN FILM TRANSISTORS WITHOUT
`CAPACITANCES BETWEEN ELECTRODES
`THEREOF
`
`[75]
`
`Inventors: Hisatoshi Morl, Fussa; Nobuyuki
`Yamamura, Hanno, both of Japan
`[73] Assignee: Casio Computer Co., Ltd., Tokyo,
`Japan
`[21] Appl. No.: 845,771
`
`[22] Filed:
`
`M~. 3, 1992
`
`[63]
`
`Related U.S. Application Data
`Continuation of Ser. No. 574,657, Aug. 28, 1990, aban(cid:173)
`doned.
`Foreign Application Priority Data
`[30]
`Sep.6, 1989 [JP]
`Japan
`[51]
`Int. CI.s
`[52] U.S. CI
`[58] Field of Search
`
`1-229227
`HOIL 49/02
`257/412; 257/66
`357/23.4, 4, 23.7;
`257/61,59,66,72,412
`References Cited
`U.S. PATENT DOCUMENTS
`4,951,113 8/1990 Huang et al.
`
`257/61
`
`[56]
`
`11111111111111111 11111 11111111111111111111111111111111111111111111111111111
`USOO5270567A
`Patent Number:
`Date of Patent:
`
`[11]
`
`[45]
`
`5,270,567
`Dec. 14, 1993
`
`5,017,984 5/1991 Tanaka et al
`5,109,260 4/1992 Tanaka et al.
`
`357/23.7
`257/61
`
`357/23.7
`357/23.7
`357/4
`357/23.7
`357/4
`350/334
`357/4
`357/4
`357/4
`357/23.7
`
`FOREIGN PATENT DOCUMENTS
`53-26584 3/1978 Japan
`56-15063 2/1981 Japan
`58-28870 2/1983 Japan
`60-117881
`6/1985 Japan
`61-105863
`5/1986 Japan
`61-156106 7/1986 Japan
`62-15857
`1/1987 Japan
`62-213165 9/1987 Japan
`63-131569 6/1988 Japan
`1-91467 4/1989 Japan
`Primary Examiner-Martin Lerner
`Assistant Examiner-Hung Dang
`Attorney, Agent, or Firm-Frishauf, Holtz, Goodman &
`Woodward
`[57]
`ABSTRACT
`In this film transistor used for a liquid crystal display
`element, etc.,
`the source and drain electrodes are
`formed at positions which do not overlap the gate elec(cid:173)
`trode. Capacitances between the gate and source elec(cid:173)
`trodes and between the gate and drain electrodes can be
`almost eliminated.
`
`5 Claims, 6 Drawing Sheets
`
`14
`
`12
`
`Exhibit 1003, page 1
`
`

`

`u.s. Patent
`
`Dec. 14, 1993
`
`Sheet 1 of 6
`
`5,270,567
`
`1
`
`13
`
`11
`
`2
`FIG.1
`(PRIOR ART)
`
`14
`
`12
`
`FIG.2
`
`Exhibit 1003, page 2
`
`

`

`u.s. Patent
`
`Dec. 14, 1993
`
`Sheet 2 of 6
`
`5,270,567
`
`10 (A)
`1 X1 0-4
`
`(VO=10V)
`
`1 X 10-6
`1X10-a
`1 X 10- 10 r - -_
`
`1 X 10-12
`"
`"
`1 X 1 0 - 14+---4'-';';"-------,
`o
`·40
`+40
`
`VG(V)
`
`FIG.S
`
`10(X10-6A)
`
`(VG=15V)
`
`5 4 3 2 1 o
`
`-F-"-------r------.
`o
`10
`20
`
`VO (V)
`FIG .•
`
`Exhibit 1003, page 3
`
`

`

`u.s. Patent
`
`US. Patent
`
`Dec. 14, 1993
`Dec. 14, 1993
`
`Sheet 3 of 6
`Sheet 3 of 6
`
`5,270,567
`5,270,567
`
`as
`It)
`~
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`C'CS
`N_
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`C")
`~
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`
`\
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`V
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`7
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`m3.
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`\
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`a:H.
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`C'CS
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`~
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`
`\\
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`m2.
`
`\\\\\“\‘\\\‘\\\\\n
`
`///////////
`
`\\\§\\\x
`s\\\\\\\\\\
`V\\\\\\\\\\xA
`
`.‘
`
`x\\\‘
`
`xxx
`
`‘\
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`(D
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`,.. -
`•
`as aN
`MNF
`Il.
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`C'CS
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`N,..
`amp
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`I
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`-2.
`0)
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`co
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`as
`m2.
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`C")
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`«a.
`
`."
`m
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`U.“—
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`x
`x
`
`\
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`\
`\\
`
`\\\\~\\s\x\§\\\s‘x\x‘\x
`
`\\~~
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`\
`
`wameww..
`\a:
`
`as
`,..
`,..
`
`Exhibit 1003, page 4
`
`Exhibit 1003, page 4
`
`
`
`
`
`
`

`

`u.s. Patent
`
`Dec. 14, 1993
`
`Sheet 4 of 6
`
`5,270,567
`
`(C/Cmax)
`
`1 .'.
`
`0.8
`
`0.6
`
`0.4
`
`0.2
`
`-----------------\------------'-"
`..I
`
`ELEMENT OF FIG.5
`
`ELEMENT OF FIG.6
`
`O-+------r----..-------.
`10
`100
`1000
`1
`FREQUENCY (kHz)
`
`FIG.7
`
`12
`FIG.8
`
`Exhibit 1003, page 5
`
`

`

`u.s. Patent
`
`Dec. 14, 1993
`
`Sheet 5 of 6
`
`5,270,567
`
`228
`
`21
`
`23
`
`X
`_____.J
`
`30
`
`24
`
`, 2p
`
`\ 28
`
`II,.•
`
`\
`
`29
`
`22
`FIG.&
`
`24
`
`21
`
`22
`
`FIG.10
`
`Exhibit 1003, page 6
`
`

`

`u.s. Patent
`
`Dec. 14, 1993
`
`Sheet 6 of 6
`
`5,270,567
`
`228
`FIG.11
`
`31
`
`32
`
`FIG.12
`
`Exhibit 1003, page 7
`
`

`

`1
`
`THIN FILM TRANSISTORS WITHOUT
`CAPACITANCES BETWEEN ELECTRODES
`THEREOF
`
`5,270,567
`
`2
`istics during a one-frame period until the next pixel
`electrode is selected are degraded.
`
`This application is a Continuation of application Ser.
`No. 07/574,657 filed on Aug. 28, 1990 now abandoned.
`
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`The present invention relates to a thin film transistor
`and, more particularly, to a thin film transistor which is
`improved not to have capacitances between a gate elec(cid:173)
`trode and source and drain electrodes.
`2. Description of the Related Art
`Thin film transistors (TFTS) include inverted-stag(cid:173)
`ger, stagger, inverted-coplanar, coplanar transistors.
`FIG. 1 shows a conventional thin film transistor, and,
`in this case, inverted-stagger transistor. In FIG. I, refer(cid:173)
`ence numeral I denotes a substrate made of glass or the 20
`like, and a gate electrode 2 made of a metal such as Cr
`is formed on the substrate 1. Reference numeral 3 de(cid:173)
`notes a gate insulating film made of SiN or the like
`formed on the gate electrode 2 throughout the entire
`surface of the substrate I, and reference numeral 4 de- 25
`notes an i-type a-Si semiconductor layer formed on the
`gate insulating film 3. The i-type semiconductor layer 4
`is opposite to the gate electrode 2 through the gate
`insulating film 3. Reference numeral 5 denotes n+-type 30
`a-Si semiconductor layers formed on the i-type semi(cid:173)
`conductor layer 4, and the n-type semiconductor layers
`5 are formed to vertically oppose the gate electrode 2
`and separated from each other on a channel portion.
`Reference numerals 6 and 7 denote source and drain 35
`electrodes made of a metal such as Cr and formed on
`the n-type semiconductor layers S. The source and
`drain electrodes 6 and 7 are formed to have the same
`pattern as those of the n-type semiconductor layers 5
`and connected to the i-type semiconductor layer 4 40
`through the n-type semiconductor layers S. Note that
`this thin film transistor is used as a pixel electrode selec(cid:173)
`tion switching element of a TFT active matrix liquid
`crystal display element. When the thin film transistor is
`employed to the TFT active matrix liquid crystal dis- 45
`play element, the gate electrode 2 of the thin film tran(cid:173)
`sistor is connected to a gate line (scanning line), and the
`drain and source electrodes 7 and 6 are connected to a
`data line and a pixel electrode, respectively.
`In the above thin film transistor, however, since the 50
`source and drain electrode 6 and 7 are vertically oppo(cid:173)
`site to the gate electrode 2 through the n-type and i-type
`semiconductor layers 5 and 4 and the gate insulating
`film 3, respectively, large capacitances CGsand CGDare
`generated between the gate electrode 2 and the source 55
`electrode 6 and between the gate electrode 2 and the
`drain electrode 7.
`For this reason, when the thin film transistor is used
`as, e.g., a pixel electrode selection switching element of
`a TFT active matrix liquid crystal display element, a 60
`voltage is applied from the data line to the pixel elec(cid:173)
`trode when the thin transistor is turned on upon applica(cid:173)
`tion of a gate voltage. When the thin film transistor is
`turned off, this voltage is immediately distributed in
`accordance with a rate of the gate-source capacitance 65
`(CGS) to the liquid crystal capacitance (CLe). For this
`reason, since the voltage at the pixel electrode is de(cid:173)
`creased lower than the data voltage, display character-
`
`5
`
`SUMMARY OF THE INVENTION
`The present invention has been made in consideration
`of the above problem, and has as its Object to provide a
`thin film transistor having almost no capacitances be(cid:173)
`tween a gate electrode and a source electrodes and
`10 between the gate electrode and a drain electrode.
`In order to achieve the aboveObject, according to the
`present invention, there is a thin mm transistor compris(cid:173)
`ing a gate electrode, a gate insulating film, an i-type
`semiconductor layer, an n-type semiconductor layer, a
`15 source electrode, and a drain electrode, wherein the
`source and drain electrodes are formed at positions
`which do not overlap the gate electrode. Using the
`above arrangement, capacitances between the gate and
`drain electrodes and between the gate and drain elec(cid:173)
`trodes can be almost eliminated. In addition, character(cid:173)
`istics of the thin film transistor can be confirmed.
`Additional objects and advantages of the invention
`will be set forth in the description which follows, and in
`part will be obvious from the description, or may be
`learned by practice of the invention. The objects and
`advantages of the invention may be realized and ob(cid:173)
`tained by means of the instrumentalities and combina(cid:173)
`tions particularly pointed out in the appended claims.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`The accompanying drawings, which are incorpo(cid:173)
`rated in and constitute a part of the specification, illus(cid:173)
`trate presently preferred embodiments of the invention,
`and together with the general description given above
`and the detailed description of the preferred embodi(cid:173)
`ments given below, serve to explain the principles of the
`invention.
`FIG. 1 is a sectional view showing a conventional
`thin film transistor;
`FIG. 2 is a sectional view showing a thin film transis(cid:173)
`tor according to the first embodiment of the present
`invention;
`FIG. 3 is a graph showing Va-ID characteristic
`curves of the thin film transistor in FIG. 2;
`FIG. 4 is a graph showing a Vv-ID characteristic
`curve of the thin film transistor in FIG. 2
`FIGS. 5 and 6 are views showing a testing element
`for measuring frequency characteristics of the thin film
`transistor;
`FIG. 7 is a graph showing frequency characteristics
`of the testing element in FIGS. 5 and 6;
`FIG. 8 is a sectional view showing a thin mm transis(cid:173)
`tor formed such that source and drain electrodes and an
`n-type semiconductor layer do not vertically overlap a
`gate electrode;
`FIG. 9 is a plan view showing a thin mm transistor
`according to the second embodiment of the present
`invention;
`FIGS. 10 and 11 are enlarged sectional views show(cid:173)
`ing the thin film transistor taken along lines X-X and
`XI-XI in FIG. 9; and
`FIG. 12 is a sectional view showing a thin film tran(cid:173)
`sistor according to the third embodiment of the present
`invention.
`
`Exhibit 1003, page 8
`
`

`

`5,270,567
`
`3
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS FIRST
`EMBODIMENT
`The first embodiment of the present invention will be 5
`described below.
`FIG. 2 is a sectional view showing a thin film transis(cid:173)
`tor according to this embodiment. Reference numeral
`11 denotes a substrate made of glass or the like, and a
`gate electrode 12 made of a metal such as Cr is formed 10
`on the substrate 11. Reference numeral 13 denote a gate
`insulating film formed on the gate electrode 12 through(cid:173)
`out the almost entire surface of the substrate 11, and
`reference numeral 14 denotes an i-type semiconductor
`layer made of amorphous silicon or polysilicon and 15
`formed on the gate insulating film 13. The i-type semi(cid:173)
`conductor layer 14 is opposite to the gate electrode 12
`through the gate insulating film 13. Reference numerals
`15 denote n-type semiconductor layers made of amor(cid:173)
`phous silicon or polysilicon and formed on the i-type 20
`semiconductor layer 14, and the n-type semiconductor
`layers 15 are formed to vertically oppose the gate elec(cid:173)
`trode 12 and separated from each other on a channel
`portion. Reference numerals 16 and 17 respectively
`denote source and drain electrodes made of a metal such 25
`as Cr formed on the n-type semiconductor layer 15. The
`source and drain electrodes 16 and 17 are formed at
`positions which do not vertically overlap the gate elec(cid:173)
`trode 12. The source and drain electrodes 16 and 17 are
`connected to the i-type semiconductor layer 14 through 30
`the n-type semiconductor layers 15. In this embodiment,
`a length 11 of an isolated portion (channel portion) of the
`n-type semiconductor is set to be 5 ILm, a horizontal
`interval 2 between the source or drain electrode 16 or
`17 is set to be 5 ILm, and a length 13 of the extended 35
`portion of the n-type semiconductor layer 15 from the
`source or drain electrode 16 or 17 is set to be 9 ILm.
`FIGS. 3 and 4 show static characteristics of the thin
`film transistor, wherein FIG. 3 shows V G (gate vol(cid:173)
`tage)-ID (drain current) characteristics when VD 40
`(drain voltage) = 10 V, and FIG. 4 shows V D-
`ID
`characteristics when VG = 15V.
`In the thin film transistor, since the source and drain
`electrodes 16 and 17 are formed at positions which do
`not vertically overlap the gate electrode 12, capaci- 45
`tances at high-frequency regions between the gate elec(cid:173)
`trode 12 and the source electrode 16 and between the
`gate electrode 12 and the drain electrode 17 can be
`almost eliminated.
`FIG. 7 shows a result obtained by measuring the two 50
`types of testing elements shown in FIGS. 5 and. 6,
`wherein the abscissa indicates frequencies (kHz), and
`the ordinate indicates a rate (C/Cmax) of a measuring
`capacitance (C) corresponding to each frequency to a
`maximum capacitance (Cmax obtained by changing 55
`frequencies. Each of the testing elements is formed by
`the following manner. A lower metal mm 120 is formed
`on a glass substrate lla. and an insulating mm 130 made
`of SiN and an i-type semiconductor layer 140 made of
`amorphous silicon or polysilicon are stacked thereon. 60
`An n-type semiconductor layer 15a made of amorphous
`silicon or polysilicon is formed on the i-type semicon(cid:173)
`ductor layer 140 to have the same pattern as the lower
`metal film 120. and an upper metal film 18 is formed on
`the n-type semiconductor layer 15a. The testing ele- 65
`ment in FIG. 5 is obtained by forming the upper metal
`film 18 to have an area (3.6X 1O-3cm2) which is almost
`equal to that of the lower metal film 120. and the testing
`
`4
`element in FIG. 6 is obtained by forming the upper
`metal film 18 to have a ! area of the lower metal film
`120. Note that, in FIGS. 5 and 6, reference numeral 19
`denotes an opening which is formed in a part of the
`stacked film from the upper metal film 18 to the insulat(cid:173)
`ing film 130 and which is formed for applying a voltage
`to the lower metal film 120.
`When the frequency characteristics of the two types
`of testing elements are measured by applying a testing
`voltage of 35 V to the lower metal mm 120. the fre(cid:173)
`quency characteristics of the testing element in FIG. 5
`obtained by forming the upper metal mm 18 to have an
`area which is almost equal to that of the lower metal
`mm 120 has characteristics indicated by a broken line in
`FIG. 7, and the testing element in FIG. 5 has a maxi(cid:173)
`mum capacitance of about 65 pF. The frequency char(cid:173)
`acteristics of the testing element in FIG. 6 obtained by
`forming the upper metal mm 18 to have a ! area of the
`lower metal mm 120 are characteristics indicated by a
`solid line in FIG. 7. The testing element in FIG. 6 has a
`maximum capacitance of 63 pF which is equal to that of
`the testing element in FIG. 5 in a low frequency region
`(1.0 kHz), but the testing element has a maximum capac(cid:173)
`itance of 19 pF (C/Cmax=0.3) in a high-frequency
`region (1.0 MHz). The testing element in FIG. 6 has a
`capacitance almost equal to that of the testing element
`in FIG. 5 in the low-frequency region, since the n-type
`semiconductor layer 150 formed on the i-type semicon(cid:173)
`ductor layer 140 to have the same pattern as that of the
`lower metal film 120 serves as an electrode in the low(cid:173)
`frequency region. A region constituted by a single layer
`of the n-type semiconductor layer 150 does not have a
`capacitance in the low-frequency region.
`That is, the capacitances between the gate and source
`electrodes 12 and 16 and between the gate and drain
`electrodes 12 and 17 depend on a portion where the
`drain and gate electrodes 16 and 17 overlap the gate
`electrode 12. As the thin film transistor of the first em(cid:173)
`bodiment, when the source and drain electrodes 16 and
`17 are formed at a positions which do not vertically
`overlap the gate electrode 12, capacitances between the
`gate and source electrodes 12 and 16 and between the
`gate and drain electrodes 12 and 17 in the high-fre(cid:173)
`quency region are lower than those characteristics indi(cid:173)
`cated by the solid line in FIG. 7.
`In addition, in the thin film transistor according to the
`first embodiment, the n-type semiconductor layers 15
`for connecting the gate electrode 12 to the source and
`drain electrodes 16 and 17 are formed to vertically
`oppose the gate electrode 12, and the source and drain
`electrodes 16 and 17 are connected to the i-type semi(cid:173)
`conductor layer 14 through the n-type semiconductor
`layers 15. Therefore, as described above,
`the n-type
`semiconductor layers 15 serve as source and drain elec(cid:173)
`trodes to obtain satisfactory transistor characteristics.
`That is, in order to eliminate the capacitances be(cid:173)
`tween the gate and source electrodes 12 and 16 and
`between the gate and drain electrodes 12 and 17, as in
`the thin fllm transistor shown in FIG. 8, the source and
`drain electrodes 16 and 17 and the n-type semiconduc(cid:173)
`tor layers 15 may be formed at the positions which do
`not vertically overlap the gate electrode 12. However,
`when a gate voltage is applied to the gate electrode 12,
`the thin film transistor is not operated, and any ON
`current (ION) does not flow. For this reason, in the thin
`film transistor of the above embodiment,
`the n-type
`semiconductor layers 15 for connecting the gate elec(cid:173)
`trode 12 to the source and drain electrodes 16 and 17 are
`
`Exhibit 1003, page 9
`
`

`

`5
`formed to vertically oppose the gate electrode 12, and
`only the source and drain electrodes 16 and 17 are
`formed at positions which do not vertically overlap the
`gate electrode 12. In this manner, as shown in FIGS. 3
`and 4, since the drain current ID of about 1.5 ILA flows 5
`when the drain voltage VD= 10 V and the gate voltage
`Va= 15 V, satisfactory.transistor characteristics can be
`obtained.
`In a thin film transistor used as, e.g., a pixel electrode
`selection switching element of a TFT active matrix 10
`liquid crystal display element, a gate ON time required
`for the ON current IONis about 60 ILsec, which corre(cid:173)
`sponds to a frequency of 17 kHz, and a fall time ofa gate
`pulse which adversely affects the gate-source capaci(cid:173)
`tance (Cas) is about 60 ILsec, which corresponds to a 15
`frequency of 20 MHz. As in the thin film transistor of
`the fIrst embodiment, when a portion where the source
`and drain electrodes are opposite to the gate electrode
`12 is formed by only the n-type semiconductor layers
`15, the n-type semiconductor layers 15 serve as source 20
`and drain electrodes in the gate ON time (17 kHz) to
`flow the ON current (ION). Since the n-type semicon(cid:173)
`ductor layer 15 has a gate-source capacitance (Cas) in
`the fall time (20 MHz), when the thin fIlm transistor is
`turned off, the pixel electrode voltage is not distributed 25
`at a rate of the gate-source capacitance (Cas) to a liquid
`crystal capacitance (CLe). Therefore, a display state can
`be continued during a one-frame period until the next
`pixel electrode is selected.
`The inverted-stagger thin fIlm transistor has been 30
`described in the above fIrst embodiment, but the present
`invention can be applied to stagger, inverted-coplanar,
`and coplanar thin transistors. In addition, the present
`invention can be applied to not only a thin fIlm transis(cid:173)
`tor used as a pixel electrode selection switching element 35
`of a TFT active matrix liquid crystal display element,
`but a thin fIlm transistor used in other applications.
`
`Second Embodiment
`The second embodiment of the present invention will 40
`be described below. FIGS. 9 to 11 show a thin fIlm
`transistor of a TFT panel used in a TFT active matrix
`liquid crystal display element according to the second
`embodiment of the present invention.
`Referring to FIGS. 9 to 11, reference numeral 21 45
`denotes an insulating transparent substrate made of
`glass, reference numeral 22 denotes a gate electrode
`formed on the substrate 21, and reference numeral 23
`denotes a gate line (scanning line) wired on the substrate
`21 and made of a metal such as chromium. The gate 50
`electrode 22 is connected to the gate line 23. The gate
`electrode 22 is formed by an n-type semiconductor
`layer made of amorphous silicon or polysilicon. The
`gate electrode 22 and the gate line 23 constituted by the
`n-type semiconductor layer are formed as follows. An 55
`n-type semiconductor and a metal such as chromium are
`sequentially deposited on the substrate 21, the metal
`film is patterned to have a shape of the gate line 23, and
`then the deposited n-type semiconductor film is pat(cid:173)
`terned to have a shape of the gate electrode 22. The 60
`deposited n-type semiconductor fIlm is linearly left
`under the gate line 23 throughout the entire length of
`the gate line 23, and the gate electrode 22 is connected
`to the gate line 23 at a line portion 220 under the gate
`line 23. Note that the thickness of the n-type semicon- 65
`ductor layer serving as the gate electrode 22 is about
`250 At and the thickness of the gate line 23 is about
`1,000 A.
`
`5,270,567
`
`6
`Reference numeral 24 denotes a transparent gate
`insulating fIlm formed on the entire surface of the sub(cid:173)
`strate 21 on the gate electrode 22 and the gate line 23
`and made of silicon nitride (SiN). An i-type semicon(cid:173)
`ductor layer 25 made of amorphous silicon or polysili(cid:173)
`con is formed to oppose the gate electrode 22 on the
`gate insulating film 24. Reference numeral 26 denotes an
`n-type semiconductor layer formed on the i-type semi(cid:173)
`conductor layer 25 and made of amorphous silicon or
`polysilicon, and the n-type semiconductor layers 26 are
`isolated from each other on a channel portion. Refer(cid:173)
`ence numerals 27 and 28 denote source and drain elec(cid:173)
`trodes made of a metal such as chromium. The source
`and drain electrodes 27 and 28 are formed on the n-type
`semiconductor layers 26 and connected to the i-type
`semiconductor layer 25 through the n-type semiconduc(cid:173)
`tor layers 26. An inverted-stagger thin fIlm transistor is
`constituted by the gate electrode 27, the gate insulating
`fIlm 24, the i-type semiconductor layer 25, the n-type
`semiconductor layers 26, and the source and drain elec(cid:173)
`trodes 27 and 28. The drain electrode 28 is connected to
`a data line 29 wired perpendicularly to the gate line 23
`on the gate insulating film 24. Reference numeral 30
`denotes a pixel electrode constituted by a transparent
`conductive fIlm such as ITO formed on the gate insulat(cid:173)
`ing fIlm 24. The pixel electrode 30 is connected to the
`source electrode 27 such that a terminal of the pixel
`electrode 30 is formed to overlap the source electrode
`27.
`That is, in the thin fIlm transistor of the second em(cid:173)
`bodiment, the source and drain electrodes 27 and 28 are
`formed to vertically oppose the gate electrode 22, and
`the gate electrode 22 is made of an n-type semiconduc(cid:173)
`tor and connected to the gate line 23 made of a metal.
`According to the thin fIlm transistor of the second
`embodiment, since the gate electrode 22 is made of an
`n-type semiconductor, capacitances between the gate
`electrode 22 and the source electrode 27 and between
`the gate electrode 22 and the drain electrode 28 can be
`eliminated. That is, when the gate electrode 22 is made
`of an n-type semiconductor, the source and drain elec(cid:173)
`trodes 27 and 28 are metal electrodes and capacitances
`are not formed between the gate electrode 22 and the
`source electrode 27 and between the gate electrode 22
`and the drain electrode 28 even if the gate electrode 22
`is vertically opposite to the source and drain electrodes
`27 and 28. This is because one of the gate electrode 22
`and the source or drain electrode 27 or 28 which inter(cid:173)
`poses the gate insulating film 24, the i-type semiconduc(cid:173)
`tor layer 25, and the n-type semiconductor layer 26 with
`the gate electrode 22 comprises only an n-type semicon(cid:173)
`ductor electrode. Therefore, as in the thin fUm transis(cid:173)
`tor of the fITst embodiment, capacitances between the
`gate electrode 22 and the source electrode 27 and be(cid:173)
`tween the gate electrode 22 and the drain electrode 28
`can be eliminated. According to this thin fUm transistor,
`the capacitances are not formed between the gate elec(cid:173)
`trode 22 and the source electrode 27 and between the
`gate electrode 22 and the drain electrode 28.·Unlike a
`conventional thin fIlm transistor, when the thin fUm
`transistor is turned off, a voltage applied from the data
`line to the pixel electrode by turning on the thin fUm
`transistor upon application of the gate voltage is not
`immediately distributed at a rate of a gate-source capac(cid:173)
`itance to a liquid crystal capacitance. Therefore, since
`the pixel electrode voltage during a one-frame period
`until the next pixel electrode 30 is selected can be kept
`at a voltage almost equal to a data voltage applied dur-
`
`Exhibit 1003, page 10
`
`

`

`7
`ing the selection, a display state during the one-frame
`period can be properly maintained, thereby improving
`display characteristics of a liquid crystal display ele(cid:173)
`ment.
`In addition, in the above thin film transistor of the 5
`second embodiment since metal electrodes are used as
`the source and drain electrodes 27 and 28 and the source
`and drain electrode 27 and 28 are vertically opposite to
`the gate electrode 22, an ON current larger than that of
`the thin fIlm transistor of the first embodiment can be 10
`obtained.
`In the thin fUm transistor of the second embodiment,
`only the gate electrode 22 is made of an n-type semicon(cid:173)
`ductor and the gate line 23 connected to the gate elec(cid:173)
`trode 22 is a metal line. Although the gate electrode 22 15
`is made of an n-type semiconductor, the electric resis(cid:173)
`tance of the gate line 23 can be decreased, and voltage
`drop across the gate line 23 can be reduced.
`Note that, in the second embodiment, an n-type semi(cid:173)
`conductor layer serving as the gate electrode 22 is lin- 20
`early formed throughout the entire length of the gate
`line 23, and the n-type semiconductor serving as the
`gate electrode 22 may be provided to only the transistor
`element portion. The gate electrode 22 may be formed 25
`such that a portion of the electrode 22 overlaps the gate
`line 23 to connect the gate line 23. In addition, an invert(cid:173)
`ed-stagger thin film transistor has been described in the
`above second embodiment. The present invention can
`be applied to stagger, inverted-coplanar, and coplanar 30
`thin film transistors. The present
`invention can be
`widely applied to not only a thin film transistor of a
`TFT panel for a TFT active matrix liquid crystal dis(cid:173)
`play element, but thin firm transistors for various pur(cid:173)
`poses such as a thin film transistor used as a memory 35
`element of a TFT memory array.
`
`Third Embodiment
`The third embodiment of the present invention will
`be described below. FIG. 12 is a sectional view showing 40
`a thin film transistor according to the third embodiment
`of the present invention.
`In the thin film transistor of the third embodiment,
`the n-type semiconductor layer described in the second
`embodiment is used as the gate electrode of the thin film 45
`transistor described in the first embodiment.
`That is, as a substrate, a gate electrode 32 constituted
`by an n-type semiconductor layer made of amorphous
`silicon or polysilicon is formed. Reference numeral 33
`denotes a gate insulating film made of SiN or the like 50
`and formed on the gate electrode 32 throughout the
`almost entire surface of the substrate 31, and reference
`numeral 34 denotes an i-type semiconductor layer
`which is opposite to the gate electrode 32 through the
`gate insulating fUm 33. Reference numerals 35 denote 55
`n-type semiconductor layers made of amorphous silicon
`or polysilicon and deposited on the i-type semiconduc(cid:173)
`tor layer 34, and the n-type semiconductor layers 35 are
`formed to vertically oppose the gate electrode 32 and
`isolated from each other on a channel portion. Refer- 60
`ence numerals 36 and 37 denote source and drain elec(cid:173)
`trodes made of a metal such as Cr and formed on the
`n-type semiconductor layers 35. The source and drain
`electrodes 36 and 37 ar formed at positions which do
`not vertically overlap the gate electrode 32, and the 65
`source and drain electrodes are connected to the i-type
`
`5,270,567
`
`8
`semiconductor layer 34 through the n-type semiconduc(cid:173)
`tor layers 35.
`As described above, according to this embodiment, as
`in the first embodiment, capacitances between the gate
`and source electrodes and between the gate and drain
`electrodes can be almost eliminated, and satisfactory
`thin film transistor characteristics can be properly ob(cid:173)
`tained.
`Although an inverted-stagger thin mm transistor has
`been described in the third embodiment, this embodi(cid:173)
`ment can be applied to stagger, inverted-eoplanar, and
`coplanar thin fllm transistors.
`In addition, this embodiment can be applied to not
`only a thin film transistor used as a pixel electrode selec(cid:173)
`tion switching element of a TFT active matrix liquid
`crystal display element, but a thin film transistor used
`for other purposes.
`As described above, according to the present inven(cid:173)
`tion, since the source and drain electrodes are formed at
`positions which do not overlap the gate electrode, ca(cid:173)
`pacitances between the gate and source electrodes and
`between the gate and drain electrodes can be almost
`eliminated. In addition, satisfactory thin film transistor
`characteristics can be properly obtained.
`Additional advantages and modifications will readily
`occur to those skilled in the art. Therefore, the inven(cid:173)
`tion in its broader aspects is not limited to the specific
`details, and representative devices, shown and de(cid:173)
`scribed herein. Accordingly, various modifications may
`be made without departing from the spirit or scope of
`the general inventive concept as defined by the ap(cid:173)
`pended claims and their equivalents.
`What is claimed is:
`1. A thin film transistor comprising:
`an I-type semiconductor;
`a gate electrode facing said I-type semiconductor
`with a gate insulating film therebetween;
`a pair of n-type semiconductor layers formed on a
`surface of said I-type semiconductor, said n-type
`semiconductor layers being separated from each
`other so as to form a channel portion in said I-type
`semiconductor, such that said n-type semiconduc(cid:173)
`tor layers partially overlap said gate electrode,
`each of said n-type semiconductor layers having a
`first portion, overlapping said gate electrode, and a
`second portion, which does not overlap said gate
`electrode; and
`'.
`source and drain electrodes partially formed on the
`second portions of said n-type semiconductor lay(cid:173)
`ers, such that. said source and drain electrodes do
`not overlap said gate electrode.
`2. A thin film transistor according to claim 1, wherein
`said source and drain electrodes are situated outside of
`outer edges of said gate electrode.
`3. A thin film transistor according to claim 1, wherein
`said gate electrode is formed only on an n-type semicon(cid:173)
`ductor layer.
`4. A thin film transistor according to claim 1, wherein
`each of said I-type semiconductor and said n-type semi(cid:173)
`conductor layers is formed of a thin fUm semiconductor
`of amorphous silicon.
`5. A thin film transistor according to claim 1, wherein
`each of said I-type semiconductor and said n-type semi(cid:173)
`conductor layers is formed of a thin film semiconductor
`of polysilicon.
`• • • • •
`
`Exhibit 1003, page 11
`
`