SEL EXHIBIT NO. 2019
`INNOLUX CORP. v. PATENT OF SEMICONDUCTOR ENERGY
`LABORATORY CO., LTD.
`
`IPR2013-00064
`
`

`

`Jpn. J. Appl. Phys. Vol. 37 (1998) pp. 4704-4710
`Part 1, No. 9A, September 1998
`©1998 Publication Board, Japanese Journal of Applied Physics
`
`Electrical Instability of Hydrogenated Amorphous Silicon Thin-Film Transistors
`for Active-Matrix Liquid-Crystal Displays
`Chun-sung CHIANG 1 , Jerzy KANICKI1· * and Kazushige TAKECHI2
`1 Department of Electrical Engineering and Computer Science, CenTer for Display Technology and Manufacturing,
`University of Michigan, Ann Arb01; Michigan, USA
`2 Functional Devices Research Laboratories, NEC Corp, Kawasaki, Kanagawa, Japan
`
`(Received May 14, 1998; accepted for publication July 1, 1998)
`
`We investigated the threshold voltage shifts (11. VT) of inverted-staggered hydrogenated amorphous silicon (a-Si:H) thin(cid:173)
`film transistors (TFTs) induced by steady-state (de) and pulsed (ac) gate bias-temperature-stress (BTS) conditions. Our
`study showed that, for an equivalent effective-stress-time, 11. VT has an apparent pulse-width dependence under negative BTS
`conditions-the narrower the pulse width, the smaller the 11. VT. This gate-bias pulse-width dependence is explained by an
`effective-carrier-concentration model, which relates 11. VT for negative pulsed gate-bias stress to the concentration of mobile
`carriers accumulated in the conduction channel along the a-Si:Hjgate insulator interface. In addition, our investigation of the
`methodology of a-Si:H TFT electrical reliability evaluation indicates that, instead of steady-state BTS, pulsed BTS should be
`used to build the database needed to extrapolate 11. VT induced by a long-term display operation. Using these experimental
`results, we have shown that a-Si:H TFTs have a satisfactory electrical reliability for a long-term active-matrix liquid-crystal
`display (AMLCD) operation.
`KEYWORDS: amorphous silicon thin film transistor, threshold voltage, electrical instability, active-matrix liquid-crystal display
`
`1.
`
`Introduction
`There have been many studies of hydrogenated amorphous
`silicon (a-Si:H) thin-film transistors (TFTs) that concluded
`that two main mechanisms can explain the electrical insta(cid:173)
`bilities. I-B) One is the carrier trapping in the gate insulator.
`In most cases, the gate insulator of a-Si:H TFTs is made of
`amorphous silicon nitride (a-SiNx :H) deposited by plasma(cid:173)
`enhanced chemical-vapor-deposition (PECVD) technique. It
`is known that this type of a-SiNx :H can have a high density of
`defects, 1•2) which could trap charges during a gate bias-stress
`of a-Si:H TFTs. This trapping will induce a threshold voltage
`(VT) shift. The other mechanism is point defect creation at or
`near the a-Si:Hj a-SiNx :H interface that will increase the den(cid:173)
`sity of deep-gap states, causing the electron threshold voltage
`to shift in a more positive direction.4•5•8) A decrease in defect
`density has the opposite effect on VT.
`Until recently, most studies of a-Si:H TFT electrical in(cid:173)
`stability have employed a steady-state (de) bias-temperature(cid:173)
`stress (BTS) conditions in which a constant gate bias is ap(cid:173)
`plied to the gate electrode and a-Si:H TFT characteristics
`are measured during and/ or after a certain bias-stress pe(cid:173)
`riod. A satisfactory description of the stress-voltage, stress(cid:173)
`temperature, and stress-time dependence of the threshold
`voltage shift (.6. VT) has been reported for such experiments. 1)
`However, in active-matrix liquid-crystal displays (AMLCDs),
`a-Si:H TFTs are bias-stressed under a pulsed (ac) gate(cid:173)
`bias addressing (line-at-a-time) with a typical addressing fre(cid:173)
`quency of 60 Hz.9) It has been pointed out that certain differ(cid:173)
`ences exist in .6. VT between the steady-state and pulsed-bias
`stresses. 10· 11) Therefore, from a practical point of view, to ob(cid:173)
`tain a good estimation of the long-term reliability of a-Si:H
`TFTs in AMLCDs, it is necessary to understand the details
`of the electrical instability of a-Si:H TFTs under pulsed gate(cid:173)
`bias stress conditions that are similar to a typical AMLCD
`addressing conditions.
`In this paper, we investigate the .6. VT of bottom-gate back-
`
`*E-mail address: kanichi@eecs.umich.edu
`
`channel-etched a-Si:H TFTs induced by pulsed BTS. First,
`we examine the mechanism responsible for .6. VT in our a(cid:173)
`Si:H TFTs. Then, we propose a model to explain the ob(cid:173)
`served difference between steady-state and pulsed BTS in(cid:173)
`duced .6. VT, especially in the case of the negative gate-bias
`stress. We also examine methods of estimating .6. VT of a-Si:H
`TFTs under pulsed bias-stress having both positive and nega(cid:173)
`tive gate-voltage cycles. Using the proposed pulsed gate-bias
`instability model, an example of the reliability estimation of
`AMLCDs is given at the end of this paper.
`
`2. Experiment
`Figure 1(a) shows the cross-section of the inverted(cid:173)
`staggered bottom-gate a-Si:H TFT used in this study. Both
`a-Si:H and a-SiNx :H layers are about 3000 A thick. This TFT
`is a back-channel-etched type with a phosphorus (P) doped
`(n+) a-Si:H layer 500 A thick that is used to form an ohmic
`contact to chromium sourcejdrain electrodes. An over-etch
`process was used to assure complete removal of then+ a-Si:H
`in the back-channel region. At room temperature ("'-'25°C),
`the regular a-Si:H TFT with channel width(W)jlength(L)
`of 80 11m! 12 f,Lm has a field-effect mobility (tlFE) of about
`0.9cm2/V·s and a threshold voltage (VT) of 1 V. These val(cid:173)
`ues indicate a good electrical performance of a-Si:H TFTs
`used in this study. Together with the regular TFTs, ambipolar
`a-Si:H TFTs were also fabricated for studying the electrical
`instability mechanism as shown in Fig. l(b). The fabrication
`process for the ambipolar TFT is the same as for the regu(cid:173)
`lar TFT except that then+ a-Si:H layer was omitted and alu(cid:173)
`minum was used as the sourcejdrain contact metal. To have
`a similar process sequence for both types of a-Si:H TFTs, an
`etching process of the back-channel was used for the ambipo(cid:173)
`lar a-Si:H TFTs with an etching time approximately equal to
`the over-etching time used for the regular TFT. In addition,
`the ambipolar a-Si:H TFT has a channel length of 480 11m; a
`long channel length is selected in this case to reduce the effect
`of series resistance of the source/ drain contacts.
`A series of bias-temperature-stress experiments were con(cid:173)
`ducted for both steady-state and pulsed bias-stress conditions
`
`4704
`
`

`

`Jpn. J. Appl. Phys. Vol. 37 (1998) Pt. 1, No. 9A
`
`C. CHIANG eta[.
`
`4705
`
`a-SiNx:H (3000 A)
`
`H P 4156
`Semiconductor
`Analyzer
`1-----t
`
`1
`
`2
`
`HP41501
`Pulse
`Generator
`
`Fig. 2. Schematic of experimental setup used for steady-state and pulsed
`bate bias-temperature-stress experiments.
`
`a-SiNx:H (3000 A)
`
`dark condition.
`
`(a)
`
`(b)
`
`a-Si:H (3000 A)
`
`Fig. 1. Cross-sections of (a) regular and (b) ambipolar back-channel-etch
`a-Si:H TFTs used in this study.
`
`using an HP4156A semiconductor parameter analyzer and a
`pulse generator (Fig. 2). Pulses with different waveforms
`were applied to the gate electrode. To assure a uniform elec(cid:173)
`trical field distribution along the a-Si:H/ a-SiNx :H interface,
`the drain-to-source voltage (Vn) of the TFr was set to 0 V
`during the BTS. At the preselected stress time, the bias-stress
`was interrupted and the current-voltage Un-Vo) character(cid:173)
`istics were immediately measured in the saturation region
`(Vn > Va - VT) at the temperature used for BTS. For the
`ambipolar a-Si:H TFTs, a drain voltage of 15 V and a larger
`gate voltage (sweeping from -30V to +30V) were used to
`obtain both electron and hole conduction characteristics. A
`delay time of 2 s was used for each measurement point to re(cid:173)
`duce the transient effect, This delay time was a trade-off be(cid:173)
`tween getting a significant hole current and reducing the mea(cid:173)
`surement voltage .stress effect. Because of the longer mea(cid:173)
`surement time needed for the ambipolar TFrs, a lower stress
`temperature (40°C) was used to reduce the stress effect dur(cid:173)
`ing the In-Va sweeping. On the other hand, a higher stress
`temperature (TsT = 70°C) was chosen for the regular a-Si:H
`TFTs during the steady-state and pulsed BTS to accelerate
`the electrical instability that can be produced within a reason(cid:173)
`able experimental period. The threshold voltage (VT) at stress
`time (tsT) during the stress of a-Si:H TFr was extracted from
`the In-Va characteristics by using the conventional current(cid:173)
`voltage equations derived from the gr;:tdual channel approxi(cid:173)
`mation (GCA) theory,
`w
`1
`ln(tsT) = lJLFECiL[Va- VT(fsT)]:-
`
`?
`
`with Vn > (Va- VT)
`
`(1)
`
`where In· <tsT) is the measured drain current at tsT and Ci is
`the gate insulator capacitance per unit area. We used regular
`a-Si:H TFrs with L = 10 J.Lm and W = 60 J.Lm, that is sim(cid:173)
`ilar to the TFrs used in AMLCDs. It should be noted that
`all BTS and current-voltage measurements were conducted in
`
`3. Results and Discussion
`3.1 Steady-state BTS of a-Si:H TFTs
`It has been previously indicated that the mechanism re(cid:173)
`sponsible for 1:::. VT of a-Si:H TFTs can be determined by using
`ambipolar a-Si:H TFrs.4l The ambipolar a-Si:H TFTs pro(cid:173)
`vide the capability of measuring electron and hole conduc(cid:173)
`tions simultaneously because no n+ a-Si:H layer is used at
`source/drain contacts to block the hole current. If charges
`are trapped in a-SiNx:H during BTS, both electron and hole
`conduction characteristics will have rigid shift in the same di(cid:173)
`rection. On the other hand, they will shift in the opposite di(cid:173)
`rections if defect density is changed by BTS. Figure 3 shows
`the evolution of In-Va characteristics for our ambipolar a(cid:173)
`Si:H TFrs under +20V and -20V steady-state BTS. As
`can be seen in this figure, the electrons have a higher con(cid:173)
`duction current than holes, indicating that electrons have a
`higher mobility in a-Si:H TFrs. For the +20 V BTS condi(cid:173)
`tion, an apparent right shift was obtained for electron conduc(cid:173)
`tion characteristics. The hole conduction characteristics, on
`the other hand, shifted slightly to the right at the beginning of
`the positive gate-bias stress and then started to shift to the left.
`These results indicate that there is an increase of the density of
`deep-gap states in a-Si:H near the a-Si:Hja-SiNx:H interface,
`which causes the electron and hole conduction characteristics
`to shift in opposite directions. However, there are also charge
`trapping which induces the initial right shift of the hole con(cid:173)
`duction characteristics. The combination of charge trapping
`and defect creation causes an additive and complimentary ef(cid:173)
`fects in the shifts of electron and hole conduction characteris(cid:173)
`tics, respectively. For -20 V BTS, an apparent left shift was
`obtained for electron conduction characteristics, and a steeper
`characteristics was obtained for hole conduction. This result
`corresponds to a decrease of deep-gap states in the band-gap
`region. Similarly to the positive BTS, charge trapping is also
`present and the resulting effects is large electron conductimi
`shifts and much smaller hole conduction shift.
`It was reported previously that, empirically, a stretched(cid:173)
`exponential function can well describe the stress-time and
`stress-voltage dependence of 1:::. VT in a-Si:H TFrs;1, 12l
`
`1:::. VT(tsT) = 1:::. VTo 11- exp [- c~T Y])'
`
`(2)
`
`

`

`4706
`
`Jpn. J. Appl. Phys. Vol. 37 (1998) Pt. 1, No. 9A
`
`C. CHIANG eta!.
`
`--initial
`-------- 5-102 s = t
`ST
`············ 1·103 s
`---5-103s
`--1·104s
`
`-20
`
`-10
`
`0
`
`.. -
`~7
`.. ,~:f'
`,r .~.~
`l'tJ'
`"
`I
`!! II
`'I
`•:
`
`Ik
`
`.: I
`U I
`l
`J.l
`Stress: T ~ 40 oc
`V8T=+20V
`20
`30
`
`10
`
`Gate voltage (V)
`
`(a)
`
`--initial
`2
`-------- 5·10 S = 1gT
`............ 1-103 s
`---5·103s
`---l-104s
`
`~~
`~~·
`VD = 15 v
`,._~-;::;•
`~~=<·;~'
`'I ...
`{, f/
`i I ::
`II f!
`...
`~---fL.·
`,, :•
`·'
`'
`I .,
`/' ::
`} .. ,
`j:
`I
`/.·~'
`
`Stress: T8T = 40 oc
`V8T=-20V
`
`-Original
`---- tST=200s
`······tST=500s
`-~1000s
`- t5T=2000s
`
`10-5
`
`10-6
`
`10·7
`
`10-8
`
`10-9
`
`< '-"
`....f
`
`10-11
`-10
`
`-5
`
`8
`
`6
`
`TST=70°C
`
`5
`
`10
`
`0
`VG(V)
`
`(a)
`
`4
`
`-> ._,
`;.:
`~ 0
`
`2
`
`-2
`
`-4
`
`10-5
`
`10-6
`<
`......, 10-7
`=
`~
`10-8
`=
`·ta
`Q 10-9
`
`(.)
`
`10.10
`
`10-11
`-30
`
`10-5
`
`10-6
`
`10-7
`
`s
`=
`~ 10-8
`=
`·ta
`Q 10-9
`
`(.)
`
`10.10
`
`10-11
`-30
`
`-20
`
`20
`
`30
`
`102
`
`-10
`10
`0
`Gate voltage (V)
`
`(b)
`
`103
`Stress time (sec)
`
`104
`
`(b)
`
`Fig. 3. Evolution of Io-Va characteristics of the ambipolar a-Si:H
`lFTs induced by (a) positive and (b) negative steady-state gate
`bias-temperature-stress. The stress and measurement temperatures are
`40°C.
`
`(a) Evolution of Io-VG characteristics and (b) extracted !1 VT ver(cid:173)
`Fig. 4.
`sus stress time for the regular a-Si:H lFTs induced by steady-state pos(cid:173)
`itive and negative gate bias-temperature-stress. The 1FT chamtel width
`and length are 80 and 12 Jlm, respectively. The stress and measurement
`temperatures are 70°C.
`
`with
`
`where 11 VTo is the shift at infinite time, r is a characteris(cid:173)
`tics time constant, and {3 is the stretched-exponential expo(cid:173)
`nent which is temperature-dependent. For a short effective
`stress time (tsT « r), eq. (2) can be simplified as
`
`(4)
`Figure 4(a) shows the evolution of Io-Va characteristics
`of our ordinary a-Si:H TFTs under +20 V and -20 V steady(cid:173)
`state BTS at 70°C. Because of the presence of P-doped a(cid:173)
`Si:H layer at the sourcejdrain contacts, only the electron con(cid:173)
`duction characteristics are observed. The characteristics have
`right and left shifts under +20V and -20V BTS, respec(cid:173)
`tively. The evolution of the threshold voltage shift extracted
`from these curves, using eq. (1), is shown in Fig. 4(b). Fit-
`
`ting of the experimental data with eq. (4) is also shown; we
`obtained the stretched-exponential exponents {3 of 0.50 and
`0.32 for positive and negative BTS, respectively; and these {3
`values are similar to those reported previously. 1• 3l
`Figure 5 shows 11 VT as the functions of effective gate-bias
`stress voltages at various stress times. The effective stress
`voltage is defined as the difference between the applied gate(cid:173)
`bias stress voltage CVsT) and the initial threshold voltage (VTi)·
`It can be seen that there is a power-law dependence between
`11 VT and the effective stress voltage that can be described by,
`
`(5)
`
`This power law dependence on stress voltage indicates that
`the characteristics time constant r in eq. (2) must be stress(cid:173)
`voltage dependent. We can further simplify the stretched(cid:173)
`exponential equation to
`
`

`

`Jpn. J. Appl. Phys. Vol. 37 (1998) Pt. 1, No. 9A
`
`C. CHIANG eta/.
`
`4707
`
`10-5
`
`10-7
`
`Pulse-width = 10ms
`10-6 Duty-cycle = 50%
`--Original
`-------- t8T=200s
`············ t8T=500s
`-·-·-·-·-·-· t8T=2000s
`-··-··········· t5T=5000s
`
`,.-.. 10-8
`$
`.....P
`
`10-9
`
`Slope= 1.7
`
`T =70 oc
`ST
`tsT= 1000 sec
`
`0.1 '---------'-------~~-----'------'
`20
`40
`
`1'1 VT as a function of effective stress voltage I VsT- V" I induced by
`Fig. 5.
`positive and negative BTS.
`
`10-11~...:--~--'=--~---J.--~--':--~-_j
`-10
`-5
`0
`5
`10
`VG(V)
`
`Fig. 6. Evolution of ID-VG characteristics of the regular a-Si:H TFTs in(cid:173)
`duced by pulsed positive and negative gate bias-temperature-stress. The
`TFT channel width and length are 80 and 12 j..l.m, respectively. The stress
`and measurement temperatures are 70° C.
`
`(6)
`
`where A is a constant. Equation (6) was often used for the
`estimation of 1'. VT in AMLCDs, 13l and will be used in this
`study. Table I lists the parameters extracted from the experi(cid:173)
`mental data obtained for the a-Si:H TFTs under positive and
`negative steady-state gate-bias stress. This data is consistent
`with the previously repmted results. 13l
`
`4
`
`V8T= + 20V
`3 -o-d.c.
`-~>.- PW=lOOms
`2 -v-PW=lms
`--o-- PW=20f.I.S
`
`T8T= 70 °C
`50% duty-cycle
`
`3.2 Pulsed BTS of a-Si:H TFTs
`Figure 6 show the evolution of In-Vo characteristics of a(cid:173)
`Si:H TFTs during a positive and negative pulsed BTS with a
`duty-cycle of 50% and gate-bias pulse width of 50 f.LS at 70°C.
`A qualitative comparison between Fig. 6 and Fig. 4(a) shows
`that, under positive BTS, pulsed and steady-state bias-stress
`induce a similar evolution of In-V0 characteristics. However,
`1'. VT induced by the negative pulsed gate-bias stress is signif(cid:173)
`icantly smaller in comparison with 1'. VT induced by negative
`steady-state gate-bias stress. Figure 7 shows the threshold
`voltage shift versus effective stress time under both positive
`and negative bias-stress for different pulse conditions. The ef(cid:173)
`fective stress time is the accumulated time when the gate volt(cid:173)
`age is high (ON). For positive pulsed gate-bias stress, 1'. VT
`is slightly smaller than that for steady-state gate-bias stress
`and does not depend apparently on gate-bias pulse width. For
`negative pulsed gate-bias stress, 1'. VT has strong pulse-width
`(PW) dependence-the wider the pulse-width, the greater the
`magnitude of 1'. VT.
`It was reported previously that detrapping during pulsed
`operation can explain the smaller 1'. VT induced by steady(cid:173)
`state BTS. 10l The detrapping mechanism can be applied to
`a-Si:H TFTs if the electrical instability mechanism is mainly
`
`Table I. Extracted parameters from 1'1 VT induced by positive and negative
`steady-state bias-stress for inverted-staggered a-Si:H TFTs used in this
`study.
`
`Positive(+ )BTS
`Negative(+)BTS
`
`A
`
`1.5 X 10-4
`-1.4 X 10-4
`
`Cl
`
`1.9
`2.4
`
`fJ
`0.5
`0.32
`
`'-'
`
`ll(
`
`ll(
`
`)j(
`
`ll(
`
`)j(
`
`1 - VsT=-20V
`> 0 -•-d.c.
`-e-PW=ls ~ > <I -1 - • - PW=200ms
`""
`-T - PW=lOOms ~
`
`-2
`
`-3
`
`-+-PW=50ms
`-+-PW=lOms
`-x-PW=lms
`--*- PW=l00f.I.S
`
`-4
`101
`
`103
`102
`Effective stress time (sec)
`
`1'1 VT versus effective stress time induced by positive and negative
`Fig. 7.
`gate-bias stress with different gate pulse width. The effective stress time is
`the accumulated time when the gate voltage is high (ON).
`
`associated with the charge-trapping in the gate insulator. Dur(cid:173)
`ing the OFF-cycle of the pulse bias-stress, some of the trapped
`charge which is not deeply trapped could be relaxed from the
`trap centers. However, for our a-Si:H TFTs, defect creation
`also contributes to the shift of VT. Therefore, this smaller
`1'. VT for positive pulsed BTS can also be partially attributed
`to relaxation of created deep-gap defects during OFF-periods
`in the pulsed operation. It should be noted that there is a very
`small pulse-width dependence observed for positive pulsed
`BTS. As will be discussed below, this can be explained by the
`fast channel electron accumulation during positive pulse bias,
`that is about or less than 1 f.LS for a 10-f.LID channel-length
`TFT.
`
`

`

`4708
`
`Jpn. J. Appl. Phys. Vol. 37 (1998) Pt. 1, No. 9A
`
`C. CHIANG et al.
`
`For negative pulsed BTS, the pulse-width dependence of
`.6. VT was previously attributed to the different effective(cid:173)
`voltages across the gate insulator under different pulsed bias(cid:173)
`stress conditions_lll This explanation is also based on a
`charge-trapping mechanism indicating that .6. VT is related
`to the trapped charge in gate insulators, and the amount of
`trapped charge is related to the electrical field across the gate
`insulator. As shown earlier, for our a-Si:H TFTs, in addition
`to positive charge trapping, there is also defect removal which
`contributes to the negative .6. VT. To characterize the apparent
`pulse-width dependent .6. VT for negative BTS condition, we
`used an simple RC circuit to simulate the operation of a-Si:H
`TFTs under negative pulsed BTS. This RC circuit consists
`of the gate insulator capacitance Ci, a-Si:H capacitance Cs,
`and a effective a-Si:H resistance Rs for hole conduction, as
`shown in Fig. 8. When a negative pulse is applied to the gate
`electrode, the total gate voltage is initially distributed across
`the insulator and a-Si:H because the a-Si:H layer acts as a
`semi-insulator under negative bias at high frequency. After
`the negative pulse is turned-on, carriers (holes) would start to
`accumulate near the interface due to thermal generation and
`the voltage drop across the gate insulator that increases grad(cid:173)
`ually. The voltage drops across the insulator and a-Si:H at
`timet* after applying a gate pulse with amplitude VsT can be
`expressed as
`
`*
`[
`V;,(t ) = VsT 1-
`
`ci
`Ci + Cs
`
`(
`t* )]
`exp - -
`TRe
`
`(7)
`
`with
`
`TRe = RsCs
`TRe represents the effective time constant of hole accumula(cid:173)
`tion along the a-Si:Hja-SiNx :H interface. The accumulation
`of hole could be due to thermal electron-hole pair generation
`near the a-Si:Hja-SiNx:H interface, in which the generated
`electrons are repelled by the applied negative gate-bias. The
`initial voltage (t* = 0) across the gate insulator is about
`Cs
`VsT
`Ci +Cs
`which is about 60% of the stress gate voltage level. There(cid:173)
`fore, the effective-voltage model could not explain the very
`small .6. VT (less than 10% of .6. VT for steady-state condition)
`
`(8)
`
`(9)
`
`V;, (0) =
`
`Fig. 8. The equivalent circuit of a-Si:H TFT during negative pulsed gate
`bias-temperature-stress.
`
`1 1PW
`NAe = --
`PW o
`( PW)]
`TRe
`TRe
`=Nne 1 - - - + --exp - - -
`[
`TRe
`PW PW
`where Nne = -C1 VsT I q is the accumulated carrier under
`steady-state gate bias condition.
`Assuming that .6. VT during the negative bias-stress is pro(cid:173)
`portional to the effective carrier concentration, we have the
`following relationship between steady-state and pulsed stress
`bias induced .6. VT with the same effective stress time,
`.6. V.f'e = 1 _ TRe + TRe exp (- PW)
`.6. v.pe
`TRe
`
`N(t*) dt*
`
`PW PW
`
`observed for narrow pulse-width ( < 1 ms) in our BTS exper(cid:173)
`iment, since the voltage across the gate insulator dming the
`pulse operation is always greater than [Cs/(C + Cs)]VsT·
`In this paper, we propose an alternative effective carrier
`model which correlates the threshold voltage shift to the ef(cid:173)
`fective hole concentration accumulated near the a-Si:Hja(cid:173)
`SiNx :H interface during negative pulse operation. As shown
`in the RC circuit of Fig. 8, after applying a negative· gate
`pulse, the accumulated carrier concentration Naccum at the a(cid:173)
`Si:Hja-SiNx:H intelface can be expressed as
`
`(10)
`Naccum = -Ni + Ns
`where Ni = Ci V,jq, Ns = Cs V5 jq, and q is the electron
`charge. From eq. (7) and using VsT = v; + Vs, we then have
`the accumulated carrier concentration N at timet* given by
`J
`- 1 .
`
`C VsT [
`*
`N (t ) = -q- exp
`
`(
`
`t* )
`- rRe
`
`(11)
`
`The average accumulated carrier concentration, NAe, under
`pulsed gate-bias with pulse-width of PW can then be ex(cid:173)
`pressed as
`
`(12)
`
`(1 3)
`
`where .6. v.fe and .6. v.pe are threshold voltage shifts induced
`by pulsed and stead-state BTS, respectively. Figure 9 shows
`the experimental .6. VT at a fixed effective stress time of 1000 s
`as a function of pulse-width. A fitting curve using eq. (13)
`is also shown in this figure with fitting parameters, rRe ~
`0.032 s which corresponds to Rs ~ 99 kQ-cm2 per unit area
`for 3000 A thick a-Si:H. The equivalent resistivity at the
`stressing temperature (70aC) is then about 3.3 x 10100-cm.
`This high resistivity could be due to a low conductivity of
`holes andjor a high contact resistance between then+ a-Si:H
`and intrinsic a-Si:H layers for hole conduction under negative
`bias-stress.
`
`3.3 Estimation of .6. VT during AMLCD operation
`A method for AMLCD long-term lifetime estimation based
`on addition of .6. VT's induced by positive and negative steady(cid:173)
`state BTS was reported in the literature. 13l However, as shown
`above, steady-state BTS results can not truly reflect the elec(cid:173)
`trical instability of a-Si:H TFT induced by pulsed BTS. We
`have conducted several BTS experiments to test the superpo(cid:173)
`sition method of positive and negative BTS under both steady(cid:173)
`state and pulsed BTS conditions. Figure 10(a) shows positive
`(+20 V) and negative ( -20 V) steady-state BTS induced .6. VT
`together with .6. VT induced by an alternatively pulsed BTS of
`+20V and -20V with a 50% duty-cycle. It can be clearly
`seen that, for the 50% duty-cycle condition, the real threshold
`
`

`

`Jpn. J. Appl. Phys. Vol. 37 (1998) Pt. 1, No. 9A
`
`C. CHIANG et al.
`
`4709
`
`1.0
`
`0.8
`
`0.6
`
`0.4
`
`I
`
`I
`
`T5T= 70 °C
`e V5T=-20V
`.A. V5y=+20V
`-- - - - - Fitting curve
`
`I
`I
`I
`I
`I
`
`I ,_
`
`I
`I
`I
`I
`I
`I
`I
`
`0.2 -
`
`0.0 1-
`
`...
`10-5
`
`=f-,
`,
`-t-___ .:e-'
`.......
`......
`....
`10-3
`10-2
`10-4
`
`.......
`10-1
`
`.. ...
`10°
`
`LWU
`
`101
`
`Gate-bias pulse width (sec)
`
`threshold voltage shift versus gate-bias stress
`Fig. 9. Normalized
`pulse-width. The measurements and bias stress were done at 70°C.
`
`voltage shift under alternatively pulsed BTS is (especially at
`longer stress time) greater than the values obtained by simply
`adding up the !l VT's induced by the corresponding positive
`and negative steady-state BTS. This difference is due to an
`overestimation of !l VT induced by negative steady-state BTS
`in comparison to negative pulsed BTS induced !l VT, which
`has apparent pulse-width gate-bias dependence as discussed
`above.
`On the other hand, Figure lO(b) shows the results for
`both the superposition of pulsed positive and negative BTS,
`and the corresponding alternative positive/negative pulsed
`BTS. From these experimental results, we can conclude
`that !l VT induced by pulsed bias-stress with alternative
`positive/negative amplitudes is approximately equal to the
`!l VT-values obtained by simply adding up !l VT's for solely
`positive and solely negative pulsed gate-bias stresses. This
`result pulsed indicates that, if !l VT of a-Si:H TFTs induced
`by positive pulsed and negative pulsed gate-bias stresses is
`obtained, respectively, a good estimation of a-Si:H TFT !l VT
`corresponding to AMLCD operation can be obtained. There(cid:173)
`fore, it is clear that only !l VT's induced by pulsed bias-stress
`with positive and negative amplitudes can be used to estimate
`AMLCD long-term electrical reliability. The total !l VT can
`be described by
`!l V/'CtsT) = !l vT+CtsT) + !l vT-CtsT).
`For our a-Si:H TFTs, positive pulsed gate-bias stress induced
`threshold voltage can be expressed as
`
`(14)
`
`!l vT+CtsT) =A+. (VaH- VT!)"'+ . UsT. De)f>+
`
`(15)
`
`and threshold voltage shift induced by negative pulsed gate(cid:173)
`bias stress, combining with the above mentioned pulse-width
`dependence, can be given by
`!l Vi CtsT) = A_ · CVT1 - VaL)"'- · [tsT · (1 - De) ]fi- · Fpw
`(16)
`
`with
`
`,....._
`G
`~
`-<J
`
`8
`
`6
`
`4
`
`2
`
`0
`
`-2
`
`-4
`
`-•-+20V,DC
`-'f'--20V,DC
`-o- +20V/-20V 50% 50Hz
`-+-Sum of-•- &-'f'-
`
`/
`
`.)' /
`
`/L -+
`/,a+-+'+
`............. ~+/
`~~
`o-¢::_..,._..,. -.........,......,.
`---...........,
`.......... .....,
`
`TsT=70°C
`
`...................
`
`102
`
`103
`
`104
`Effective stress time (sec)
`
`105
`
`(a)
`
`- • - +20V,50%,PW=50us
`6 - • - -20V,50%,PW=50us
`-o- +20V/-20V,50%,PW=50us
`-+-Sum of - • - and - • -
`
`4
`
`TsT=70°C
`
`....
`L-~
`li1
`J!f
`Q
`rq)
`~q('
`~:$
`-·-·-·-·-·-·-·-···-....-·-·
`
`> '-'
`~
`-<J
`
`2
`
`0
`
`-2 1d
`
`Effective stress time (sec)
`
`(b)
`
`t,. VT versus effective stress time for steady-state and pulsed BTS.
`Fig. 10.
`Sum of steady-state and pulsed positive and negative BTS induced t,. VT's
`is also shown.
`
`(17)
`
`De= ToN
`Tframe
`where VaL and VaH are the high and low gate-bias pulse lev(cid:173)
`els, respectively; De is the duty-cycle used to address the
`liquid-crystal pixels. Using the parameters given in Table I,
`we can estimate the evolution of !l VT induced by pulsed gate(cid:173)
`bias-stresses. Figure 11 shows the experimental results of
`!l VT induced by different pulsed gate-bias stress conditions,
`together with the calculated !l VT based on eqs. (13)-(16). It
`can be seen that a satisfactory fit between the calculated and
`experimental data can be obtained.
`Based on the methodology described above, we can esti(cid:173)
`mate the long-term evolution of !l VT induced by a typical
`AMLCD addressing conditions. For example, for a typical
`SXGA (1280 x 1024) display addressed by a 60Hz scanning
`signal, the gate pulse width is about 20 p.,s. If the gate sig(cid:173)
`nal has a positive (ON) and negative (OFF) voltage levels of
`18 and -8 V, respectively, and a common electrode voltage
`
`

`

`4710
`
`Jpn. J. Appl. Phys. Vol. 37 (1998) Pt. I, No. 9A
`
`C. CHIANG eta/.
`
`V8T=+20V/-20V
`T8T= 70 °C
`
`,.--._ >
`'--' > <l
`
`10-1
`
`10-2
`
`10-3
`
`..,
`
`10
`
`10
`
`) Period=l00!ls,DC=50
`
`• ) Period=20ms,DC=50%
`..,
`
`&
`
`) Period=20ms,DC=20%
`) Period=20ms,DC=l0%
`10
`
`Stress time (sec)
`
`11 VT versus stress time for negative and positive pulsed BTS with
`Fig. I I.
`frequency of 10KHz. The calculated 11 VT (-) is also shown for different
`pulsed gate-bias conditions.
`
`8.-----------------------~-,
`
`6
`
`4
`
`Threshold voltage shift margin
`
`Stress time (sec)
`
`Fig. I2. Projection of 11 VT for a-Si:H TFTs induced by a typical SXGA
`display addressing conditions.
`
`level of + 5 V, we then have an effective positive and nega(cid:173)
`tive gate-bias stresses of+ 13 and -13 V, respectively, during
`the TFT ON- and OFF-period. Figure 12 shows the predicted
`evolution of /1 VT for our a-Si:H TFTs under the suggested
`display addressing conditions. It can be seen that at the early
`stage of the display operation, /1 VT has a negative shift. This
`is due to the longer negative bias period during a display ad(cid:173)
`dressing in comparison to positive bias period. As stress time
`increases, /1 VT starts to increases exponentially because the
`positive bias has larger ,8-value, which starts to dominate at
`longer stress times. Assuming the maximum allowable 11 VT
`of 3 V for normal display operation, our estimation of there(cid:173)
`liability period for our a-Si:H TFTs is about 10 years at 70°C,
`which is quite satisfactory for the display industry standard.
`
`4. Conclusion
`In this paper, we investigated the electrical instabilities of
`our bottom-gate a-Si:H TFTs under different BTS conditions.
`Our BTS experiments clearly indicated that there is a funda(cid:173)
`mental difference between steady-state and pulsed gate-bias
`stress induced !1 VT. We demonstrated that the reliability es(cid:173)
`timation of a-Si:H TFTs used in AMLCDs can be obtained
`from a series of short-term steady-state and pulsed BTS ex(cid:173)
`periments. Our results suggest that the a-Si:H TFTs long-term
`reliability is quite satisfactory for AMLCD.
`
`Acknowledgments
`The authors C.-S. Chiang and J. Kanicki would like to
`thank the Center for Display Technology and Manufactur(cid:173)
`ing at University of Michigan for the financial support of this
`work and the NEC Functional Devices. Research Laboratories
`for its technical assistance.
`
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`