SEL EXHIBIT NO. 2013
`INNOLUX CORP. v. PATENT OF SEMICONDUCTOR ENERGY
`LABORATORY CO., LTD.
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`IPR2013-00064
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`Electrochemical and Solid-State Letters, 10 共8兲 J83-J85 共2007兲
`1099-0062/2007/10共8兲/J83/3/$20.00 © The Electrochemical Society
`Cu/CuMg Gate Electrode for the Application of Hydrogenated
`Amorphous Silicon Thin-Film Transistors
`M. C. Wang,a T.-C. Chang,b,*,z Po-Tsun Liu,c Y. Y. Li,d R. W. Xiao,d L. F. Lin,d
`and J. R. Chena
`aDepartment of Materials Science and Engineering, and dInstitute of Electronics Engineering,
`National Tsing Hua University, Hsin-Chui 300, Taiwan
`bDepartment of Physics and Institute of Electro-optical Engineering, Center for Nanoscience and
`Nanotechnology, National Sun Yat-sen University, Kaohsiung 804, Taiwan
`cDepartment of Photonics and Display Institute, National Chiao Tung University, Hsin-Chu 300, Taiwan
`
`J83
`
`The feasibility of using Cu/CuMg as a gate electrode for a-Si:H thin-film transistors 共TFTs兲 has been investigated in this work.
`The issue of adhesion between the Cu film and glass substrates has been overcome by introducing the Cu/CuMg alloy. Further-
`more, a wet-etching process of Cu-based gate metal has been proposed by using the copper etchant in the conventional printed
`circuit boards. The experimental result showed superior performance of a-Si:H TFT with desired electrode taper angle and
`minimal loss of critical dimension. The a-Si:H TFT exhibited mobility of 0.37 cm2/V s, subthreshold slope of 0.83 V/dec, and Vth
`of 2.02 V.
`© 2007 The Electrochemical Society.
`
`关DOI: 10.1149/1.2739209兴 All rights reserved.
`
`Manuscript submitted February 1, 2007; revised manuscript received March 26, 2007. Available electronically May 22, 2007.
`
`Copper metallization has received increasing attention in both
`microelectronics1,2 and the large-area and high-resolution active ma-
`共AM-LCDs兲,3 because
`trix liquid-crystal displays
`resistance-
`capacitance 共RC兲 time delay can be reduced considerably by em-
`ploying low electrical resistivity metallurgy. Moreover, double-
`frequency addressing has been proposed to improve the moving
`image quality by reducing the motion blur of thin-film transistor
`共TFT兲-LCDs. However, the double-rate operation also shortens the
`device
`charging time
`and therefore
`reduces
`the TFT-LCD
`brightness.4,5 To reduce the RC delay effectively, either the gate
`busline thickness or width needs to be increased to reduce the line
`resistance. However, large busline width is not desirable, because it
`may not only reduce the pixel aperture-ratio but may also increase
`the line capacitance 共crossover and busline-to-common electrode ca-
`pacitances兲. To increase the busline thickness, taper edge formation
`of the gate has to be developed to prevent crossover and interlayer
`defects due to the poor step coverage and the pinhole formation
`through the gate insulators. Unfortunately, this process is not avail-
`able at the present time and it is very difficult to develop. This has
`led to the introduction of copper metallization to silicon integrated
`circuits despite the challenges that copper poses to the fabrication
`processing and the fact that it is a potential lifetime killer. However,
`the use of Cu has also been hampered by its poor adhesion to the
`glass substrates and taper angle of the multilayer metal etching pro-
`cess. Several technologies have been used to break through these
`problems. First, self-passivated Cu gates with MgO and CrO were
`investigated. Annealing Cu alloy at 350–500°C in an O2 environ-
`ment gives rise to the self-passivation of Cu by forming metal oxide,
`which showed good adhesion to the substrate glass and good stabil-
`ity of Cu. Also, the efficient passivation of Cu electrode can be
`performed by all plasma-enhanced chemical vapor deposition
`共PECVD兲 processes.6-8 Second, an insertion of an indium tin oxide
`共ITO兲 layer between the glass substrate and Cu gate showed a good
`adhesion to the glass substrate.9 However, the former approach suf-
`fers a high temperature process and the resistivity may be increased
`due to the doping metal element. As for the second approach, the
`development of the etchant is difficult because of the galvanic effect
`of the dissimilar metals in the etchant. Third, the Al2O3 buffer layer
`formed by plasma improves the adhesion to the glass substrate and
`AlN formed by plasma protects the Cu diffusion to the TFT and
`plasma damage during the deposition of silicon–nitride layer.10
`However, the thin Al2O3 buffer layer and AlN layer suffered from
`
`* Electrochemical Society Active Member.
`z E-mail: tcchang@mail.phys.nsysu.edu.tw
`
`the process stability. The deposition of a CuMg alloy film has been
`reported by Lee et al. to form a MgO/Cu bilayer structure with low
`Cu resistivity and good adhesion to SiO2, although a higher leakage
`current density has been observed in this structure.11 In this paper,
`the Cu/CuMg alloy bilayer structure with similar Cu resistivity was
`studied in the gate metal structure for a good adhesion layer and
`provided a good taper angle of metal gate electrode after multilayer
`metal-etching process.
`
`Experimental
`A thin CuMg alloy layer 共50 nm兲 was deposited onto a glass
`substrate by dc magnetron sputtering at 99.99% purity level of
`CuMg alloy target 共4.5 atom % Mg兲 at room temperature. After-
`ward, a 300 nm thick Cu layer was continuously deposited by sput-
`tering on the CuMg alloy layer without breaking the vacuum. The
`sputtering conditions of Cu and CuMg alloy were as follows. The
`base pressure of the deposition chamber was 7.0 ⫻ 10−7 Torr, Ar
`pressure 6 mTorr, power 1500 W, and the substrate temperature was
`at room temperature. The resistivity of the metal film was measured
`by four-point probe. To investigate the adhesion ability between the
`Cu/CuMg alloy and glass substrates, the 3M 610-tape test technol-
`ogy was performed. The taper angle of the Cu/CuMg alloy structure
`after the etch process was also confirmed by scanning electron mi-
`croscopy 共SEM兲 and optical microscopy 共OM兲. The gate metal hill-
`ock issue of the Cu/CuMg alloy structure was also confirmed via
`SEM and OM observation. After patterning the Cu/CuMg alloy gate
`electrodes, the a-Si:H TFT devices were fabricated by depositing a
`300 nm thick silicon–nitride 共SiNx兲, a 200 nm thick a-Si:H active
`layer, and a 50 nm thick n+-a-Si:H layer subsequently onto the
`Cu/CuMg alloy gate using PECVD. After the Si active islands were
`patterned, an Al metal layer was deposited by sputtering and pat-
`terned for forming source/drain electrodes. Finally, the n+-a-Si:H
`layer on the TFT channel region was etched via the source/drain
`pattern electrodes as the etching mask. The detailed process flow
`was illustrated in Fig. 1. The dimensions of channel length and
`width were both 20 ␮m for the TFT devices. The electrical measure-
`ment was carried out on a HP 4156C precision semiconductor pa-
`rameter analyzer.
`
`Results and Discussion
`Table I shows the comparison of resistivity and adhesion be-
`tween different Cu metals and glass substrate using the 3M-610 tape
`test method. The alloy resistivity is
`increased from 2.6 to
`8.7 ␮⍀ cm with doping elements. Although the resistivity of pure
`Cu film is only 2.6 ␮⍀ cm, the 3M tape test failed due to the poor
`adhesion of Cu film on the glass substrate. Doping the Mg element
`
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`J84J84
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`Electrochemical and Solid-State Letters, 10 共8兲 J83-J85 共2007兲
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`Figure 1. Detailed process flow of the Cu/CuMg gate a-Si:H TFT with the
`back-channel-etched 共BCE兲 inverted-staggered TFT structure.
`
`into Cu could improve the adhesion and could pass the 3M tape test.
`This is because the Mg could easily form the MgO layer between
`the glass substrate and Cu during the sputtering process. As a result,
`the CuMg alloy film acting as a buffer layer could improve the
`adhesion between the Cu and glass substrates. By using the
`Cu/CuMg alloy structure, therefore, a low-resistance metal line with
`good adhesion can be obtained experimentally. The gate metal struc-
`ture of Cu/CuMg alloy has low resistivity compared with the pure
`Cu film and could pass the 3M tape test. Furthermore, the wet-
`etching process of the Cu/CuMg alloy structure was also success-
`fully completed by introducing the ferric chloride base etchant typi-
`cally used in printed circuit boards 共PCBs兲. The SEM image shown
`in Fig. 2 has exhibited a much-desired taper angle 共42°兲 for the
`Cu/CuMg gate electrode, beneficial for film step coverage and pre-
`venting pinhole formation through the gate insulators.12-15 By de-
`creasing the etching time,
`the taper angle below 40° could be
`achieved. The inset in Fig. 2 shows the definition of the taper angle.
`The conventional value of the taper angle used in the TFT-LCD was
`from 45 to 70°. The etch rate of the Cu/CuMg film was about
`1.8 nm/s and the critical dimension loss was less than 1.5 ␮m. The
`use of the CuMg film enhances the taper angle, due to the complete
`wet-etching process of Cu/CuMg materials similar to each other.
`Figure 3 shows the SEM image of the Cu/CuMg alloy gate after
`
`Table I. The adhesion and resistivity of metal.
`
`Pure Cu
`CuMg alloy
`Cu/CuMg alloy
`
`Thickness
`共nm兲
`300
`50
`300/50
`
`Resistivity
`共␮⍀ cm兲
`2.6
`8.7
`2.63
`
`3M-610
`tape test
`
`No pass
`Pass
`Pass
`
`Figure 2. SEM cross-sectional picture of the Cu/CuMg alloy structure after
`the wet-etching process. 共Inset兲 Definition of taper angle of gate electrode.
`
`Figure 3. SEM cross-sectional picture of the Cu/CuMg alloy as gate struc-
`ture after PECVD trilayer dielectrics. 共Inset兲 OM picture of the TFT device
`after island is defined.
`
`PECVD trilayer dielectrics. Also, the inset shows the OM image of
`the TFT device after Si island etch. Neither the SEM nor the top-
`view OM images have shown hillock formation in the thin-film
`deposition process. Because the metallic Cu has higher heat endur-
`ance than Al, the hillock formation was not observed after the
`PECVD trilayer dielectric film on the gate metal. After a complete
`TFT manufacture process, the electrical characteristics of a-Si:H
`TFTs with the Cu/CuMg alloy gate are also investigated, as shown
`in Fig. 4. Figure 4a shows transfer characteristics of the Cu/CuMg
`alloy gate a-Si:H TFT measured at the drain voltages of 0.1 and
`10 V. The proposed a-Si:H TFT with the Cu/CuMg alloy gate dem-
`onstrated the field-effect mobility of 0.37 cm2/Vs 共extracted from
`the linear ID-VG plot, where the VD = 0.1 V兲, the subthreshold slope
`of 0.83 V/dec, the threshold voltage of 2.02 V 共extracted from the
`linear ID-VG plot, where the VD = 0.1 V兲, and the ION/IOFF ratio of
`106 at VD = 10 V. The gate leakage current through the gate insula-
`tor is less than 10−13 A. The low gate leakage current is also due to
`the superior performance of the Cu/CuMg alloy gate electrode with
`the desired taper angle and nonhillock formation. Furthermore, the
`output characteristics of a-Si:H TFTs are also shown in Fig. 4b,
`measured at the gate voltages sweeping from 2 to 8 V by a voltage
`step of 2 V. No current crowding effect is observed in the Cu/CuMg
`gate a-Si:H TFT device. This also means that the voltage applied on
`the TFT was not limited by the source/drain contacted resistance.
`
`Conclusions
`A Cu alloy gate a-Si:H TFT device with low resistivity has been
`developed successfully in this work. The CuMg alloy film acting as
`a buffer layer could improve the adhesion between the Cu and glass
`substrates. In addition, the desired taper angle of the Cu/CuMg alloy
`electrode can be obtained by applying a wet-etch process with a
`ferric chloride base etchant. Low gate leakage and reliable process
`was achieved due to the Cu/CuMg electrode with an ideal taper
`angle and hillock-free dielectric film formation. Compared to the
`typical a-Si:H TFT, the Cu gate a-Si:H TFT exhibited similar device
`performance but much lower gate-line resistivity than Al or MoW
`metal gate line.
`
`Acknowledgments
`This work was partially supported by the National Science Coun-
`cil of the Republic of China under contract no. NSC-94-2120-M-
`110-005, NSC94-2215-E-009-031, NSC-95-2120-M-110-003, and
`NSC 95-2221-E-009-254-MY2 and MOEA Technology Develop-
`ment for Academia under Project 94-EC-17-A-07-S1-046 and the
`MOE ATU Program. Also, the authors thank the Taiwan TFT LCD
`Association 共TTLA兲 for their support.
`
`
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`Downloaded on 2013-06-17 to IP 130.207.50.37 ecsdl.org/site/terms_use address. Redistribution subject to ECS license or copyright; see
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`Electrochemical and Solid-State Letters, 10 共8兲 J83-J85 共2007兲
`
`
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`J85J85
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`共a兲 Output
`Figure 4.
`characteristics
`共ID-VG curve兲 of the Cu gate a-Si:H TFT
`and 共b兲 output characteristics
`共ID-VD
`curve兲 of the Cu gate a-Si:H TFT. The
`channel length and width of TFT devices
`were 20 ␮m.
`
`National Sun Yat-Sen University assisted in meeting the publication costs
`of this article.
`
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