SEL EXHIBIT NO. 2011
`
`INNOLUX CORP. v. PATENT OF SEMICONDUCTOR ENERGY
`LABORATORY CO., LTD.
`
`IPR2013-00064
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`

`

`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`INNOLUX CORPORATION
`Petitioner
`v.
`PATENT OF SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
`
`Patent Owner
`
`
`CASE IPR2013-00064; and
`CASE IPR2013-00065
`PATENT 7,923,311
`
`
`
`
`DECLARATION OF ALEX Z. KATTAMIS PH.D. P.E.
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`

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`
`
`
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`I, Alex Z. Kattamis, do hereby declare and state that all statements made herein are
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`based on my own personal knowledge and that all statements made on information
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`and belief are believed to be true. I further do hereby declare and state that these
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`statements are made with the knowledge that willful false statements are
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`punishable by fine or imprisonment or both under 18 U.S.C. § 1001.
`
`
`Dated: July 29, 2013
`
`
`
`______________________________
`
`Alex Z. Kattamis
`
`
`
`

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`
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`Table of Contents
`I. INTRODUCTION ............................................................................................. 1
`
`A. Background and Qualifications ................................................................. 1
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`B. Compensation .............................................................................................. 2
`
`C.
`
`Information Considered.............................................................................. 3
`
`II. LEGAL STANDARD OF PATENTABILITY ............................................ 3
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`A. Anticipation .................................................................................................. 3
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`B. Obviousness .................................................................................................. 4
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`C. The Person of Ordinary Skill in the Art ................................................... 7
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`D. Claim Construction ..................................................................................... 8
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`III. The ’311 Patent ............................................................................................... 9
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`A. The Background of the ’311 Patent ........................................................... 9
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`B. The Invention of the ’311 Patent .............................................................. 16
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`a) The “Step-Like” Structure ....................................................................... 16
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`b) Etching to form Source and Drain Regions
`“without Removing said Resist” and “Using said Resist” ......................... 21
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`IV. Summary of Opinions .................................................................................. 22
`
`V.
`
`Summary of the Asserted Art ...................................................................... 24
`
`A. Taniguchi .................................................................................................... 24
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`B. Mori ............................................................................................................ 29
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`C. Van Zant ..................................................................................................... 34
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`D. Kato Reference .......................................................................................... 35
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`VI. Detailed Analysis .......................................................................................... 36
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`i
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`A. Taniguchi in view of Mori does not render
`Claims 9, 10, 15, 48, and 51 obvious. ................................................................. 36
`
`B. There is no motivation to combine Taniguchi with Mori ...................... 50
`
`C. Taniguchi in view of Mori and Van Zant does not render
`Claim 11 obvious. ................................................................................................ 78
`
`D. Taniguchi in view of Mori and Kato does not render
`Claims 17, 18, 19, and 52 obvious. ..................................................................... 79
`
`E. Taniguchi in view of Mori and Van Zant does not render
`claims 23, 24, and 26 obvious. ............................................................................ 80
`
`F. Taniguchi in view of Mori and Van Zant does not render
`claim 27-30 obvious. ............................................................................................ 81
`
`G. Taniguchi in view of Mori and Van Zant does not render
` claims 31-34, and 53 obvious. ............................................................................ 82
`
`H. Taniguchi in view of Mori and Van Zant does not render
`claims 35-38, and 54 obvious. ............................................................................. 82
`
`I. Taniguchi in view of Mori and Van Zant does not render
`claims 39, 40, 42, and 49 obvious. ...................................................................... 83
`
`J. Taniguchi in view of Mori and Van Zant does not render
`claims 43, 44, 46 and 50 obvious. ....................................................................... 84
`
`
`
`ii
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`
`
`
`Declaration of Alex Z. Kattamis, Ph.D. P.E.
`
`
`INTRODUCTION
`
`I.
`
`A.
`
`Background and Qualifications
`
`1.
`
`My name is Alex Z. Kattamis and I am a Senior Managing Engineer
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`at Exponent, Inc. (“Exponent”), which is a multidisciplinary engineering and
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`science firm headquartered in Menlo Park, California 94025. I am currently based
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`in Exponent’s New York City office.
`
`2.
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`I have been retained by Steptoe and Johnson LLP on behalf of
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`Semiconductor Energy Laboratory Co., Ltd. to provide expert assistance in the
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`matter referenced above concerning liquid crystal semiconductor devices and, in
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`particular, thin film transistor (TFT) technology.
`
`3.
`
`I received the following academic degrees: Ph.D. in Electrical
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`Engineering from Princeton University, 2007; Masters of Arts in Electrical
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`Engineering from Princeton University, 2004; and a Bachelor of Science in
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`Electrical Engineering from University of Connecticut (magna cum laude), 2002. I
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`have also held a position as an adjunct assistant professor in the Department of
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`Physics at the Polytechnic Institute of New York University.
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`4.
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`I have extensive experience in the field of integrated circuits, flat
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`panel display technology, and flexible electronics, explained briefly as follows.
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`1
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`
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`5.
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`My research at Princeton University centered on the design and
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`fabrication of TFT backplanes for organic light-emitting displays and reflective
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`electrophoretic displays on flexible metal foils and polymer substrates. These
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`backplanes were fabricated using amorphous silicon as well as nanocrystalline
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`silicon. At Exponent I have assisted various companies in research and
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`development projects including developing alternative substrates for flexible TFT
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`devices and reverse engineering and characterizing a-Si and poly-Si TFT LCDs.
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`6.
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`Prior to my Ph.D., I worked and interned at General Electric Industrial
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`Systems, where I designed and implemented electronic trip units and current
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`sensing systems for metering and switchgear. The work included analog
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`electronics design, modeling, and firmware coding for product prototyping.
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`7.
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`As a result of my years of experience in researching and developing
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`integrated circuits and TFT technologies, I have authored or co-authored over 20
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`publications in major technical journals and conference proceedings.
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`8.
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`My latest curriculum vitae, which includes a list of my publications
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`and presentations, is attached at Appendix A.
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`B.
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`Compensation
`
`9.
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`Exponent charges an hourly rate of $325 plus expenses for my work
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`performed in connection with this case. My compensation is not related to any
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`particular outcome of this case.
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`2
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`C.
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`Information Considered
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`10. My opinions stated in this document are based on my careful
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`consideration of U.S. Patent No. 7,923,311 (“the ’311 patent”) and other
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`information listed in Appendix B.
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`II.
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`LEGAL STANDARD OF PATENTABILITY
`
`11.
`
`In forming my opinions and considering the patentability of the claims
`
`of the ’311 patent, I am relying upon certain legal principles that counsel has
`
`explained to me.
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`12.
`
`I understand that for an invention claimed in a patent to be found
`
`patentable, it must be, among other things, new and not obvious in light of what
`
`came before it. Patents and publications which predated the invention are
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`generally referred to as “prior art.”
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`13.
`
`I understand that in this proceeding the burden is on the party
`
`asserting unpatentability to prove it by a preponderance of the evidence. I
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`understand that “a preponderance of the evidence” is evidence sufficient to show
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`that a fact is more likely than not.
`
`A.
`
`Anticipation
`
`14.
`
`I understand that the following standards govern the determination of
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`whether a patent claim is “anticipated” by the prior art. I have applied these
`
`standards in my analysis of whether claims 9-11, 15, 17-19, 48, 51, and 52 of
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`3
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`
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`the ’311 patent (IPR2013-00064) and whether claims 23, 24, 26-40, 42-44, 46, 49,
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`50, 53, and 54 of the ‘311 patent (IPR2013-00065) were anticipated at the time of
`
`the invention.
`
`15.
`
`I understand that, for a patent claim to be “anticipated” by the prior
`
`art, each and every requirement of the claim must be found, expressly or
`
`inherently, in a single prior art reference in the manner recited in the claim.
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`16.
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`I understand that claim limitations that are not expressly found in a
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`prior art reference are inherent only if the prior art necessarily includes the claim
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`limitations.
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`B.
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`Obviousness
`
`17.
`
`I understand that a claimed invention is not patentable if it would have
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`been obvious to a person of ordinary skill in the field of the invention at the time
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`the invention was made.
`
`18.
`
`I understand that the obviousness standard is defined at 35 U.S.C. §
`
`103(a) as follows:
`
`A patent may not be obtained though the invention is not
`identically disclosed or described as set forth in section 102 of
`this title, if the differences between the subject matter sought to
`be patented and the prior art are such that the subject matter as a
`whole would have been obvious at the time the invention was
`made to a person having ordinary skill in the art to which said
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`4
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`
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`subject matter pertains. Patentability shall not be negatived by
`the manner in which the invention was made.
`
`
`I understand that the following tenets also govern the determination of
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`19.
`
`whether a claim in a patent is obvious. I have applied these standards in my
`
`consideration of whether claims 9-11, 15, 17-19, 48, 51, and 52 of the ’311 patent
`
`(IPR2013-00064) and whether claims 23, 24, 26-40, 42-44, 46, 49, 50, 53, and 54
`
`of the ‘311 patent (IPR2013-00065) would have been considered obvious at the
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`time of the invention.
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`20.
`
`I understand that obviousness may be shown by considering more
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`than one item of prior art but that the prior art must teach or suggest all the claim
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`limitations.
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`21.
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`I also understand that the relevant inquiry into obviousness requires
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`consideration of four factors:
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`1.
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`The scope and content of the prior art;
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`The differences between the prior art and the claims at issue;
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`The knowledge of a person of ordinary skill in the pertinent art;
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`2.
`
`3.
`
`and
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`4. Whatever objective factors indicating obviousness or non-
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`obviousness may be present in any particular case, such factors
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`including commercial success of products covered by the patent
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`5
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`
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`claims; a long-felt need for the invention; failed attempts by others to
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`make the invention; copying of the invention by others in the field;
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`unexpected results achieved by the invention; praise of the invention
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`by the infringer or others in the field; the taking of licenses under the
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`patent by others; expressions of surprise by experts and those skilled
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`in the art at the making of the invention; and the patentee proceeded
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`contrary to the accepted wisdom of the prior art.
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`22.
`
`I understand that for a claim to be obvious based on a combination of
`
`prior art, there must be some reason, either in the references themselves or in the
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`knowledge generally available to one of ordinary skill in the art, to modify the
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`reference or to combine such teachings. I also understand that the hypothetical
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`person of ordinary skill in the art must have had a reasonable expectation of
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`success in making such combinations or modifications. Obviousness can only be
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`established by combining or modifying the teachings of the prior art to produce the
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`claimed invention where there is some reason to do so found either explicitly or
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`implicitly in the references themselves or in the knowledge generally available to
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`one of ordinary skill in the art. “The test for an implicit showing is what the
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`combined teachings, knowledge of one of ordinary skill in the art, and the nature of
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`the problem to be solved as a whole would have suggested to those of ordinary
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`skill in the art.” In re Kotzab, 217 F.3d 1365, 1370, 55 USPQ2d 1313, 1317 (Fed.
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`6
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`
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`Cir. 2000). See also In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988);
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`In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992).
`
`23.
`
`I understand that the ’311 patent is a division of U.S. Patent
`
`Application No. 10/925,984, filed on August 26, 2004, now U.S. Patent No.
`
`7,507,991, which is a division of U.S. Patent Application No. 10/140,176, filed on
`
`May 8, 2002, now U.S. Patent No. 6,847,064, which is a division of U.S. Patent
`
`Application No. 10/011,708, filed on December 11, 2001, now U.S. Patent No.
`
`6,797,548, which is a division of U.S. Patent Application No. 09/291,279, filed on
`
`April 14, 1999, and now U.S. Patent No. 6,335,213, which is a division of U.S.
`
`Patent Application No. 09/045,696, filed on March 23, 1998, and now U.S. Patent
`
`No. 6,124,155, which is a division of U.S. Patent Application No. 08/455,067, filed
`
`on May 31, 1995, and now U.S. Patent No. 5,811,328, which is a division of U.S.
`
`Patent Application No. 08/260,751, filed on June 15, 1994, and now U.S. Patent
`
`No. 5,648,662, which is a continuation of U.S. Patent Application No. 07/895,029,
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`filed on June 8, 1992, and abandoned. The ’311 patent also claims priority to a
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`foreign patent, Japanese Patent Application No. JP 3-174541, filed on June 19,
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`1991. I have used June 19, 1991 as the “time of the invention” in my findings.
`
`C.
`
`The Person of Ordinary Skill in the Art
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`24.
`
`I believe a person of ordinary skill in the art in the field of the ’311
`
`patent would be someone with a bachelor’s degree in electrical engineering or
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`material science and five years of experience in the design, processing and
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`characterization of TFTs for LCDs, or someone with a master’s degree and
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`experience in the same.
`
`D.
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`Claim Construction
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`25.
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`I understand that generally, in a proceeding in front of the U.S. Patent
`
`Office, claims of a patent are given their broadest reasonable interpretation
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`consistent with the specification.
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`26. However, I understand that the ’311 patent expired, and that claims of
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`an expired patent are construed in accordance with the principle set forth by the
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`court in Phillips v. AWH Corp., 415 F.3d 1303, 1316 (Fed. Cir. 2005) (words of a
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`claim “are generally given their ordinary and customary meaning” as understood
`
`by a person of ordinary skill in the art in question at the time of the invention).
`
`27.
`
`I understand that in construing claims “[a]ll words in a claim must be
`
`considered in judging the patentability of that claim against the prior art.” (MPEP §
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`2143.03, citing In re Wilson, 424 F.2d 1382, 1385, 165 USPQ 494, 496 (CCPA
`
`1970)).
`
`28.
`
`I understand that extrinsic evidence may be consulted for the meaning
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`of a claim term as long as it is not used to contradict claim meaning that is
`
`unambiguous in light of the intrinsic evidence. Phillips v. AWH Corp., 415 F.3d
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`1303, 1324 (Fed. Cir. 2005) (citing Vitronics Corp. v. Conceptronic, Inc., 90 F.3d
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`8
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`
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`1576, 1583-84 (Fed. Cir. 1996)). I also understand that in construing claim terms,
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`the general meanings gleaned from reference sources must always be compared
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`against the use of the terms in context, and the intrinsic record must always be
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`consulted to identify which of the different possible dictionary meanings is most
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`consistent with the use of the words by the inventor.
`
`III.
`
` THE ’311 PATENT
`
`A.
`
`The Background of the ’311 Patent
`
`29.
`
`I have studied the ’311 patent titled “Electro-optical device and thin
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`film transistor and method for forming the same.” The ’311 patent generally
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`relates to an electro-optical device, namely a thin film transistor and methods for
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`forming the same, and in particular, the ’311 patent provides methods of forming
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`thin film transistors with “step-like” structures. The disclosed methods improve
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`over prior methods at least because they are more efficient, e.g., the disclosed
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`methods reduce the number of resist masks in forming the “step-like” structures,
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`prevent a mask misalignment, and help to control accurately the length of the
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`channel formation region.
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`30. At the time of the invention, TFTs were used to drive pixels for flat-
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`panel active matrix liquid crystal displays (AMLCDs). The TFTs act as switches
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`for charging and discharging a capacitor for each pixel. The voltage at the
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`capacitor is shared by the pixel electrode, generating an electric field across the
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`9
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`
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`liquid crystal (LC) which alters the optical properties of that pixel. In order to be
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`of practical use for this application, the TFT must demonstrate low OFF current;
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`high ON current, and therefore, a high ON/OFF current ratio; ability to transition
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`from OFF to ON at a gate voltage (VG) compatible with modern electronics; long
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`term reliability; uniform properties over a large area; and reproducible
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`performance over a series of depositions. Hydrogenated amorphous silicon (a-
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`Si:H) is a common material used to manufacture TFTs that meet these
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`requirements. See, e.g., Ex. 2012, Willem den Boer, Active Matrix Liquid Crystal
`
`Displays, Elsevier (2005).
`
`31. An advantage of amorphous silicon (a-Si) is that it can be deposited at
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`low temperature and low cost by plasma enhanced chemical vapor deposition
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`(PECVD), making it compatible with the glass substrates of AMLCDs. Once
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`deposited, the a-Si layers must be fabricated into the transistor structure. The
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`current industry standard TFT for this application consists of the “inverted-
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`staggered” structure.
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`32. Using a glass back-plane as the substrate, it consists sequentially of a
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`metal gate, a gate-insulator layer (SiNx), a layer of a-Si serving as the channel, a
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`contact layer of n+ a-Si, and metal electrodes for the source and drain (S/D). A
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`cross section of this structure is shown in the below figure. See Ex. 2012, Willem
`
`den Boer, Active Matrix Liquid Crystal Displays, Elsevier, 2005, p. 35.
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`10
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`

`

`
`
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`Cross-section schematic of a back-channel-etched inverted staggered thin film transistor.
`See Ex. 2012, Willem den Boer, Active Matrix Liquid Crystal Displays, Elsevier, 2005, p. 35.
`
`
`
`33.
`
`The n+ layer is necessary to form a good ohmic contact between the
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`metal electrodes and the channel layer to maximize the ON current. But since it is
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`conductive, the n+ layer must be removed from the channel region to obtain low
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`OFF current. This is done using a back-etch after the source and drain metals are
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`patterned. The below figures titled “BCE Structure Process Flow” illustrate the
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`process steps in TFT fabrication; the back etch is the final step. See Ex. 2013,
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`Wang et al., Cu/CuMg Gate Electrode for the Application of Hydrogenated
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`Amorphous Silicon Thin-Film Transistors, Electrochem. Solid-State Lett., vol. 10
`
`no. 8, J83-J85 (2007).
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`11
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`

`

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`
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`TFT fabrication process flow.
`See, Ex. 2013, Wang et al., Cu/CuMg Gate Electrode for the
`Application of Hydrogenated Amorphous Silicon Thin-Film Transistors,
`Electrochem. Solid-State Lett., vol. 10 no. 8, J83-J85, 2007.
`
`
`34. One critical etch in this TFT fabrication sequence is that of the n+
`
`
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`layer. Because the n+ layer is doped with phosphorus atoms, these atoms can
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`diffuse into the intrinsic a-Si layer creating a conductive channel that is always on.
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`This in turn will increase the OFF current of the TFT. This is generally overcome
`
`by overetching the n+ layer, and etching into the intrinsic a-Si layer as well. This
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`ensures that no conductive channel is present when no gate voltage is applied.
`
`35.
`
`The fabrication process for the structure shown above in paragraph 33
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`involves several steps of lithography, where a pattern is transferred onto the
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`semiconductor material, followed by deposition of metal layers to form electrical
`
`contacts. Precise control of the etching component of the lithography process is
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`12
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`

`
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`critical to the realization of the device structure, and to its reproducibility. There
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`are two types of etching in semiconductor fabrication: wet and dry.
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`36. Wet etching relies on the chemical decomposition of a material via a
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`liquid-phase etchant, e.g., a strong acid or base. Thus, an advantage of wet etching
`
`is its selectivity: the etch chemistry can be selected such that it only reacts with
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`certain materials. In lithography, the etchant is chosen so that is reacts solely with
`
`the material to be patterned and will not affect the mask. However, wet etching is
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`generally isotropic; that is, the etch rate is the same in every direction, both across
`
`the layer, and vertically down into the layer.
`
`37. Dry etching involves both a chemical and physical removal
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`(sputtering) of material, typically by a gas-phase etchant, e.g., reactive ion etching
`
`(RIE). Dry etching generally does not have the same level of selectivity as wet
`
`etching; however, directionality of the etch can be achieved via careful calibration
`
`of the etch chemistry, resulting in anisotropic etching. It is important to note that
`
`this anisotropy can be controlled by the process parameters, including pressure,
`
`power, chosen etchants, and flow rates. See Ex. 2014, H. Zou, Anisotropic Si Deep
`
`Beam Etching with Profile Control using SF6/O2 Plasma, Microsystem
`
`Technologies, vol. 10 603–607 (2004). Thus, one can select more or less
`
`anisotropy depending on the desired application. Dr. Kanicki agrees with this
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`13
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`

`
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`characterization of dry etching as shown in the following excerpt taken from the
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`transcript of Dr. Kanicki’s deposition:
`
`Q. Are the dry etches you talked about perfectly anisotropic?
`
`A. Depending on the process, desired outcome, you -- in
`certain cases you would like to have a perfectly anisotropic
`etching and perfect vertical walls that will be defined. In some
`other cases, you would like to have some lateral etching as
`well, and then -- so you can have a dry etching that will not
`be perfectly anisotropic. Depending on desired future size, on
`desire, also, future shapes that you would like to achieve, then
`you will -- you may choose perfectly anisotropic etching or you
`may choose anisotropic etching with some component of the
`isotropic etching.
`
`Q. Does the extent to which it's anisotropic depend upon the
`gas that is used?
`
`A. The gas composition during dry etching will have an
`impact on the anisotropy of the etching, yes.
`
`See Ex. 2020, Kanicki Dep., at p. 38, ll. 3-21 (emphasis added).
`
`
`38.
`
`Though the goal, as with all types of transistors, is to minimize
`
`parasitic capacitances such as Cgs, this cannot be done without penalties. It was
`
`well known at the time that the reduction and elimination of the overlap between
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`14
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`

`
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`gate electrodes and S/D electrodes leads to a problematic decrease in ON current
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`due to the introduction of series resistance. As shown in the below figure, as the
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`overlap is reduced, so is the drain current of the TFT. There comes a point where
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`the gate voltage can no longer modulate the channel (i.e., turn the TFT ON and
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`OFF) and the transistor no longer functions as a switch, but begins to function as a
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`resistor. See, e.g., Ex. 2015, Choi et al., Simple Process for Making New Self-
`
`Aligned TFT with Improved On-Current, Electrochemical Society Proceedings,
`
`Vol. 96-23, 129-137, 1997; Ex. 2016, Uchikoga et al., The Effect of Contact
`
`Overlap Distance on a-Si TFT Performance, Mat. Res. Soc. Symp. Proc., Vol. 258,
`
`1025-1030, 1992.
`
`
`
`
`
`
`Indicates the decrease in drain ON current as the gate to source overlap is reduced.
`
`See Ex. 2015, Choi et al, Simple Process for Making New Self-Aligned TFT with Improved On-
`
`Current,” Electrochemical Society Proceedings, Vol. 96-23, 129-137, 1997.
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`
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`15
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`39. When an overlap exists only between the S/D regions (n+ layer) and
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`the gate (and no overlap exists between the S/D electrodes and the gate electrode),
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`a TFT can function, though it will exhibit a problematic increase in resistance. See
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`also Ex. 2020, Kanicki Dep., at p. 72, ll. 7-12. (“A. …At least they're saying that
`
`if I have the overlap between N-plus and the gate electrode, I still have a working
`
`transistor. I do have some resistance associated with source and drain because
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`my metal is slightly recessed with the edge of the N-plus.”) (Emphasis added).
`
`B.
`
`The Invention of the ’311 Patent
`
`a)
`
`The “Step-Like” Structure
`
`40. One feature of the ’311 patent provides methods to form a structure
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`the Petitioner refers to as the “step-like” structure. The so-called “step-like”
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`structure is generally formed by a source/drain region (usually an n-type
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`semiconductor layer) extending from (or beyond) a source/drain electrode (usually
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`a metal layer). The ’311 patent not only discloses this “step-like” structure, but
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`also designs a process to accomplish it.
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`41.
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`In this regard, claims 9 and 17 describes the step-like structure by
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`reciting, “an upper portion of each of said source and drain regions extend beyond
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`a lower portion of each of said source and drain electrodes so that a distance
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`between the source and drain regions is shorter than a distance between the source
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`16
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`and drain electrodes.”1 Further, claims 23 and 27 describe the step-like structure
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`by reciting, “the conductive layer is overetched using said resist so that a distance
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`between opposed ends of the bottom surfaces of the source and drain electrodes is
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`larger than a distance between opposed ends of the bottom surfaces of the source
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`and drain regions.”2 Claims 31 and 35 similarly recite “an upper portion of each of
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`said source and drain regions extend beyond a lower portion of each of said source
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`and drain electrodes so that a distance between the source and drain regions is
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`shorter than a distance between the source and drain electrodes.”3 Claims 39 and
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`43 similarly recite “a first portion of each of the source and drain regions extend
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`beyond a lower portion of each of the source and drain electrodes so that a distance
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`1 The Petitioner labeled this limitation as 9.j and 17.k. See IPR2013-00064, Ex.
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`1014, Kanicki Decl., at page 16. For ease of reference, I will adopt the same label
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`for this limitation and refer to this limitation as 9.j and 17.k.
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`2 The Petitioner labeled this limitation as 23.f and 27.f. See IPR2013-00065, Ex.
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`1014, Kanicki Decl., at p. 93. For ease of reference, I will adopt the same label for
`
`this limitation and refer to this limitation as 23.f and 27.f.
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`3 The Petitioner labeled this limitation as 31.e and 35.e. See IPR2013-00065, Ex.
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`1014, Kanicki Decl., at p. 94. For ease of reference, I will adopt the same label for
`
`this limitation and refer to this limitation as 31.e and 35.e.
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`17
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`between the source and drain regions is shorter than a distance between the source
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`and drain electrodes.”4
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`42.
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` An example of the “step-like” structure is shown below in annotated
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`FIG. 3(G) of the ’311 patent. Annotated FIG. 3(G) illustrates a thin film transistor
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`including a source electrode (9), a drain electrode (10), a source region (11), a
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`drain region (12), an intrinsic amorphous silicon film (5), a gate insulating film (4),
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`and a gate electrode (3). The thin-film transistor is disposed on a glass substrate
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`(1) having a base film (2) disposed in between.
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`Annotated FIG. 3(G) of the ‘311 Patent.
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`
`
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`4 The Petitioner labeled this limitation as 39.e and 43.e. See IPR2013-00065, Ex.
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`1014, Kanicki Decl., at p. 95. For ease of reference, I will adopt the same label for
`
`this limitation and refer to this limitation as 39.e and 43.e.
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`18
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`43.
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`In the “step-like” structure, the source/drain regions (11, 12) extend
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`beyond the source/drain electrodes (9, 10). Thus, a portion of the source/drain
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`regions (11, 12) are not completely covered by the source/drain electrodes (9, 10).
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`44.
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` FIGS. 3 (A)-(H) of the ’311 patent (below) illustrate a method of
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`fabricating a TFT. In this example, Silicon oxide (SiO2) is deposited on a glass 1.
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`A chromium (Cr) layer 3 (the gate electrode) is formed on the base film 2. (FIG.
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`3(A)). Layer 3 is then patterned to form the gate electrode (FIG. 3(B)).
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`45. A silicon nitride film is formed as a gate insulating film 4 on the
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`chromium layer 3, and an intrinsic amorphous silicon film 5 is formed on the gate
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`insulating film 4. A doped amorphous silicon layer 6 is formed on the intrinsic
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`amorphous silicon film 5 as shown in FIG. 3(C). These layers are etched to form a
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`TFT island as shown in FIG. 3(D).
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`46. A chromium layer 7 (source and drain electrodes) is then formed by
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`sputtering on the island and the base film 2. The resulting laminate is shown in
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`FIG. 3(E). A resist layer 8 is disposed on the chromium layer 7 (source and drain
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`electrodes) and patterned. Using the resist layer 8, the chromium layer 7 and the
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`doped amorphous silicon layer 6 are etched in the channel area, forming a source
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`electrode 9, a drain electrode 10, a source region 11, and a drain region 12 as
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`shown in FIG. 3(F).
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`19
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`47.
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`The chromium layer 7 (used to form the source and drain electrodes)
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`is wet-etched without peeling off the resist 8, rendering the distance between the
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`resulting source and drain electrodes (9 and 10) larger than the distance between
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`the source and drain regions (11 and 12) as shown in FIG. 3(G).
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`48. At FIG. 3(H), silicon oxide (SiO2) 13 is deposited as a passivation
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`film on the device shown in FIG. 3(G).
`
`49.
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` The method to form the thin film transistor is shown in FIGS. 3(A)-
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`3(H).
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`
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`One fabrication process disclosed in the ’311 patent.
`See FIGS. 3(A) -3(H) in the’311 patent.
`
`
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`20
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`b)
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`Etching to form Source and Drain Regions “without
`Removing said Resist” and “Using said Resist”
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`50. Another one of the features of the ’311 patent is to reduce the number
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`of resist masks used in the process. In this regard, claim 9 provides “etching a
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`portion of said conductive layer to form source and drain electrodes using a resist
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`formed by a second photomask; etching a portion of the patterned N-type
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`semiconductor film to form source and drain regions by dry etching without
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`removing said resist.”5 The “said resist” is the resist mask used to form the source
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`and drain electrodes as well as the n+ source and drain regions. Similar limitations
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`are also recited in elements (b) and (c) of claims 23, 31, and 39 of the ‘311 patent.
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`51.
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`Therefore, claim 9 (and claims 23, 31, and 39) of the ’311 patent
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`requires that the photo resist layer used for patterning the source and drain
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`electrodes not be removed before patterning the source and drain regions.
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`52.
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`Similarly, claim 17 provides “etching a portion of said conductive
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`layer to form source and drain electrodes using a resist formed by a second
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`photomask; etching a portion of the patterned N-type semiconductor film to form
`
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`5 The Petitioner labeled this limitation as 9.h. See IPR2013-00064, Ex. 1014,
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`Kanicki Decl., at page 15. For ease of reference, I will adopt the same label for
`
`this limitation and refer to this limitation as 9.h.
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`21
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`source and drain regions using said resist.”6 The “said resist” is likewise the resist
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`mask used to form the source and drain electrodes as well as the source and drain
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`regions (n+ layer). Similar limitations are recited in elements (b) and (c) of claims
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`27, 35