SEL EXHIBIT NO. 2008
`INNOLUX CORP. v. PATENT OF SEMICONDUCTOR ENERGY
`LABORATORY CO., LTD.
`
`IPR2013-00064
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`

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`-Y
`
`APPLIED PHYSICS LETTERS
`
`pwdDuL
`wman
`PAT';
`VOLUME 72, NUMBER 21rr' (!l4E U '
`
`1 JUNE 1998
`
`Investigation of intrinsic channel characteristics of hydrogenated
`amorphous silicon thin-film transistors by gated-four-probe structure
`Chun-sung Chiang, Chun-ying Chen,
`and Jerzy Kanickib)
`Center for Display Technology and Manufacturing, Department of Electrical Engineering and Computer
`Science, University of Michigan, Ann Arbor, Michigan 48109
`Kazushige Takechi
`NEC Corp., Functional Devices Researh Laboratories, Kawasaki, Kanagawa, Japan
`
`(Received 17 November 1997; accepted for publication 2 April 1998)
`
`We use a new hydrogenated amorphous silicon (a-Si:H) device structure, the gated-four-probe
`a-Si:H thin-film transistor
`to investigate the intrinsic
`characteristics of
`channel
`(TFT),
`inverted-staggered a-Si:H TFTs without the influence of source/drain series resistances. The
`experimental results have shown that, for the conventional a-Si:H TFT structure, the field-effect
`mobility, threshold voltage, and field-effect channel conductance activation energy have a strong
`dependence on a-Si:H thickness and TFT channel length. On the other hand, for
`the
`gated-four-probe a-Si:H TFT structure, these values are a-Si:H thickness and TFI' channel length
`independent, clearly indicating that this new a-Si:H TFT structure can be effectively used to
`measure the channel intrinsic properties of a-Si:H TFTs. © 1998 American Institute of Physics.
`[S0003-6951 (98)04622-1]
`
`Among the existing hydrogenated amorphous silicon
`(a-Si:H) thin-film transistor (TFT) structures the n-channel
`inverted-staggered TFT structure is the most popular in
`active-matrix liquid-crystal displays (AMLCDs) and image
`sensors.' In this n-channel inverted-staggered TFT structure,
`the gate electrode is separated from the source and drain
`electrodes by a gate insulator (amorphous silicon nitride), an
`intrinsic a-Si:H, and a phosphorus-doped (n+) a-Si:H
`layer. Under a positive above-threshold gate bias, an accu-
`mulation layer of electrons is induced to form a conducting
`the
`a-Si:Wamorphous
`silicon
`channel
`near
`nitride
`(a-SiNs: H) interface. Because of such inverted-staggered
`structure, the electrical performance of a-Si:H TFTs is deter-
`mined by two factors: the intrinsic channel characteristics
`and parasitic series resistances. The characteristics of the in-
`trinsic channel are mainly determined by the electronic qual-
`ity of a-Si:Wa-SiN:H interface, a-Si:H bulk, and back-
`channel interface. On the other hand, the properties of
`parasitic resistances are affected by the quality of contacts
`between source/drain metal and n+ a-Si:H, intrinsic a-Si:H
`and n+ a-Si:H film thickness, and gate-to-source/drain elec-
`trode overlap. The existence of parasitic series resistances
`makes it difficult to accurately determine a-Si:H TFT intrin-
`sic characteristics such as field-effect mobility (,apE) and
`threshold voltage (VT) for optimized a-Si:H bulk material
`and a-Si:HJa-SiN:H interface. To study the intrinsic per-
`formance of a-Si:H TFTs, the effects of source/drain series
`resistances must be excluded.
`We previously reported a new structurethe gated-four-
`probe (GFP) a-Si:H TFTto accurately measure the intrin-
`sic characteristics of a-Si:H TFTs.2 In the GFP a-Si:H TEl'
`structure, two additional narrow probes are placed between
`the source and drain electrodes of a conventional inverted-
`
`'1Prent address: Motorola Inc., Tempe, Arizona.
`'Correspondlng author, electronic mail: kanlckl@eecs.umich.edu
`
`staggered a-Si:H TFT to sense the voltage difference along
`the conducting channel, By correlating this voltage differ-
`ence with the source/drain current induced by the applied
`gate bias, the a-Si:H TFT intrinsic channel characteristics for
`electron conduction can be measured without the influence
`of source/drain series resistances. In a previous study,3 we
`employed a two-dimensional device simulator to predict the
`electrical characteristics of the new GFP a-Si:H TFT struc-
`ture. The simulation results indicated that the effect of series
`resistances can be excluded in GFP a-Si:H TFTs, and deter-
`mination of the intrinsic characteristics of a-Si:H TFTs is
`possible with this new structure
`In this letter, we present experimental results for conven-
`tional inverted-staggered and GFP a-Si:H TETs structures,
`which were fabricated at the same time on glass substrates
`(Corning 7059F). A 1500 A thick chromium (Cr) layer was
`first deposited by sputtering and patterned to form the gate
`electrode. Following the gate electrode formation, a 3000 A
`thick a-SiN5: H gate insulator, intrinsic a-Si:H channel layer
`(having thicknesses of 1500 and 3000 A). and 500 A thick
`n+ a-Si:H layer were deposited consecutively by plasma-
`enhanced chemical vapor deposition. A 2000 A thick Cr
`layer was then deposited by sputtering and patterned as
`source/drain electrodes and, for GFP TFTs, two additional
`narrow probes have been added. After the source/drain/probe
`patterning, a dry back-channel-etch process was used to re-
`move the n+ a-Si:H using the patterned source/drain elec-
`trodes as the mask. To insure complete removal of n+
`a-Si:H in the channel region, an over-etch process was used
`to etch off approximately 200 A of intrinsic a-Si:H layer
`within the channel.
`An HP4156A semiconductor parameter analyzer was
`used to measure the current-voltage (I- P characteristics at
`different temperatures. For the a-Si:H TFT, the gradual
`channel approximation equation in the linear region, G
`= IDL/ WVD ILPECJ( VGS Vr), was used for
`FE and VT
`
`0003-6951/99/72(22)/2874/3/$1 5.00
`
`2874
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`© 1998 American Institule of Physics
`
`

`

`Appi. Phys. Left., Vol. 72, No. 22, 1 June 1998
`
`Chiang et at.
`
`2875
`
`300
`
`a-SiNx:H' 3000A,V0=0.IV
`a-Si: H
`solid symbol 1500 A
`- open symbol 3000 A
`
`a
`
`a
`
`0
`
`-5
`
`0
`10
`5
`15
`(VraVt) or (V0;-;) (V)
`
`20
`
`0
`
`5
`
`10
`IS
`V65 or v0; (V)
`
`20
`
`FIG. 2. Sheet conductance vs effective gate voltage characteristics for con-
`ventional a-Si:H TFT and GFP a-Si:H TFT structures having different
`channel lengths. a-Si:H and a-SiN:H films are both about 3000 A thick.
`
`length TFT. Again, this is due to the effect of source/drain
`series resistances, which becomes stronger in a-Si:H TFTs
`with shorter channel lengths.4 For GFP a-Si:H TFTs, no sub-
`stantial channel length dependence is observed in the C'
`- V5 characteristics. Figure 3 shows the evolution of the
`field-effect mobilities and threshold voltages, extracted from
`Fig. 2, with channel lengths for both conventional a-Si:H
`TFTs and GFP a-Si:H TFTs. As predicted by the numerical
`simulation,3 no dependence on channel length is observed for
`GFP a-Si:H TFTs. For a-Si:H TFTs, a strong dependence on
`channel length is observed, where longer channel length de-
`vices have higher extracted field-effect mobilities. This result
`clearly illustrates that the GFP a-Si:H TFT structure can ef-
`fectively eliminate the effect of series resistances and pro-
`vide the intrinsic device properties.
`The field-effect channel conductance activation energy
`(EA) is associated with the position of the Fermi level (EF)
`in a-Si:H that can be changed by gate biases, Its evolution
`with Vs was used to calculate the density of states in a-Si:H
`TFTs,5 Therefore, it is critical to know the exact EA values at
`different gate biases. As shown above, the series resistance
`has a significant effect on the overall source-to-drain conduc-
`tion characteristics, especially for shorter channel length
`TFTs. It is expected, therefore, that series resistances will
`influence the determination of EA values, and the extent of
`that influence depends on the a-Si:H film thickness and the
`channel length.6 Figure 4 shows the evolution of E4 with
`
`80
`
`60
`
`40
`L or L' (jim)
`
`0
`
`20
`
`1.0
`
`0.8
`
`0.6
`
`0A
`
`0.2
`
`0.0
`
`0C
`
`)
`
`FIG. 3. Evolution of ihe field-effect mobility and threshold voltage as a
`function of channel length that were extracted from Fig. 2.
`
`FIG. 1. Sheet conductance vs effective gate voltage characteristics for con-
`ventional a-Sl:1-1 TFF and GFP a-Sl:H TFT structures having two different
`a-Sl:H layer thicknesses. (W/L) for the conventional a-Si:H TFT and GFP
`a-Si:H TFF are (56/16) and (100/20), respectIvely. V, (1500 A)5.8 V and
`2.5 V. Thickness of gate Insulator (a-SiNs :H) is fixed at
`14 (3000 A)
`3000 A.
`
`extraction, where C is the normalized channel conductance,
`C1 is the geometrical capacitance of the gate insulator, V is
`the applied gate bias, and Wand L are the channel width and
`length. For the GFP a-Si:H TFT structure, the device char-
`acteristics can be expressed as C' = IDL'f W( 13
`VA)
`= C,ILFE( V VT), where C' is the effective normalized
`channel conductance, VA and 11B are the electrical potential
`for the two inner probes, V5= VGS (VB+ VA)12 is the ef-
`fective gate bias, and L' = (XB XA) is the effective channel
`length. Since probes A and B only sense the electrical poten-
`tial, VA and 11B represent the true channel electrical potential.
`Hence, by using the GFP a-Si:H TFT structure, intrinsic
`field-effect mobility and intrinsic threshold voltage can be
`extracted from this equation without the influence of source!
`drain series resistances. The field-effect channel conductance
`activation energy (EA) at different gate voltages was ob-
`tained from the slope of the Arrhenius ln(G) vs r1 plot, as
`C= Coexp(EA/k2J, where C0 is a constant, k is the Bolt-
`zmann constant, and T is the absolute temperature.
`Figure 1 shows the C Vs and C' - V5 characteristics
`in the linear region obtained for both a-Si:H TFT and GFP
`a-Si:H TFT structures having a-Si:H layers 1500 and 3000
`A thick. By fitting the experimental data to the above equa-
`tions, we obtained for GFP a-Si:H TFTs the intrinsic field-
`effect mobility of about 0.85 cm2N s. An effective gate bias,
`VGS VT or V5 V-, was used in Fig. Ito offset the effect
`of back-interface defect states on the threshold voltage; VT is
`2.5 and 6 V for TFTs with 3000 and 1500 A a-Si:H films,
`respectively. As can be seen in Fig. 1, a thicker a-Si:H layer
`(3000 A) causes a stronger reduction in the source-drain con-
`ductance of a-Si:H TFTs at higher gate voltages, indicating
`that a thicker a-Si:H layer introduces a higher device series
`resistance. However, for GFP a-Si:H TFTs, the C' - ( V5
`- VT) characteristics are nominally independent of a-Si:H
`film thickness, indicating that the effect of TFT series resis-
`tances has been excluded in this structure, which is consis-
`tent with the simulated data.3
`The C Vcs and C VE5 characteristics for a-Si:H
`TFTs and GFP a-Si:H TFTs having different channel lengths
`(L or L') are shown in Fig. 2. For a-Si:H TFTs in the linear
`region, a lower conductance is observed for a shorter channel
`
`

`

`2876
`
`AppI. Phys. Lett., Vol. 72, No. 22, 1 June 1998
`
`Chiang et aL
`
`4. On the other hand, for a GFP a-Si:H TFT with different
`channel lengths (10, 30, and 90 jim), the BA value decreases
`with increasing effective gate bias, which indicates that EF
`approaches the conduction band-edge as gate-bias increases.
`In addition, BA values extracted for GFP TFTs do not depend
`on channel length (see inset of Fig. 4). This observation is
`consistent with theoretical calculation,3 since the effect of
`source/drain series resistances have been excluded in this
`structure. Hence, the EA value obtained for GFP a-Si:H
`TFTs represents the true intrinsic BA value that can be used
`to characterize the quality of a-Si:H TFT channel (including
`the a-Si;l-1Ja-SiN;H interface).
`In this letter we have shown the experimental results for
`GFP a-Si:H TFTs that confirm our previous numerical
`simulation3 indicating that GFP a-Si:H TFTs are immune to
`the influence of source/drain series resistances. This work
`clearly demonstrates that the GFP a-Si:H TFT structure is a
`veiy useful tool for optimization and control of the intrinsic
`performance of a-Si:H TFTs during AMLCD fabrication.
`
`The authors would like to thank the Center for Display
`Technology and Manufacturing at the University of Michi-
`gan for its financial support and the NEC Functional Devices
`Research Laboratories for its assistant in PECVD film depo-
`sition. The GFP a-Si:H TFT structure was developed and
`fabricated at the University of Michigan.
`
`'M, J. Powell, IEEE Trans. Electron Devices 36. 2915 (1989).
`2c.-y. Chen and J. Kanicld, IEEE Electron Device Len. 18, 340 (1997).
`3C.-Y. Chen and J. Kanicki, SPIE Proc. 3014, 30 (1997).
`4J. Kanicki, F. R. Llbsch, J. Griffith, and Il. Polastre, J. AppI. Phys. 69.
`2339 (1991).
`5R. E. 1. Schropp, J. Snljder, and J. F. Verwey, J. AppI. Phys, 60, 643
`(1986),
`°C.-Y. Chen and J. Kanickl, Solid-State Electron. 42, 705 (1998).
`
`o-SiHTFt
`OFPWT
`
`0
`
`20
`
`08
`80
`L08LPmp
`
`PS
`
`L (pm)
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`L'Qtm)= 19.30.90,
`20
`10
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`
`FIG. 4. Evolution of the channel conductance activation energy as a func-
`tlon of gate voltages for conventional a-Sl:i-i TFI' and GFP a-SI:!-! TFF
`structures. The channel length for a-Si:H TFTs is 6 m (), 16 jm (A), 36
`zm (V) and 96 /.cm (+); channel length for GFP TFI's is 10 jan (0), 30
`jzm (0), and 96 jan (+). Channel widths for a-Sl:H TFF and GFP TFT are
`60 and 100 jan, respectively. Thickness of a-Sl:1-1 layer is 3000 A. EA at
`VGS (or V'05) = 20 V as a function of channel length Is shown in the inset.
`
`VGS obtained for a-Si:H TFT and GFP a-Si:I-1 TFT struc-
`tures, where a-Si:H thickness is 3000 A. At a higher gate
`bias (l'cs=2O V), the extracted BA values are 0.23, 0.19,
`0.14, and 0.10 eV for a-Si:H TFTs with channel lengths of 6,
`16, 36, and 96 jim, respectively. For V5 above the threshold
`voltage, EA increases with increasing Vs for a short channel
`length TFT (L= 6 jim), while it saturates at higher VG5 for a
`longer channel TFT (L=96 jim). This channel-length de-
`pendence of EA is mainly due to the increasing influence of
`series resistances on TFT conductioi characteristics with de-
`creasing channel length and increasing gate voltage; varia-
`tion of EA with L at Vcs=2O V is shown in the inset of Fig.
`
`