IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`
`
`
`
`
`
`Trial No.:
`
`
`
`
`
`
`
`
`
`
`IPR 2012-00042
`
`
`
`
`Inventors:
`
`For:
`
`
`
`In re U.S. Patent No. 6,240,376
`Application No.:
`09/127,587
` Filed:
`July 31, 1998
` Issued:
`May 29, 2001
`
`Alain Raynaud
`Luc M. Burgun
`
`Patent Owner: Mentor Graphics
`Corporation
`
`METHOD AND
`APPARATUS FOR GATE-
`LEVEL SIMULATION OF
`SYNTHESIZED
`REGISTER TRANSFER
`LEVEL DESIGNS WITH
`SOURCE-LEVEL
`DEBUGGING
`
`Atty. Dkt. No.
`
`
`007121.00004
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Mail Stop PATENT BOARD
`Patent Trial and Appeal Board
`United States Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`PRELIMINARY RESPONSE BY PATENT OWNER
`UNDER 37 C.F.R. § 42.107
`
`
`
`
`
`
`

`

`Preliminary Response By Patent Owner
`
`
`
`IPR 2012-00042
`
`TABLE OF CONTENTS
`
`The Requested Inter partes Review Is Barred Under 35 U.S.C. § 315(b) ...... 1
`Background, Including Service Of Complaint On EVE In 2006
`A.
`Asserting Infringement of the ‘376 Patent ............................................ 2
`B.
`EVE and Synopsys Are In Privity ......................................................... 5
`There Is No Reasonable Likelihood of Petitioner Prevailing As To A
`II.
`Challenged Claim of the `376 Patent ............................................................... 9
`A.
`Technology Background ....................................................................... 9
`Introduction To and Overview of Patent Owner’s Response To
`B.
`Petitioner’s Invalidity Arguments ....................................................... 12
`Patent Owner’s Response To Petitioner’s Unpatentability
`Arguments ........................................................................................... 15
`1.
`There Is No Reasonable Likelihood of Any of Claims 1-
`5, 8-10, 20-24, 28 and 32-33 Being Found to be
`Anticipated by Koch (SYNOPSYS 1004) ................................ 15
`There Is No Reasonable Likelihood of Any of Claims 11
`and 25-27 Being Found to be Rendered Obvious by Koch
`(SYNOPSYS 1004) in View of Koch 1995 (SYNOPSYS
`1006) ......................................................................................... 27
`There Is No Reasonable Likelihood of Any of Claims 1-
`9, 11-14, 24-25 and 28-33 Being Found to be Anticipated
`or Rendered Obvious by Gregory (SYNOPSYS 1007) ............ 30
`There Is No Reasonable Likelihood of Any of Claims 10,
`15, 20-23 and 26-27 Being Found to be Rendered
`Obvious by Gregory (SYNOPSYS 1007) in view of
`Koch 1995 (SYNOPSYS 1006) ................................................ 36
`There Is No Reasonable Likelihood of Any of Claims 1,
`2, 5, 10-11 and 28 Being Found to be Anticipated Or
`Rendered Obvious by
`the HDL-ICE Brochure
`(SYNOPSYS 1009) .................................................................. 40
`There Is No Reasonable Likelihood of Any of Claims 1,
`2, 5, 10 and 28 Being Found to be Anticipated Or
`Rendered Obvious by Sample (SYNOPSYS 1010) ................. 43
`
`C.
`
`I.
`
`
`
`2.
`
`3.
`
`4.
`
`5.
`
`6.
`
`i
`
`

`

`Preliminary Response By Patent Owner
`
`
`
`IPR 2012-00042
`
`7.
`
`There Is No Reasonable Likelihood of Claim 11 Being
`Found to be Rendered Obvious by Sample (SYNOPSYS
`1010) in View of Koch 1995 (SYNOPSYS 1006) ................... 46
`III. Conclusion ..................................................................................................... 46
`
`
`
`
`ii
`
`
`
`

`

`Preliminary Response By Patent Owner
`
`
`
`IPR 2012-00042
`
`EXHIBIT LIST
`First Amended Complaint in Mentor Graphics Corp. v. EVE-
`USA, Inc. and Emulation and Verification Engineering, SA,
`6:06-CV-00341-AA (D. OR., filed March 13, 2006)
`
`Defendants’ Unopposed Motion By Special Appearance For
`Extension Of Time To Respond To Plaintiff’s First Amended
`Complaint in Mentor Graphics Corp. v. EVE-USA, Inc. and
`Emulation and Verification Engineering, SA, 6:06-CV-00341-
`AA (D. Or., filed May 23, 2006)
`
`Order of Dismissal in Mentor Graphics Corp. v. EVE-USA, Inc.
`and Emulation and Verification Engineering, SA, 6:06-CV-
`00341-AA (D. Or., filed November 20, 2006)
`
`Complaint for Declaratory Judgment and Injunctive Relief in
`Synopsys, Inc., EVE-USA, Inc. and Emulation and Verification
`Engineering, S.A. v. Mentor Graphics Corp., 3:12-cv-050025-
`LB (N.D. Cal., filed September 27, 2012)
`
`Banner & Witcoff, Ltd.’s “Messenger Log”
`
`October 4, 2012 Synopsys Press Release “Synopsys Acquires
`EVE”
`
`EVE-USA’s Supplemental Corporate Disclosure Statement,
`Docket No. 7, Synopsys, Inc. et al. v. Mentor Graphics Corp.,
`3:12-CV-05025-MC (N.D. Cal. filed October. 26, 2012)
`
`Jansen, D., The Electronic Design Automation Handbook,
`Kluwer Academic Publishers, 2003, Chapter 2
`
`Bhatnagar, Advanced ASIC Chip Synthesis: Using Synopsys®
`Design Compiler™ and PrimeTime®, Kluwer Academic
`Publishers, 1999
`
`Gregory et al. U.S. Patent No. 5,937,190
`
`iii
`
`MG 2001
`
`
`MG 2002
`
`
`MG 2003
`
`
`MG 2004
`
`
`MG 2005
`
`MG 2006
`
`
`MG 2007
`
`
`MG 2008
`
`
`MG 2009
`
`
`MG 2010
`
`
`
`
`

`

`Preliminary Response By Patent Owner
`
`
`
`IPR 2012-00042
`
`MG 2011
`
`
`
`
`
`
`
`HDL Compiler™ for VHDL User Guide, Version F-2011.09-
`SP4, March 2012, SYNOPSYS, Section 4
`
`iv
`
`

`

`Preliminary Response By Patent Owner
`
`
`
`IPR 2012-00042
`
`
`
`PRELIMINARY RESPONSE BY PATENT OWNER
`UNDER 37 C.F.R. § 42.107
`
`Patent Owner Mentor Graphics Corporation (hereinafter “Patent Owner”)
`
`hereby respectfully submits this Preliminary Response to the Petition seeking inter
`partes review in this matter. This filing is timely under 35 U.S.C. § 313 and 37
`C.F.R. §42.107, as it is being filed within three months of the September 28, 2012
`mailing date of the Notice granting the Petition a filing date of September 26,
`2012.
`
`
`A trial should not be instituted in this matter for the following reasons:
`1. Institution of an inter partes review trial on the basis of the Petition filed by
`petitioner Synopsys, Inc. is barred under 35 U.S.C. § 315(b), since more
`than one year prior to the filing of the Petition requesting the proceeding,
`Patent Owner served a complaint alleging infringement of subject U.S.
`Patent No. 6,240,376 (hereinafter “the `376 patent”) on privies of Petitioner,
`EVE-USA, Inc. and Emulation and Verification Engineering, S.A.
`2. None of the references relied upon by Petitioner in its Petition gives rise to a
`reasonable likelihood of Petitioner prevailing with respect to a challenged
`claims of the `376 patent, as required for the grant of a petition for inter
`partes review under 35 U.S.C. § 314(a).
`
`I.
`
`The Requested Inter partes Review Is Barred Under 35
`U.S.C. § 315(b)
`
`Inter partes review cannot be instituted on Synopsys’ Petition because
`
`institution by the Director is barred by 35 U.S.C. §315(b). Synopsys is the parent
`company of Emulation and Verification Engineering S.A. and EVE-USA Inc.
`(together, “EVE”). EVE was sued for infringement of the ’376 Patent in 2006.
`Section 315(b) prevents a petitioner “or privy of the petitioner” from obtaining
`
`
`
`1
`
`

`

`Preliminary Response By Patent Owner
`
`
`
`IPR 2012-00042
`
`inter partes review if the petitioner or its privy was served with a complaint
`alleging infringement of the patent-at-issue more than a year before the request.
`Inter partes review is barred for EVE – the defendant in the 2006 infringement
`litigation – and for Synopsys, who is in privity with EVE. EVE is a privy of
`Synopsys because EVE is a wholly owned subsidiary of Synopsys and they share
`common legal and property interests. The Director cannot institute inter partes
`review of the ’376 Patent because EVE is a privy of Synopsys.
`Section 315(b) imposes a statutory bar against inter partes review initiated
`
`by certain parties:
`
`An inter partes review may not be instituted if the petition requesting
`the proceeding is filed more than 1 year after the date on which the
`petitioner, real party in interest, or privy of the petitioner is served
`with a complaint alleging infringement of the patent. The time
`limitation set forth in the preceding sentence shall not apply to a
`request for joinder under subsection (c).
`
`There is no doubt that a petition for inter partes review filed by EVE could not be
`instituted because more than one year – indeed, over six years – have passed since
`EVE was served with a complaint alleging infringement of the ’376 Patent. EVE’s
`corporate parent, Petitioner Synopsys, is also precluded.
`
`A.
`Background, Including Service Of Complaint On EVE In 2006
`Asserting Infringement of the ‘376 Patent
`
`The litigation between Mentor Graphics and EVE regarding the ’376 Patent
`
`occurred in 2006. EVE and Synopsys were separate companies until the autumn of
`2012. The relevant events in the 2006 litigation and the relationship between
`Synopsys and EVE are set forth below.
`
`
`
`2
`
`

`

`Preliminary Response By Patent Owner
`
`
`
`IPR 2012-00042
`
`• May 19, 2006: Mentor Graphics asserts that EVE’s ZeBu line of
`emulators infringe the ’376 Patent in a First Amended Complaint in Civil
`Action No. 6:06-CV-00341-AA in the District of Oregon. See First
`Amended Complaint in Mentor Graphics Corp. v. EVE-USA, Inc. and
`Emulation and Verification Engineering, SA, 6:06-CV-00341-AA (D.
`OR., filed March 13, 2006) (MG 2001).1
`• December 2006: The 2006 Action is dismissed pursuant to a settlement
`agreement. See Order of Dismissal in Mentor Graphics Corp. v. EVE-
`USA, Inc. and Emulation and Verification Engineering, SA, 6:06-CV-
`00341-AA (D. Or., filed November 20, 2006) (MG 2003).
`• September 27, 2012:
`o Synopsys and EVE enter into an agreement for Synopsys to
`acquire EVE. See Complaint for Declaratory Judgment and
`Injunctive Relief in Synopsys, Inc., EVE-USA, Inc. and Emulation
`and Verification Engineering, S.A. v. Mentor Graphics Corp.,
`3:12-cv-050025-LB (N.D. Cal., filed September 27, 2012) (MG
`2004) at ¶ 13.
`o Synopsys and EVE file a Complaint in the Northern District of
`California for declaratory judgment of invalidity and non-
`infringement of the ’376 Patent in regards to EVE’s ZeBu line of
`
`
`1 Service of the First Amended Complaint on EVE, as of May 23, 2006, is reflected
`by “Defendants’ Unopposed Motion By Special Appearance For Extension of
`Time To Respond To Plaintiff’s First Amended Complaint” filed May 23, 2006 in
`the 2006 litigation (MG 2002).
`
`
`
`3
`
`

`

`Preliminary Response By Patent Owner
`
`
`
`IPR 2012-00042
`
`emulation products. See 2012 Declaratory Judgment Complaint
`(MG 2004).
`o Synopsys serves the Petition for inter partes review of the ’376
`Patent on Mentor Graphics.2
`• October 4, 2012: Synopsys completes the acquisition of EVE and EVE
`becomes a wholly owned subsidiary of Synopsys.3 See October 4, 2012
`Synopsys Press Release “Synopsys Acquires EVE” (MG 2006).
`• December 31, 2012: With the filing of this Preliminary Response, the
`earliest possible date on which an inter partes review could be instituted
`
`2 On September 27, 2012, Synopsys served the petition on the ‘376 Patent’s PTO
`correspondence address of record, making September 27, 2012, the effective
`filing date pursuant to 37 C.F.R. §§ 42.105(a) and 42.106, rather than the
`September 26, 2012 filing date accorded to the Petition by the PTAB. Receipt of
`the Petition at the correspondence address of record is shown by Banner &
`Witcoff’s “Messenger Log” (MG 2005) (See 5th entry dated September 27, 2012,
`indicating “Mentor Graphics.”) The petition is dated September 26, 2012, the
`date Synopsys unsuccessfully attempted to serve the petition by hand on an
`incorrect address.
`3 EVE-USA is a wholly owned subsidiary of Emulation and Verification
`Engineering S.A. Emulation and Verification Engineering S.A. is owned by
`Synopsys Global Licensing and Distribution Limited Liability Company.
`Synopsys Global Licensing and Distribution Limited Liability Company is owned
`by Synopsys Ireland Limited. Synopsys Ireland Limited is owned by Petitioner
`Synopsys. See EVE-USA’s Supplemental Corporate Disclosure Statement,
`Docket No. 7, Synopsys et al. v. Mentor Graphics, No. 3:12-CV-05025-MC (N.D.
`Cal. filed Sept. 27, 2012) (MG 2007).
`
`
`
`4
`
`

`

`Preliminary Response By Patent Owner
`
`
`
`IPR 2012-00042
`
`by the Director (if the Petitioner was not barred by § 315(b)). 35 U.S.C.
`§ 314(b).
`
`EVE and Synopsys Are In Privity
`
`B.
`In the context of § 315(b), “[a] ‘privy’ is a party that has a direct relationship
`
`to the petitioner with respect to the allegedly infringing product or service.” 157
`Cong. Rec. S5432 (daily ed. Sept. 8, 2011) (statement of Sen. Schumer);4 see also
`157 Cong. Rec. S1376 (daily ed. Mar. 8, 2011) (statement of Sen. Kyl) (“privity is
`an equitable rule that takes into account the ‘practical situation,’ and should extend
`to parties to transactions and other activities relating to the property in
`question.”). At a minimum, privies include those who would be subject to
`collateral estoppel based on a determination in the previous litigation. Office
`Patent Trial Practice Guide (“OPTPG”) at 16-17 (Fed. Reg. 48756, 48759)
`(quoting 154 Cong. Rec. S9987 (daily ed. Sept. 27, 2008) (statement of Sen. Kyl)).
`The term is given a broader scope in 35 U.S.C. § 315(b) than its traditional
`meaning. Id. (“The word ‘privy’ has acquired an expanded meaning”).
`
`The courts, in the interest of justice and to prevent expensive litigation, are
`striving to give effect to judgments by extending ‘privies’ beyond the classical
`description.”) (quoting 154 Cong. Rec. S9987 (daily ed. Sept. 27, 2008) (statement
`of Sen. Kyl) (citing Cal. Physicians’ Serv. v. Aoki Diabetes Research Inst., 163
`Cal. App. 4th 1506 (Cal. App. 2008)). For example, privies could include
`customers of a petitioner. 157 Cong. Rec. S5432 (daily ed. Sept. 8, 2011)
`(statement of Sen. Schumer) (“With the addition of the word ‘privy,’ a company
`
`
`4 The terms “privy” and “privity” are defined in the Office Patent Trial Practice
`Guide (“OPTPG”) primarily by reference to the legislative history of the America
`Invents Act. OPTPG at 16-17 (77 Fed. Reg. 48756, 48759).
`
`
`
`5
`
`

`

`Preliminary Response By Patent Owner
`
`
`
`IPR 2012-00042
`
`could seek a section 18 proceeding on the basis that customers of the petitioner had
`been sued for [or accused of] infringement.”)
`
`Synopsys and EVE have acknowledged that Synopsys and EVE each have a
`“direct relationship” to the property in question in the 2006 litigation: the EVE
`ZeBu family of emulators. The September 27, 2012 Complaint for declaratory
`judgment filed jointly by EVE and Synopsys states:
`
`[I]n the immediate future, Plaintiffs [EVE and Synopsys] will be
`using, importing, selling, offering for sale and/or supporting the ZeBu
`Products in the United States, which line of products was previously
`accused by Mentor Graphics of infringing the …[’376 Patent] and
`which products share structures and functionality that Mentor
`Graphics alleged are relevant to the claims of the … [’376 Patent].5
`
`Complaint (MG 2004) at ¶ 13. The common interest held by Synopsys and EVE in
`the importation, manufacture, use, and sale of the ZeBu products, and the nature of
`Synopsys’ acquisition of EVE, establish privity between Synopsys and EVE.
`Synopsys has a direct relationship to EVE with respect to the ZeBu products – the
`allegedly infringing product. And under the broad meaning that Congress
`intended, Synopsys’ ownership of, control of, and common interests with EVE
`establish privity between Synopsys and EVE.6
`
`
`5 The reference in the Complaint (MG 2004) to prior allegations by Mentor
`Graphics relates to the 2006 litigation. See First Amended Complaint (MG
`2001).
`
`6 Since Synopsys and EVE share a common interest, EVE may be a real party in
`interest in this inter partes review. But because EVE and Synopsys are clearly in
`
`
`
`6
`
`

`

`Preliminary Response By Patent Owner
`
`
`
`IPR 2012-00042
`
`The term “privity” was traditionally used for a set of substantive legal
`
`relationships between a party to a judgment and a nonparty that was to be bound by
`that judgment. Taylor v. Sturgell, 553 U.S. 880, 894 (2008) (“Qualifying
`relationships include, but are not limited to, preceding and succeeding owners of
`property, bailee and bailor, and assignee and assignor.”) The meaning has
`expanded to include all of the reasons that collateral estoppel may apply to a
`nonparty. Id. at 894 fn. 8; OPTPG at 16-17 (quoting 154 Cong. Rec. S9987 (daily
`ed. Sept. 27, 2008) (statement of Sen. Kyl) (citing Cal. Physicians’ Serv., 163 Cal.
`App. 4th 1506)). But even under the most restrictive meaning of “privity,” EVE
`and Synopsys are in privity as predecessor and successor in interest in the rights to
`import, make, use, and sell the ZeBu line of emulators.
`
`In 2006, EVE was the sole owner of all rights in the ZeBu line of products.
`Any interest Synopsys holds today is derived from its acquisition of EVE.7 The
`Supreme Court has explained that the binding of succeeding owners of property
`rights to the decisions affecting preceding owners of the same property rights
`“originated as much from the needs of property law as from the values of
`preclusion by judgment.” Taylor, 553 U.S. at 894 (quoting 18A C. Wright, A.
`Miller, & E. Cooper, Federal Practice and Procedure § 4448, p. 329 (2d ed. 2002)).
`Thus, the Federal Circuit has held that because a party’s predecessors-in-interest
`were parties to a decision by a government agency, that party was “bound by the
`
`
`privity, the Board need not reach the question of whether EVE is a real party in
`interest.
`
`7 Synopsys asserts that it holds at least a sufficient interest in importing, making,
`using, and selling ZeBu products that it has standing to file a declaratory
`judgment suit against Mentor Graphics. See Complaint (MG 2004).
`
`
`
`7
`
`

`

`Preliminary Response By Patent Owner
`
`
`
`IPR 2012-00042
`
`resolution of this issue and cannot relitigate this issue.” Underwood Livestock, Inc.
`v. U.S., 417 Fed. App’x 934, 938 (Fed. Cir. 2011). As an owner of rights
`previously held by EVE, Synopsys is bound by the previous court decisions
`regarding those rights.
`
`EVE had a full and fair opportunity to represent itself in the 2006 litigation.
`Synopsys and EVE therefore fall under the expanded definition of privity
`described in Taylor and the OPTPG because “a nonparty may be bound by a
`judgment because she was adequately represented by someone with the same
`interests who was a party to the suit.” Taylor, 553 U.S. at 894 (citation and
`formatting omitted). The test for adequate representation is whether the party to
`the previous litigation (i) “had the same interest as the party to be precluded” and
`(ii) “had a strong motive to assert that interest.” Cal. Physicians’ Serv., 163 Cal.
`App. 4th 1506, 1522-23 (cited in OPTPG discussion of privity).8 Here, the first
`condition applies because all of the interests Synopsys holds today in the ZeBu
`products were held by EVE at the time of the previous litigation, and the second
`condition applies because EVE had a strong motive to defend itself and the ZeBu
`products in patent infringement litigation. EVE therefore adequately represented
`the interests in the ZeBu products that today are held by Synopsys, and Synopsys is
`in privity with EVE.
`Courts applying the Supreme Court’s analysis in Taylor have held that
`
`“where one entity is a wholly owned subsidiary of the other, the two entities are in
`privity.” E.g., Royse v. Corhart Refractories Co., Inc., 2008 WL 4911117 at *3
`(W.D. Ky. 2008) (concluding that at least one of the “substantive legal
`
`
`8 Courts “do not undertake to measure the adequacy of the representation on the
`basis of an assessment of the performance” of the counsel representing the party
`to the litigation. Id.
`
`
`
`8
`
`

`

`Preliminary Response By Patent Owner
`
`
`
`IPR 2012-00042
`
`relationships” and “adequate representation” doctrines described by the Supreme
`Court in Taylor must apply in parent/subsidiary relationship). And Courts have
`held that a corporate merger creates a privity relationship. E.g., Butts v. JP
`Morgan Chase Bank, Slip Copy, 2011 WL 7109344 at *2 (N.D. Tex. 2011)
`(reasoning that “JPMC is the successor by merger to CHF” and “[t]his relationship
`is sufficient to establish privity” because “privity exists where the non-party is the
`successor in interest to a party's interest in property”) (citations and formatting
`omitted).
`Synopsys and EVE are in privity and therefore, the Director is barred from
`instituting an inter partes review of the ‘376 Patent based on a petition from either
`EVE or Synopsys.
`
`II.
`
`Technology Background
`
`There Is No Reasonable Likelihood of Petitioner Prevailing
`As To A Challenged Claim of the `376 Patent
`A.
`The ‘376 patent addresses shortcomings in previously known techniques for
`designing an electrical circuit that will ultimately be implemented in an integrated
`circuit. The process of designing a modern-day integrated circuit typically begins
`with a high-level description of the desired behavior of the circuit (a behavioral or
`algorithmic level description). From this, a separate register transfer level (RTL)
`circuit description can be developed. The RTL description, which is still at a
`relatively high level, specifies the circuit in terms of the inputs to, and outputs
`from, storage devices (registers) that store binary values representing the states of
`the circuit in a given clock cycle. Stated another way:
`
`Whilst the algorithmic description identifies operations needed to
`implement the desired functionality, the register transfer level goes
`
`
`
`9
`
`

`

`Preliminary Response By Patent Owner
`
`
`
`IPR 2012-00042
`
`one step further and schedules those operations into certain clock
`cycles.
`
`Jansen, D., The Electronic Design Automation Handbook, Kluwer Academic
`Publishers, 2003, Chapter 2 (MG 2008) at 7.
`
`Today, RTL or the Register Transfer Level is the most popular form
`of high-level design specification. An RTL description of a design
`describes the design in terms of transformation and transfer of logic
`from one register to another. Logic values are stored in registers
`where they are evaluated through some combinational logic, and then
`re-stored in the next register.
`
`H. Bhatnagar, Advanced ASIC Chip Synthesis: Using Synopsys® Design
`CompilerTM and PrimeTime®, Kluwer Academic Publishers, 1999 (MG 2009), at 4.
`
`A process known as “synthesis” is used to create, from a circuit description
`at one level of abstraction, a corresponding circuit specification at a lower level of
`abstraction. For example, a circuit description at the behavioral or algorithmic
`level may be synthesized to obtain an RTL circuit description. This is commonly
`referred to as high-level synthesis. Moving down a level of abstraction, an RTL
`level circuit description may be synthesized to obtain a corresponding structural
`circuit description (a specification of logic level gates corresponding to the
`physical circuit components and their electrical interconnections (nets)). This low-
`level structural specification is known as a “gate-level netlist.”
`
`Debugging and verification perform two functions in the circuit design
`process. First, debugging is used to verify that the designer has described/defined
`a system that does what it is intended to do. Secondly, verification is the process
`of confirming that each lower level of description created in the synthesis process
`
`
`
`10
`
`

`

`Preliminary Response By Patent Owner
`
`
`
`IPR 2012-00042
`
`successfully performs the function specified by the higher-level description serving
`as the starting point of the synthesis. Debugging and verification can be carried
`out at every level of synthesis using modeling, e.g., software simulation, hardware
`emulation or a combination of the two.
`
`Hardware emulation permits a circuit specification to be embodied in
`hardware for verification and debugging, before commitment of a design to
`fabrication on a chip. This has benefits over software simulation in terms of speed
`of execution, and facilitating possible insertion of the circuit into an actual system
`environment where the design is to be used upon completion. In the hardware
`emulation process, the circuit specification, which may be a high-level circuit
`specification such as RTL, or a low level circuit specification such as a gate-level
`netlist, is mapped to programmable hardware (e.g., FPGAs) of the emulation
`platform.
`
`In the case of modeling a high-level (e.g., behavioral or RTL) design by
`hardware emulation, instead of emulating the design at the gate level, high-level
`functions (e.g., adders, multipliers, etc.) may be mapped to high-level resources
`supplied by the emulator. One motivation for modeling at the behavioral or
`register transfer level (RTL) is to avoid the need to model every detail of the gate-
`level design.
`
`Of course, modeling at the behavioral level or RTL does not replace the
`need to debug and verify a circuit design at the gate level, as it is at this gate level
`that a circuit will ultimately be specified for fabrication. Thus, modeling at the
`gate level, by either and/or both of software simulation and hardware emulation,
`remains a desirable part of the process; it is to this part of the process that the
`inventions of the `376 patent have uniquely beneficial application.
`
`As described in the Background section of the `376 patent (2:18-24):
`
`
`
`11
`
`

`

`Preliminary Response By Patent Owner
`
`
`
`IPR 2012-00042
`
`A typical design flow will include creating a design at the RTL level,
`then synthesizing it into a gate-level netlist. Although simulation of
`this netlist can be performed at greater speeds using emulators or
`hardware accelerators, the ability to debug the design at the gate level
`is severely limited in comparison with software RTL simulation.
`
`B.
`Introduction To and Overview of Patent Owner’s Response To
`Petitioner’s Invalidity Arguments
`
`The `376 patent describes example methodologies that yield the benefits of
`
`high-level (e.g., RTL) debugging in conjunction with synthesis to obtain a gate-
`level circuit design.
` Stated another way, “[m]ethods of
`instrumenting
`synthesizable register transfer level (RTL) source code to enable debugging
`support akin to high-level language programming environments for gate-level
`simulation are provided.” `376 patent (SYNOPSYS 1001) at 2:26-29. The
`challenged claims of the ‘376 patent are directed to such methods (and storage
`media including executable instructions for carrying out such methods).
`
`The Petition challenges the patentability of claims 1-15 and 20-33. All of
`these claims pertain to gate-level synthesis (synthesis to obtain a gate-level design
`constituting a specification of the structural components (e.g., logic gates and their
`interconnections) of the physical circuit to be fabricated) from a higher-level
`abstract description of the circuit. Petitioner relies upon five references:
`• two articles by Koch et al. (SYNOPSYS 1004 and 1006);
`• Gregory et al. U.S. Patent No. 6,132,109 (SYNOPSYS 1007);
`• a brochure by Quickturn Design Systems, Inc. entitled “HDL-ICE
`ASIC Emulation System” (SYNOPSYS 1008); and
`• Sample et al. U.S. Patent No. 5,960,191 (SYNOPSYS 1010) (relied
`upon for its discussion of the HDL-ICE system).
`
`
`
`12
`
`

`

`Preliminary Response By Patent Owner
`
`
`
`IPR 2012-00042
`
`The two Koch articles, and the HDL-ICE system described in the Quickturn
`brochure and the Sample patent, all deal with design flow portions at a level of
`abstraction above gate-level synthesis.
`
`For example, the HDL-ICE system described in the cited Quickturn
`brochure (SYNOPSYS 1008), and referenced in the Sample et al. `191 patent
`(SYNOPSYS 1010), pertains to “high-level design verification” (id. at 2), as
`opposed to debugging and verification at the gate-level. With that system, “[y]ou
`can debug chips, systems and software at hardware speeds, before the process of
`gate-level synthesis and optimization for layout and manufacturing.” SYNOPSYS
`1008 at 2 (emphasis added).
`
`In addition, the HDL-ICE Quickturn brochure (SYNOPSYS 1008) has not
`been shown to even constitute a prior art printed publication. The document itself
`bears no indicia of publication or dissemination. Petitioner relies upon an alleged
`submission and availability of the document in the file history of another patent as
`evidence of publication at least of its date of submission. However, this
`submission does not evidence any publication of the document early enough to
`constitute prior art. The file history it was cited in (SYNOPSYS 1009) did not
`become publicly available until the patent issued on November 17, 1998 (no pre-
`grant publication), which is well after the July 31, 1998 filing date of the `376
`patent. Cf., Resqnet.com, Inc. v. Lansa, Inc., 594 F.3d 860, 865-66 (Fed. Cir.
`2010) (computer software user manuals did not qualify as prior art printed
`publications because there was no evidence that they had actually been published
`or disseminated to the public).
`
`The two Koch et al. references (SYNOPSYS 1004 and 1006) relate to
`“Source Level Emulation (SLE)” techniques to correlate “hardware elements and
`the behavioral VHDL source” (SYNOPSYS 1004 at 1) that are useful for
`debugging at the behavioral VHDL specification level (SYNOPSYS 1006 at 6),
`
`
`
`13
`
`

`

`Preliminary Response By Patent Owner
`
`
`
`IPR 2012-00042
`
`not at the gate level. The second Koch et al. reference (Ex. 1006) was considered
`during the original prosecution of the ‘376 patent. The Examiner did not apply the
`original Koch et al. reference, but did apply the Chen reference (SYNOPSYS
`1003). Chen is generally similar to the Koch et al. references insofar as it also
`pertains to the performance of debugging and verification at a level of abstraction
`above gate level. In particular, Chen discloses a high-level synthesis technique
`that starts with a behavioral algorithmic design description and generates an
`equivalent RTL description that may then be simulated for debugging and
`validation of the behavioral description at the RTL level.
`
`Similar to the Matisse system described in Chen, the Source Level
`Emulation (SLE) of the Koch et al. references, and the HDL-ICE ASIC Emulation
`System, also debug and validate behavioral or algorithmic description, but do so by
`generating an equivalent high-level emulation circuit. Given the focus of these
`systems on behavioral or RTL level verification, the circuits generated for
`emulation will not reflect the structure and timing of the gates to be ultimately
`fabricated. Instead, these high-level emulation circuits will only be algorithmically
`equivalent. Moreover, the processes purposely skip generating a gate-level netlist
`altogether, instead going straight from a behavioral-level description to a physical
`manifestation on the emulator.
`
`Gregory et al. U.S. Patent No. 6,132,109 (“Gregory”; SYNOPSYS 1007)
`involves gate-level synthesis, but does not involve the instrumentation-related
`methods set forth in the claims. This patent and Gregory et al. U.S. Patent No.
`5,937,190 (MG 2010), which was considered during the prosecution of the `376
`
`
`
`14
`
`

`

`Preliminary Response By Patent Owner
`
`
`
`IPR 2012-00042
`
`patent, share a common parent application (Serial No. 08/226,147) and a
`substantial amount of the disclosure claimed to be relevant by Petitioner.9
`Gregory’s “probe statements” (which are actually comments) that are added
`
`to HDL source code simply prevent circuit components created in the synthesis of
`the source code from being removed in a subsequent circuit optimization process.
`Signals may be relabeled as temporary outputs in order to preserve them through
`the optimization process, but those do not constitute instrumentation in the sense of
`the `376 patent claims.
`Accordingly, none of the references relied upon by Petitioner gives rise to a
`reasonable likelihood of Petitioner prevailing with respect to at least one of the
`challenged claims of the `376 patent.
`
`C.
`Patent Owner’s Response To Petitioner’s Unpatentability
`Arguments
`1. There Is No Reasonable Likelihood of Any of Claims 1-