`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`In re U.S. Patent No. 6,240,376
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`Application No.:
`Filed:
`Issued:
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`09/127,587
`July 31, 1998
`May 29, 2001
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`Inventors:
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`Alain Raynaud
`Luc M. Burgun
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`Trial No.:
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`Atty. Dkt. No.
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`IPR 2012-00042
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`007121.00004
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`Patent Owner: Mentor Graphics
`Corporation
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`METHOD AND APPARATUS
`FOR GATE-LEVEL
`SIMULATION OF
`SYNTHESIZED REGISTER
`TRANSFER LEVEL DESIGNS
`WITH SOURCE-LEVEL
`DEBUGGING
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`For:
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`Mail Stop PATENT BOARD
`Patent Trial and Appeal Board
`United States Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
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`PATENT OWNER’S REPLY IN SUPPORT OF ITS SUBSTITUTE MOTION TO AMEND
`UNDER 37 C.F.R. § 42.121
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`Table of Contents
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`I. Petitioner and Its Expert Improperly Interpret the Substitute Claims ............................ 1
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`II. Petitioner’s Reading of the Substitute Claims on Gregory is Faulty .............................. 2
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`III. Petitioner’s Alleged “Knowledge And Skill Possessed By An Ordinarily Skilled Artisan”
`Fails To Rebut The Demonstrated Non-Obviousness ................................................. 3
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`Previously Filed
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`MG 2001
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`MG 2002
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`MG 2003
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`MG 2004
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`MG 2005
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`MG 2006
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`MG 2007
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`MG 2008
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`MG 2009
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`EXHIBIT LIST
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`First Amended Complaint in Mentor Graphics Corp. v. EVE-USA, Inc.
`and Emulation and Verification Engineering, SA, 6:06-CV-00341-AA
`(D. OR., filed March 13, 2006)
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`Defendants’ Unopposed Motion By Special Appearance For Extension
`Of Time To Respond To Plaintiff’s First Amended Complaint in Mentor
`Graphics Corp. v. EVE-USA, Inc. and Emulation and Verification
`Engineering, SA, 6:06-CV-00341-AA (D. Or., filed May 23, 2006)
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`Order of Dismissal in Mentor Graphics Corp. v. EVE-USA, Inc. and
`Emulation and Verification Engineering, SA, 6:06-CV-00341-AA (D.
`Or., filed November 20, 2006)
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`Complaint for Declaratory Judgment and Injunctive Relief in Synopsys,
`Inc., EVE-USA, Inc. and Emulation and Verification Engineering, S.A.
`v. Mentor Graphics Corp., 3:12-cv-05025 (N.D. Cal., filed September
`27, 2012)
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`Banner & Witcoff, Ltd.’s “Messenger Log”
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`October 4, 2012 Synopsys Press Release “Synopsys Acquires EVE”
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`EVE-USA’s Supplemental Corporate Disclosure Statement, Docket
`No. 7, filed October 26, 2012 in Synopsys, Inc. et al. v. Mentor
`Graphics Corp., 3:12-CV-05025 (N.D. Cal. filed September 27, 2012)
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`Jansen, D., The Electronic Design Automation Handbook, Kluwer
`Academic Publishers, 2003, Chapter 2
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`Bhatnagar, Advanced ASIC Chip Synthesis: Using Synopsys® Design
`Compiler™ and PrimeTime®, Kluwer Academic Publishers, 1999
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`MG 2010
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`Gregory et al. U.S. Patent No. 5,937,190
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`ii
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`MG 2011
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`MG 2012
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`MG 2013
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`MG 2014
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`MG 2015
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`MG 2016
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`MG 2017
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`MG 2018
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`MG 2019
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`MG 2020
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`MG 2021
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`MG 2022
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`MG 2023
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`HDL Compiler™ for VHDL User Guide, Version F-2011.09-SP4, March
`2012, SYNOPSYS, Section 4
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`Plaintiffs’ Opposition to Mentor Graphics Corporation’s Motion to
`Transfer, dated January 25, 2013
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`Notice of Incomplete Petition, mailed November 30, 2012 in CMI Corp.
`v. Yoshiharu, et. al., PTAB Case IPR 2013-00066
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`Response to Notice of Incomplete Petition Issued November30, 2012,
`filed November 30, 2012 in CMI Corp. v. Yoshiharu, et. al., PTAB
`Case IPR 2013-00066
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`Notice of Filing Date Accorded to Petition and Time for Filing Patent
`Owner Preliminary Response, mailed December 5, 2012 in CMI Corp.
`v. Yoshiharu, et. al., PTAB Case IPR 2013-00066
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`Declaration of Allison Anderson
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`Notice of Filing Date Accorded to Petition and Notice for Setting the
`Time Period for Filing Patent Owner Preliminary Response
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`[Proposed] Patent Owner’s Requests for Production To Petitioner
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`[Proposed] Patent Owner’s Interrogatories To Petitioner
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`[Proposed] Patent Owner’s Requests for Admission To Petitioner
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`[Proposed] Patent Owner’s Notice of Deposition of Petitioner
`Synopsys
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`Assignment of the ‘376 Patent from inventors to Mentor Graphics Corp
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`Notice of Party Name Change, filed March 22, 2013, in EVE-USA, Inc.
`and Emulation and Verification Engineering, S.A. v. Mentor Graphics
`Corp., 3:12-cv-05025 (N.D. Cal., filed September 27, 2012)
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`MG 2024
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`Slide presentation “Meeting Verification Challenges” by Luc Burgun,
`VP, Synopsys Emulation Division, Verification Group, November 2012
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`iii
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`MG 2025
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`MG 2026
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`MG 2027
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`MG2028
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`MG2029
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`Currently Filed
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`MG2030
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`MG2031
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`MG2032
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`MG2033
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`Silicon Valley Wire press release “Mountain View Based Synopsys
`Acquires EVE,” dated October 4, 2012
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`LinkedIn Profile of Luc Burgun listing his employment history
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`Declaration of Majid Sarrafzadeh, PH.D in Support of Patent Owner
`Response, including Exhibits A through E thereto
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`Declaration of Michael Sapoznikow in Support of Mentor Graphics
`Corporation's Motion for Partial Summary Judgment, filed 05/31/13 in
`Case 3:10-cv-00954-MO Doc. 369 (exhibit 5)
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`Declaration Of Patrick M. Bible In Support Of Mentor Graphics
`Corporation’s Motion For Partial Summary Judgment, filed 05/31/13 in
`Case 3:10-cv-00954-MO Doc. 368 (exhibits 2, 3, 8, 9-11, 15, 18-21,
`27, 30, 32-34, 40)
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`Annotated Figure 13 of the Gregory et al. ‘109 Patent (Hutchings
`Deposition Exhibit)
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`Annotated Figure 17 of the Gregory et al. ‘109 Patent (Hutchings
`Deposition Exhibit)
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`Transcript of Deposition of Brad Hutchings Ph.D. conducted
`September 20, 2013
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`Declaration of William D. Davis
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`iv
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`The request to substitute claim 37 for claim 2 is hereby withdrawn. Novelty and non-
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`obviousness of the substitute claims over Gregory are established in Patent Owner’s
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`Motion, at 11-14. Petitioner’s opposition to the Motion fails to raise any substantial new
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`issues in this regard.
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`I.
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`Petitioner and Its Expert Improperly Interpret the Substitute Claims
`The plain meaning of the claimed “instrumentation logic comprising instrumentation
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`logic circuitry that is additional to circuitry specified in the source code” requires added
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`elements that perform logical operations (e.g., logic gates). Wires and/or I/Os of a circuit
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`design do not perform any logical operations. Petitioner provides no support for arguments
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`to the contrary. Further, substitute claims 34 and 36 recite that the instrumentation signal is
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`indicative of an execution status of the identified at least one statement within the RTL
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`synthesizable source code. 1 Dr. Hutchings opinions are not competent as he admitted that
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`he had formed no opinion regarding the meaning of “execution status.” Hutchings Dep. T.
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`(Ex. 2032) at 35-36. Similarly, neither Petitioner nor Dr. Hutchings have addressed the claim
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`limitation “instrumentation signal,” requiring, for all claims, that the signal indicate whether a
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`corresponding statement of the RTL synthesizable source code is active. See Sarrafzadeh
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`Decl. (Ex. 2027) at ¶ 37.
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`1 Petitioner’s opposition only addresses the language added in the claims. The alleged
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`incorporation of arguments by reference (Opposition at 3) violates 37 C.F.R. § 42.6(a)(3).
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`1
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`II.
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`Petitioner’s Reading of the Substitute Claims on Gregory is Faulty
`Gregory’s probe statements do not result in a gate level netlist with added logic
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`providing an instrumentation signal. Gregory’s “tempin” and “tempout” are merely flags or
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`labels used to preserve selected circuitry through post-synthesis optimization. Motion at 12-
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`13; Sarrafzadeh Decl. ¶¶ 44, 51-53 and 61-63. These connections (wires) do not have
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`additional logic associated with them. Id. at ¶ 45. Dr. Hutchings’ statement (Decl at ¶ 29)
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`that “logic circuitry is broader than logic gates and could include additional wires and
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`input/output connections” misses the point. As Dr. Hutchings testified, it is the logic gates in
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`Gregory’s logic circuit that perform logic functions, not wires and I/O. Hutchings Dep. T. at
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`38-45. Hence, added wires and I/O do not constitute additional logic circuitry. Dr. Hutchings
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`admitted that tempin and tempout, as shown, e.g., in Fig. 18, are directly connected to each
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`other such that the circuit function is unaltered (Hutchings Dep. T. at 68 and 71), i.e., the
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`connection is only a wire that by itself does not constitute additional logic circuitry.
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`Petitioner’s comparison of Figs. 14 and 18 in Gregory does not show additional logic
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`resulting from Gregory’s probe statements. Figs. 14 and 18 are respectively optimized from
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`Figs. 13 and 17, which Dr. Hutchings now concedes include identical functions and no
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`discernible difference in logic. Hutchings Dep. T. at 56-57. Dr. Hutchings retracted ¶ 33 of
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`his Declaration as inaccurate. Hutchings Dep. T. at 27-28 and 54-55. Figs. 14 and 18 could
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`not include logic circuitry that is additional to circuitry specified in the source code, because
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`both Fig. 14 and Fig. 18 have been reduced from the circuitry specified in the respective
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`source code, i.e., as reflected in Figs. 13 and 17. Whether one optimization (i.e., Fig. 18
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`based on probes) reduces the gate count less than another optimization (i.e., Fig. 14 based
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`on no probes) is entirely irrelevant, because neither optimization includes logic circuitry that
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`is additional to circuitry specified in the source code from which both Figs 14 and 18 are
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`optimized. Petitioner’s reasoning based on comparing Figs. 7 and 8 is similarly deficient.
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`Petitioner further fails to demonstrate that Gregory’s “tempin” and “tempout” indicate
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`execution status of a corresponding statement, as required by substitute claims 34 and 36,
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`or whether the statement is active as required by the “instrumentation signal” recited in all
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`the claims. The opposition fails to address these claim requirements, and Dr. Hutchings’
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`opinions on anticipation and obviousness are incompetent and entitled to no weight, for at
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`least the reason that he formed no opinion on the meaning of “execution status.” Hutchings
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`Dep. T. at 35-36. Gregory does not disclose functionally simulating a gate level netlist, or
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`any other means of obtaining an indication of execution status using a gate level netlist.
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`Hutchings Dep. T. at 47-51.
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`Petitioner’s Alleged “Knowledge And Skill Possessed By An Ordinarily Skilled
`III.
`Artisan” Fails To Rebut The Demonstrated Non-Obviousness
`The FPGA (emulation) related disclosures of Petitioner’s cited Exhibits 1014-1018 do
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`not remedy Gregory’s deficiencies. First, Gregory is concerned only with aspects of gate-
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`level debugging (e.g., area study, path delay analysis) to which functional simulation is not
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`applicable. Thus, the Petitioner’s attempt to relate the FPGA functional simulation referred
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`to in the references to Gregory’s debugging of optimized netlists is entirely misplaced. See
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`Hutchings Dep. T. at 47-51 (Dr. Hutchings could point to no disclosure in Gregory of
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`functionally simulating a gate level netlist). Additionally, the FPGA disclosures of routing a
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`signal to an unused I/O does not disclose adding such routing to a gate level netlist. Indeed,
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`exhibits1014 (p. 65) and 1017 (p. 1036) explicitly disclose the opposite by storing such
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`routing separately from the “real design.” Moreover, while Dr. Hutchings testified (e.g., Dep.
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`T. at 75-76, 81) that I/O might be originally specified in a gate level netlist then optimized
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`away, Gregory’s system is premised on the conflicting principle of primary netlist I/O not
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`being optimized away as a way of preserving a signal. So, Dr. Hutchings’ testimony only
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`serves to further illustrate the incompatibility of the cited teachings with Gregory. Still further,
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`routing and I/O are not logic, and thus, not additional logic circuitry as the claims require.
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`Petitioner, as confirmed in the conference call with the Board on September 25,
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`2013, does not rely upon the Boubezari et al. patent (Ex. 1012) as prior art. Nonetheless, to
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`disprove the asserted prior art status of the reference under 35 U.S.C. § 102(e), Patent
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`Owner submits herewith a Declaration of William Davis (Ex. 2033) establishing, prior to the
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`102(e) date, conception of the claimed inventions, evidenced at least by the inventors’ initial
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`disclosure article received by Mr. Davis before January 9, 1998, which describes every
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`feature of the substitute claims. Davis Decl. (Ex. 2033) ¶¶ 6-7. Reasonable diligence toward
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`a constructive reduction to practice extending back from the effective filing date of the `376
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`patent to before the 102(e) date is evidenced by Mr. Davis’ and the inventors’ efforts in
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`preparing the parent application (Id. at ¶¶ 8-12), which is substantially the same to the
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`application of the ‘376 patent (Id. at ¶ 3), and fully supports the substitute claims (see
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`Motion at 6-8). C.f., Walker v. Bailey, 245 F.2d 486, 490 (C.C.P.A. 1957).
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`Being neither relied upon as prior art, nor constituting prior art in fact, Boubezari is
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`not competent evidence of what was within the knowledge and skill of one of ordinary skill in
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`the art at the time of the invention. Petitioner’s citation to Geo M. Martin Co. v. Alliance
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`Mach. Sys. Int’l, LLC, 618 F.3d 1294, 1305-06 (Fed. Cir. 2010) is inapposite. The holding in
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`that case was strictly limited to a situation where evidence of a near-simultaneously
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`invention was coupled with strong evidence of obviousness based on other references, and
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`where there were multiple examples of simultaneous invention. See Apple, Inc., v.
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`Samsung Elecs. Co., 877 F. Supp.2d 838, 881 (N. D. Cal. 2012) rev’d on other grounds,
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`695 F.3D 1370 (Fed. Cir. 2012). Petitioner’s failure to present a strong showing of
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`obviousness based on other references, along with Boubezari being the only alleged
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`evidence of simultaneous invention, render the alleged evidence insufficient to demonstrate
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`obviousness. C.f., id.
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`Dated: September 26, 2013
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`Respectfully submitted,
`MENTOR GRAPHICS CORP.
`/Christopher L. McKee/
`Christopher L. McKee, Reg. No. 32,384
`Michael S. Cuviello, Reg. No. 59,255
`Banner & Witcoff, Ltd
`1100 13th Street, NW Suite 1200
`Washington, DC 20005
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`By:
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`CERTIFICATE OF SERVICE
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`The undersigned certifies service on the Petitioner, pursuant to 37 C.F.R. § 42.6(e)
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`and agreement of the parties, by email delivery of a true copy of the foregoing PATENT
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`OWNER’S REPLY IN SUPPORT OF ITS SUBSTITUTE MOTION TO AMEND UNDER 37
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`C.F.R. § 42.121 to counsel of record for Petitioner as follows:
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`William H. Wright, Esq.
`wwright@orrick.com
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`Travis Jensen, Esq.
`tjensen@orrick.com
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` /Christopher L. McKee/
`Dated: September 26, 2013
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`Christopher L. McKee
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