IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`In re U.S. Patent No. 6,240,376
`
`Application No.:
`Filed:
`Issued:
`
`09/127,587
`July 31, 1998
`May 29, 2001
`
`Inventors:
`
`Alain Raynaud
`Luc M. Burgun
`
`
`
`Trial No.:
`
`
`
`
`
`
`Atty. Dkt. No.
`
`IPR 2012-00042
`
`007121.00004
`
`Patent Owner: Mentor Graphics
`Corporation
`
`METHOD AND APPARATUS
`FOR GATE-LEVEL
`SIMULATION OF
`SYNTHESIZED REGISTER
`TRANSFER LEVEL DESIGNS
`WITH SOURCE-LEVEL
`DEBUGGING
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`For:
`
`Mail Stop PATENT BOARD
`Patent Trial and Appeal Board
`United States Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`PATENT OWNER’S REPLY IN SUPPORT OF ITS SUBSTITUTE MOTION TO AMEND
`UNDER 37 C.F.R. § 42.121
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`In re U.S. Patent No. 6,240,376
`
`Application No.:
`Filed:
`Issued:
`
`09/127,587
`July 31, 1998
`May 29, 2001
`
`Inventors:
`
`Alain Raynaud
`Luc M. Burgun
`
`
`
`Trial No.:
`
`
`
`
`
`
`Atty. Dkt. No.
`
`IPR 2012-00042
`
`007121.00004
`
`Patent Owner: Mentor Graphics
`Corporation
`
`METHOD AND APPARATUS
`FOR GATE-LEVEL
`SIMULATION OF
`SYNTHESIZED REGISTER
`TRANSFER LEVEL DESIGNS
`WITH SOURCE-LEVEL
`DEBUGGING
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`For:
`
`Mail Stop PATENT BOARD
`Patent Trial and Appeal Board
`United States Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`PATENT OWNER’S REPLY IN SUPPORT OF ITS SUBSTITUTE MOTION TO AMEND
`UNDER 37 C.F.R. § 42.121
`
`
`
`
`Table of Contents
`
`I. Petitioner and Its Expert Improperly Interpret the Substitute Claims ............................ 1
`
`II. Petitioner’s Reading of the Substitute Claims on Gregory is Faulty .............................. 2
`
`III. Petitioner’s Alleged “Knowledge And Skill Possessed By An Ordinarily Skilled Artisan”
`Fails To Rebut The Demonstrated Non-Obviousness ................................................. 3
`
`
`
`
`
`
`
`
`
`i
`
`
`
`
`
`Previously Filed
`
`MG 2001
`
`MG 2002
`
`MG 2003
`
`MG 2004
`
`MG 2005
`
`MG 2006
`
`MG 2007
`
`MG 2008
`
`MG 2009
`
`EXHIBIT LIST
`
`First Amended Complaint in Mentor Graphics Corp. v. EVE-USA, Inc.
`and Emulation and Verification Engineering, SA, 6:06-CV-00341-AA
`(D. OR., filed March 13, 2006)
`
`Defendants’ Unopposed Motion By Special Appearance For Extension
`Of Time To Respond To Plaintiff’s First Amended Complaint in Mentor
`Graphics Corp. v. EVE-USA, Inc. and Emulation and Verification
`Engineering, SA, 6:06-CV-00341-AA (D. Or., filed May 23, 2006)
`
`Order of Dismissal in Mentor Graphics Corp. v. EVE-USA, Inc. and
`Emulation and Verification Engineering, SA, 6:06-CV-00341-AA (D.
`Or., filed November 20, 2006)
`
`Complaint for Declaratory Judgment and Injunctive Relief in Synopsys,
`Inc., EVE-USA, Inc. and Emulation and Verification Engineering, S.A.
`v. Mentor Graphics Corp., 3:12-cv-05025 (N.D. Cal., filed September
`27, 2012)
`
`Banner & Witcoff, Ltd.’s “Messenger Log”
`
`October 4, 2012 Synopsys Press Release “Synopsys Acquires EVE”
`
`EVE-USA’s Supplemental Corporate Disclosure Statement, Docket
`No. 7, filed October 26, 2012 in Synopsys, Inc. et al. v. Mentor
`Graphics Corp., 3:12-CV-05025 (N.D. Cal. filed September 27, 2012)
`
`Jansen, D., The Electronic Design Automation Handbook, Kluwer
`Academic Publishers, 2003, Chapter 2
`
`Bhatnagar, Advanced ASIC Chip Synthesis: Using Synopsys® Design
`Compiler™ and PrimeTime®, Kluwer Academic Publishers, 1999
`
`MG 2010
`
`Gregory et al. U.S. Patent No. 5,937,190
`
`ii
`
`
`
`
`
`
`
`MG 2011
`
`MG 2012
`
`MG 2013
`
`MG 2014
`
`MG 2015
`
`MG 2016
`
`MG 2017
`
`MG 2018
`
`MG 2019
`
`MG 2020
`
`MG 2021
`
`MG 2022
`
`MG 2023
`
`HDL Compiler™ for VHDL User Guide, Version F-2011.09-SP4, March
`2012, SYNOPSYS, Section 4
`
`Plaintiffs’ Opposition to Mentor Graphics Corporation’s Motion to
`Transfer, dated January 25, 2013
`
`Notice of Incomplete Petition, mailed November 30, 2012 in CMI Corp.
`v. Yoshiharu, et. al., PTAB Case IPR 2013-00066
`
`Response to Notice of Incomplete Petition Issued November30, 2012,
`filed November 30, 2012 in CMI Corp. v. Yoshiharu, et. al., PTAB
`Case IPR 2013-00066
`
`Notice of Filing Date Accorded to Petition and Time for Filing Patent
`Owner Preliminary Response, mailed December 5, 2012 in CMI Corp.
`v. Yoshiharu, et. al., PTAB Case IPR 2013-00066
`
`Declaration of Allison Anderson
`
`Notice of Filing Date Accorded to Petition and Notice for Setting the
`Time Period for Filing Patent Owner Preliminary Response
`
`[Proposed] Patent Owner’s Requests for Production To Petitioner
`
`[Proposed] Patent Owner’s Interrogatories To Petitioner
`
`[Proposed] Patent Owner’s Requests for Admission To Petitioner
`
`[Proposed] Patent Owner’s Notice of Deposition of Petitioner
`Synopsys
`
`Assignment of the ‘376 Patent from inventors to Mentor Graphics Corp
`
`Notice of Party Name Change, filed March 22, 2013, in EVE-USA, Inc.
`and Emulation and Verification Engineering, S.A. v. Mentor Graphics
`Corp., 3:12-cv-05025 (N.D. Cal., filed September 27, 2012)
`
`MG 2024
`
`Slide presentation “Meeting Verification Challenges” by Luc Burgun,
`VP, Synopsys Emulation Division, Verification Group, November 2012
`
`iii
`
`
`
`
`
`
`
`MG 2025
`
`MG 2026
`
`MG 2027
`
`MG2028
`
`MG2029
`
`Currently Filed
`
`MG2030
`
`MG2031
`
`MG2032
`
`MG2033
`
`
`Silicon Valley Wire press release “Mountain View Based Synopsys
`Acquires EVE,” dated October 4, 2012
`
`LinkedIn Profile of Luc Burgun listing his employment history
`
`Declaration of Majid Sarrafzadeh, PH.D in Support of Patent Owner
`Response, including Exhibits A through E thereto
`
`Declaration of Michael Sapoznikow in Support of Mentor Graphics
`Corporation's Motion for Partial Summary Judgment, filed 05/31/13 in
`Case 3:10-cv-00954-MO Doc. 369 (exhibit 5)
`
`Declaration Of Patrick M. Bible In Support Of Mentor Graphics
`Corporation’s Motion For Partial Summary Judgment, filed 05/31/13 in
`Case 3:10-cv-00954-MO Doc. 368 (exhibits 2, 3, 8, 9-11, 15, 18-21,
`27, 30, 32-34, 40)
`
`Annotated Figure 13 of the Gregory et al. ‘109 Patent (Hutchings
`Deposition Exhibit)
`
`Annotated Figure 17 of the Gregory et al. ‘109 Patent (Hutchings
`Deposition Exhibit)
`
`Transcript of Deposition of Brad Hutchings Ph.D. conducted
`September 20, 2013
`
`Declaration of William D. Davis
`
`iv
`
`
`
`
`
`
`
`The request to substitute claim 37 for claim 2 is hereby withdrawn. Novelty and non-
`
`obviousness of the substitute claims over Gregory are established in Patent Owner’s
`
`Motion, at 11-14. Petitioner’s opposition to the Motion fails to raise any substantial new
`
`issues in this regard.
`
`I.
`
`Petitioner and Its Expert Improperly Interpret the Substitute Claims
`The plain meaning of the claimed “instrumentation logic comprising instrumentation
`
`logic circuitry that is additional to circuitry specified in the source code” requires added
`
`elements that perform logical operations (e.g., logic gates). Wires and/or I/Os of a circuit
`
`design do not perform any logical operations. Petitioner provides no support for arguments
`
`to the contrary. Further, substitute claims 34 and 36 recite that the instrumentation signal is
`
`indicative of an execution status of the identified at least one statement within the RTL
`
`synthesizable source code. 1 Dr. Hutchings opinions are not competent as he admitted that
`
`he had formed no opinion regarding the meaning of “execution status.” Hutchings Dep. T.
`
`(Ex. 2032) at 35-36. Similarly, neither Petitioner nor Dr. Hutchings have addressed the claim
`
`limitation “instrumentation signal,” requiring, for all claims, that the signal indicate whether a
`
`corresponding statement of the RTL synthesizable source code is active. See Sarrafzadeh
`
`Decl. (Ex. 2027) at ¶ 37.
`
`1 Petitioner’s opposition only addresses the language added in the claims. The alleged
`
`incorporation of arguments by reference (Opposition at 3) violates 37 C.F.R. § 42.6(a)(3).
`
`
`
`1
`
`
`
`
`
`II.
`
`Petitioner’s Reading of the Substitute Claims on Gregory is Faulty
`Gregory’s probe statements do not result in a gate level netlist with added logic
`
`providing an instrumentation signal. Gregory’s “tempin” and “tempout” are merely flags or
`
`labels used to preserve selected circuitry through post-synthesis optimization. Motion at 12-
`
`13; Sarrafzadeh Decl. ¶¶ 44, 51-53 and 61-63. These connections (wires) do not have
`
`additional logic associated with them. Id. at ¶ 45. Dr. Hutchings’ statement (Decl at ¶ 29)
`
`that “logic circuitry is broader than logic gates and could include additional wires and
`
`input/output connections” misses the point. As Dr. Hutchings testified, it is the logic gates in
`
`Gregory’s logic circuit that perform logic functions, not wires and I/O. Hutchings Dep. T. at
`
`38-45. Hence, added wires and I/O do not constitute additional logic circuitry. Dr. Hutchings
`
`admitted that tempin and tempout, as shown, e.g., in Fig. 18, are directly connected to each
`
`other such that the circuit function is unaltered (Hutchings Dep. T. at 68 and 71), i.e., the
`
`connection is only a wire that by itself does not constitute additional logic circuitry.
`
`Petitioner’s comparison of Figs. 14 and 18 in Gregory does not show additional logic
`
`resulting from Gregory’s probe statements. Figs. 14 and 18 are respectively optimized from
`
`Figs. 13 and 17, which Dr. Hutchings now concedes include identical functions and no
`
`discernible difference in logic. Hutchings Dep. T. at 56-57. Dr. Hutchings retracted ¶ 33 of
`
`his Declaration as inaccurate. Hutchings Dep. T. at 27-28 and 54-55. Figs. 14 and 18 could
`
`not include logic circuitry that is additional to circuitry specified in the source code, because
`
`both Fig. 14 and Fig. 18 have been reduced from the circuitry specified in the respective
`
`
`
`2
`
`
`
`
`
`source code, i.e., as reflected in Figs. 13 and 17. Whether one optimization (i.e., Fig. 18
`
`based on probes) reduces the gate count less than another optimization (i.e., Fig. 14 based
`
`on no probes) is entirely irrelevant, because neither optimization includes logic circuitry that
`
`is additional to circuitry specified in the source code from which both Figs 14 and 18 are
`
`optimized. Petitioner’s reasoning based on comparing Figs. 7 and 8 is similarly deficient.
`
`Petitioner further fails to demonstrate that Gregory’s “tempin” and “tempout” indicate
`
`execution status of a corresponding statement, as required by substitute claims 34 and 36,
`
`or whether the statement is active as required by the “instrumentation signal” recited in all
`
`the claims. The opposition fails to address these claim requirements, and Dr. Hutchings’
`
`opinions on anticipation and obviousness are incompetent and entitled to no weight, for at
`
`least the reason that he formed no opinion on the meaning of “execution status.” Hutchings
`
`Dep. T. at 35-36. Gregory does not disclose functionally simulating a gate level netlist, or
`
`any other means of obtaining an indication of execution status using a gate level netlist.
`
`Hutchings Dep. T. at 47-51.
`
`Petitioner’s Alleged “Knowledge And Skill Possessed By An Ordinarily Skilled
`III.
`Artisan” Fails To Rebut The Demonstrated Non-Obviousness
`The FPGA (emulation) related disclosures of Petitioner’s cited Exhibits 1014-1018 do
`
`not remedy Gregory’s deficiencies. First, Gregory is concerned only with aspects of gate-
`
`level debugging (e.g., area study, path delay analysis) to which functional simulation is not
`
`applicable. Thus, the Petitioner’s attempt to relate the FPGA functional simulation referred
`
`to in the references to Gregory’s debugging of optimized netlists is entirely misplaced. See
`
`
`
`3
`
`
`
`
`
`Hutchings Dep. T. at 47-51 (Dr. Hutchings could point to no disclosure in Gregory of
`
`functionally simulating a gate level netlist). Additionally, the FPGA disclosures of routing a
`
`signal to an unused I/O does not disclose adding such routing to a gate level netlist. Indeed,
`
`exhibits1014 (p. 65) and 1017 (p. 1036) explicitly disclose the opposite by storing such
`
`routing separately from the “real design.” Moreover, while Dr. Hutchings testified (e.g., Dep.
`
`T. at 75-76, 81) that I/O might be originally specified in a gate level netlist then optimized
`
`away, Gregory’s system is premised on the conflicting principle of primary netlist I/O not
`
`being optimized away as a way of preserving a signal. So, Dr. Hutchings’ testimony only
`
`serves to further illustrate the incompatibility of the cited teachings with Gregory. Still further,
`
`routing and I/O are not logic, and thus, not additional logic circuitry as the claims require.
`
`Petitioner, as confirmed in the conference call with the Board on September 25,
`
`2013, does not rely upon the Boubezari et al. patent (Ex. 1012) as prior art. Nonetheless, to
`
`disprove the asserted prior art status of the reference under 35 U.S.C. § 102(e), Patent
`
`Owner submits herewith a Declaration of William Davis (Ex. 2033) establishing, prior to the
`
`102(e) date, conception of the claimed inventions, evidenced at least by the inventors’ initial
`
`disclosure article received by Mr. Davis before January 9, 1998, which describes every
`
`feature of the substitute claims. Davis Decl. (Ex. 2033) ¶¶ 6-7. Reasonable diligence toward
`
`a constructive reduction to practice extending back from the effective filing date of the `376
`
`patent to before the 102(e) date is evidenced by Mr. Davis’ and the inventors’ efforts in
`
`preparing the parent application (Id. at ¶¶ 8-12), which is substantially the same to the
`
`
`
`4
`
`
`
`
`
`application of the ‘376 patent (Id. at ¶ 3), and fully supports the substitute claims (see
`
`Motion at 6-8). C.f., Walker v. Bailey, 245 F.2d 486, 490 (C.C.P.A. 1957).
`
`Being neither relied upon as prior art, nor constituting prior art in fact, Boubezari is
`
`not competent evidence of what was within the knowledge and skill of one of ordinary skill in
`
`the art at the time of the invention. Petitioner’s citation to Geo M. Martin Co. v. Alliance
`
`Mach. Sys. Int’l, LLC, 618 F.3d 1294, 1305-06 (Fed. Cir. 2010) is inapposite. The holding in
`
`that case was strictly limited to a situation where evidence of a near-simultaneously
`
`invention was coupled with strong evidence of obviousness based on other references, and
`
`where there were multiple examples of simultaneous invention. See Apple, Inc., v.
`
`Samsung Elecs. Co., 877 F. Supp.2d 838, 881 (N. D. Cal. 2012) rev’d on other grounds,
`
`695 F.3D 1370 (Fed. Cir. 2012). Petitioner’s failure to present a strong showing of
`
`obviousness based on other references, along with Boubezari being the only alleged
`
`evidence of simultaneous invention, render the alleged evidence insufficient to demonstrate
`
`obviousness. C.f., id.
`
`
`Dated: September 26, 2013
`
`
`
`
`
`
`
`
`
`
`
`.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Respectfully submitted,
`MENTOR GRAPHICS CORP.
`/Christopher L. McKee/
`Christopher L. McKee, Reg. No. 32,384
`Michael S. Cuviello, Reg. No. 59,255
`Banner & Witcoff, Ltd
`1100 13th Street, NW Suite 1200
`Washington, DC 20005
`
`
`
`
`
`
`
`By:
`
`
`
`5
`
`
`
`
`
`CERTIFICATE OF SERVICE
`
`The undersigned certifies service on the Petitioner, pursuant to 37 C.F.R. § 42.6(e)
`
`and agreement of the parties, by email delivery of a true copy of the foregoing PATENT
`
`OWNER’S REPLY IN SUPPORT OF ITS SUBSTITUTE MOTION TO AMEND UNDER 37
`
`C.F.R. § 42.121 to counsel of record for Petitioner as follows:
`
`William H. Wright, Esq.
`wwright@orrick.com
`
`Travis Jensen, Esq.
`tjensen@orrick.com
`
`
`
`
`
`
` /Christopher L. McKee/
`Dated: September 26, 2013
`
`Christopher L. McKee
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
Accessing this document will incur an additional charge of $.
After purchase, you can access this document again without charge.
Accept $ Charge
Still Working On It
This document is taking longer than usual to download. This can happen if we need to contact the court directly to obtain the document and their servers are running slowly.
Give it another minute or two to complete, and then try the refresh button.
A few More Minutes ... Still Working
It can take up to 5 minutes for us to download a document if the court servers are running slowly.
Thank you for your continued patience.
This document could not be displayed.
We could not find this document within its docket. Please go back to the docket page and check the link. If that does not work, go back to the docket and refresh it to pull the newest information.
Your account does not support viewing this document.
You need a Paid Account to view this document. Click here to change your account type.
Your account does not support viewing this document.
Set your membership
status to view this document.
With a Docket Alarm membership, you'll
get a whole lot more, including:
- Up-to-date information for this case.
- Email alerts whenever there is an update.
- Full text search for other cases.
- Get email alerts whenever a new case matches your search.
One Moment Please
The filing “” is large (MB) and is being downloaded.
Please refresh this page in a few minutes to see if the filing has been downloaded. The filing will also be emailed to you when the download completes.
Your document is on its way!
If you do not receive the document in five minutes, contact support at support@docketalarm.com.
Sealed Document
We are unable to display this document, it may be under a court ordered seal.
If you have proper credentials to access the file, you may proceed directly to the court's system using your government issued username and password.
Access Government Site
