Paper No.___________
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SYNOPSYS, INC.
`Petitioner
`
`v.
`
`Patent of MENTOR GRAPHICS CORPORATION
`Patent Owner
`
`____________
`
`Case IPR2012-00042 (SCM)
`Patent 6,240,376 B1
`
`Mail Stop Patent Board, PTAB
`United State Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`PETITIONER’S REPLY TO PATENT OWNER’S RESPONSE
`
`OHSUSA:754079484.5
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`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SYNOPSYS, INC.
`Petitioner
`
`v.
`
`Patent of MENTOR GRAPHICS CORPORATION
`Patent Owner
`
`____________
`
`Case IPR2012-00042 (SCM)
`Patent 6,240,376 B1
`
`Mail Stop Patent Board, PTAB
`United State Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`PETITIONER’S REPLY TO PATENT OWNER’S RESPONSE
`
`OHSUSA:754079484.5
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`
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`Petitioner’s Reply to Patent Owner’s Response
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`IPR2012-00042
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`TABLE OF CONTENTS
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`II.
`
`TABLE OF CONTENTS........................................................................................ ii
`EXHIBIT LIST...................................................................................................... iii
`I.
`PETITIONER SYNOPSYS’ INTERPARTESREVIEWIS NOT
`BARRED BY § 315(B) OR ASSIGNOR ESTOPPEL..................................1
`CLAIM CONSTRUCTION. .........................................................................2
`A.
`The Board’s Construction Of Instrumentation Signal Is Correct. ...........3
`1.
`The claim language supports the Board’s construction.................4
`2.
`Mentor’s construction conflicts with the specification. ................5
`3.
`Mentor’s extrinsic evidence cannot overcome the
`intrinsic record.............................................................................8
`III. GREGORY ANTICIPATES THE CHALLENGED CLAIMS...................8
`A.
`Gregory Anticipates Claim 1..................................................................9
`1.
`Gregory satisfies the “instrumentation signal” limitation. ............9
`2.
`Gregory satisfies the “execution status” limitation.....................10
`Gregory Anticipates Dependent Claims 2-4.........................................12
`
`B.
`
`C.
`
`D.
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`Gregory Anticipates Claim 5................................................................14
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`Gregory Anticipates Dependent Claims 6-9 And 11. ...........................14
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`Gregory Anticipates Claims 28-29.......................................................15
`E.
`IV. CONCLUSION. ...........................................................................................15
`CERTIFICATE OF SERVICE.............................................................................17
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`ii
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`EXHIBIT LIST
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`Previously Filed
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`1001
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`1002
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`1003
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`1004
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`1005
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`1006
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`1007
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`1008
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`1009
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`1010
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`1011
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`1012
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`1013
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`1014
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`U.S. Patent No. 6,240,376 to Raynaud, et al.
`
`Prosecution history of application Serial No. 09/127,584, which matured
`into the ‘376 patent.
`
`Chen, et al., “A Source-Level Dynamic Analysis Methodology and Tool
`for High-Level Synthesis,” Proceedings of the Tenth International
`Symposium on System Synthesis, 1997, pp. 134-140, Sep. 1997.
`
`Koch, et al., “Breakpoints and Breakpoint Detection in Source Level
`Emulation,” ISSS Proceedings of the 9th International Symposium on
`System Synthesis, pp. 26-31 (1996).
`
`Koch Publication information from CiteCeerX and ACM archives.
`
`Koch, et al., “Debugging of Behavioral VHDL Specifications by Source
`Level Emulation,” Proceedings of the European Design Automation
`Conference, pp. 256-261, September 1995.
`
`U.S. Patent No. 6,132,109 to Gregory, et al.
`
`HDL-ICETM ASIC Emulation System, Quickturn Design Systems, Inc.
`
`Prosecution history for application Serial No. 08/566,401, which matured
`into U.S. Patent No. 5,838,948.
`
`U.S. Patent No. 5,960,191 to Sample, et al.
`
`Transcript of Initial Conference Call, Mar. 21, 2013
`
`U.S. Patent No. 6,363,520 to Boubezari et al.
`
`Declaration of Dr. Brad Hutchings in support of Petitioner’s Opposition
`to Patent Owner’s Substitute Motion to Amend
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`Excerpts from Field-Programmable Gate Array Technology, Stephen M.
`Trimberger, 1994.
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`EXHIBIT LIST (CONT’D)
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`1015
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`1016
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`1017
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`1018
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`1019
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`1020
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`Taking Advantage of Reconfigurable Logic, Bradly K. Fawcett, Seventh
`Annual IEEE International Proceedings, ASIC Conference, 1994, pgs.
`227-230.
`
`Effects of FPGA Architecture on FPGA Routing, Stephen Trimberger,
`32nd ACM/IEEE Design Automation Conference, 1995.
`
`A Reprogrammable Gate Array and Applications, Stephen Trimberger,
`Proceedings of the IEEE, Vol. 81, No. 7, July 1993.
`
`Proper Use of Hierarchy in HDL-Based High Density FGPA Design,
`Carol A. Fields, published in Lecture Notes in Computer Science, 1995
`at pgs. 168-177.
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`Deposition Transcript of Dr. Majid Sarrafzadeh dated August, 22, 2013.
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`Declaration of Travis Jensen.
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`iv
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`Petitioner’s Reply to Patent Owner’s Response
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`IPR2012-00042
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`I. PETITIONER SYNOPSYS’ INTERPARTESREVIEWIS NOT
`BARRED BY § 315(b) OR ASSIGNOR ESTOPPEL.
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`Section 315(b) does not bar Synopsys’ request for inter partes review.
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`Mentor’s privity argument fails because Mentor admitted that Synopsys and EVE
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`were not in privity in 2006 when EVE was served with a complaint alleging
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`infringement. See, e.g., Paper 24 at 3; Paper 16 at 16-17; Paper 23 at 4-5; Paper 15
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`at 2, 7-8. The Board expressly held this was the legal standard for § 315(b) and
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`that “the effective filing date of the petition and the status of EVE as a real party-
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`in-interest to the inter partes review” are not relevant to this standard. Paper 24 at
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`3. In any event, Mentor cannot prove that Synopsys and EVE were in privity prior
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`to, or on, the filing date of the petition. Mentor now argues that privity should be
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`assessed at “any time before the institution of the IPR, including after the filing of
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`the Petition.” Response at 7. This argument is foreclosed by the plain language of
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`§ 315(b) itself which refers to the date “the petition requesting the proceeding is
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`filed.” Mentor’s argument that EVE was a real party in interest fails because
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`Mentor cites no evidence to support its assertions.
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`Neither does assignor estoppel bar Synopsys’ request. Mentor cites no law
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`or legislative history suggesting that assignor estoppel is cognizable in an inter
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`partes review. See Paper 24 at 7-10. Nor does Mentor show that inter partes
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`review should be different
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`from inter partes reexamination where it was
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`recognized that “[t]he Office, an administrative agency, is bound by the statues and
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`rules which authorize and govern its proceedings” and “Congress did not make
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`provision for assignor estoppel.”1
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`In re Harvey, Decision Dismissing Petition to
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`Vacate, Control No. 95/000,155, Mar. 8, 2007 at 6-7 (emphasis in original).
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`Even if assignor estoppel were a cognizable defense, the doctrine would not
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`be applicable here. Equitable estoppel is “concerned mainly with the balance of
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`equities between the parties” and the equities favor Synopsys. Diamond Scientific
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`Co. v. Ambico, Inc., 848 F.2d 1220, 1225-26 (Fed. Cir. 1988). Synopsys invented
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`the same subject matter claimed in the ’376 patent and filed a patent application on
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`it four years before Mentor’s patent application and 18 years before Luc Burgun
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`joined Synopsys. Synopsys’ application led to U.S. Patent 6,132,109 (“Gregory”),
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`the prior art reference at issue here. There is nothing unfair in allowing Synopsys
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`to use its own prior art to challenge the ’376 patent. To the contrary, it would be
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`manifestly unjust to prevent Synopsys from doing so.
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`II. CLAIM CONSTRUCTION.
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`In its Institution Decision the Board construed four terms. Paper 16 at 4-14.
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`Mentor challenges only the Board’s construction of “instrumentation signal.”
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`Paper 28 at 29-36. The claim construction issue is whether “the ’376 patent []
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`supports an interpretation that an instrumentation signal can [] be created solely
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`using preservation of circuit components” as the Board already determined (Paper
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`1 All emphasis is added unless otherwise noted.
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`16 at 26) or whether an instrumentation signal must be “created using added logic
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`elements (e.g., gates)” as Mentor contends (Response at 32).
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`The Board gives claims their “broadest reasonable construction in light of
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`the specification.” 37 C.F.R. § 100(b). This analysis adopts the perspective of one
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`of ordinary skill in the art.
`
`In re Suitco Surface, Inc., 603 F.3d 1255, 1260 (Fed.
`
`Cir. 2010). Rule 100(b) does not change the primacy of the claim language when
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`construing claims. See Innova/Pure Water, Inc. v. Safari Water Filtration Sys.,
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`381 F.3d 1111, 1115-1116 (Fed. Cir. 2004) (“a claim construction analysis must
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`begin and remain centered on the claim language itself.”).
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`A. The Board’s Construction Of Instrumentation Signal Is Correct.
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`The Board previously concluded that the broadest reasonable interpretation
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`of instrumentation signal “at least encompasses an output signal created during
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`synthesis of RTL source code by inserting additional logic, preserved from the
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`source code, that indicates whether the corresponding RTL source code statement
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`is active.” Paper 16 at 10. This construction is amply supported by the claim
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`language and the specification. In contrast, Mentor’s construction—which reads in
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`a limitation from the specification and excludes a preferred embodiment—is
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`improper under any claim construction standard.
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`1. The claim language supports the Board’s construction.
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`In its Institution Decision the Board noted that the “Patent Owner does not
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`direct us to any language in claim 1 … that supports an interpretation that an
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`instrumentation signal cannot be created solely using preservation of circuit
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`components.” Paper 16 at 26. Mentor’s Response likewise fails to address the
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`actual claim language.
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`Indeed, Mentor’s claim construction analysis begins by
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`eliminating “signal” and defining “instrumentation” by itself. Response at 31.
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`Nothing about the phrase “instrumentation signal” suggests that the recited signal
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`requires the addition of combinatorial logic gates during synthesis as Mentor
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`contends. Response at 32. Rather, the patentee’s deliberate choice to use the word
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`“instrumentation signal” suggests something different, and broader.
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`Basic principles of claim differentiation support the Board’s construction.
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`See, e.g., Liebel-Flarsheim Co. v. Medrad, Inc., 358 F.3d 898, 910 (Fed. Cir. 2004)
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`(“where the limitation that is sought to be ‘read into’ an independent claim already
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`appears in a dependent claim,
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`the doctrine of claim differentiation is at
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`its
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`strongest.”). Comparing independent claim 5 with dependent claim 9 demonstrates
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`the breadth of the term “instrumentation signal.” Claim 5 recites “creating an
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`instrumentation signal ….” Claim 9 adds the step of “generating cross-reference
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`instrumentation data ….” This language is an unmistakable reference to the
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`alternative embodiment discussed at cols. 2:47-50 and 5:32-45. In this alternative
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`IPR2012-00042
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`embodiment, “the gate-level netlist is not modified but the instrumentation signals
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`implementing the instrumentation logic are contained in a cross-reference
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`instrumentation database.”
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`’376 at 2:47-50. Thus, the term “instrumentation
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`signal” in claim 5 must also be broad enough to include the embodiment where no
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`additional gates are added to the gate-level netlist. The Board’s construction
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`covers the embodiment that supports claim 9; Mentor’s construction does not.2
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`Additionally, claim 1 only requires “synthesizing the source code into a
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`gate-level netlist including at least one instrumentation signal.” ’376 at 15:5-6. In
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`contrast, dependent claim 2 requires “generating instrumentation logic to provide
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`the instrumentation signal.” ’376 at 15:11-12. This requirement in claim 2 would
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`be superfluous if “instrumentation signal” in claim 1 were construed to require
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`generating instrumentation logic gates during synthesis. Mentor’s proposed
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`construction violates the doctrine of claim differentiation for this reason as well.
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`2. Mentor’s construction conflicts with the specification.
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`The specification defines “instrumentation” as “the process of preserving
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`high-level information through the synthesis process.” ’376 at 5:3-4. Mentor’s
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`argument
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`that
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`this
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`statement “describes only the purpose to which the
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`instrumentation is put” is unpersuasive. Response at 36. The specification does
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`2 Mentor offers no explanation for its statement that claim 5 excludes “an external
`‘cross-reference database’.” Response at 33; see also Sarrafzadeh Dec., ¶ 35.
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`not state “only the purpose” of instrumentation as Mentor contends. Rather, the
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`statement
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`is fairly read as describing how that purpose is achieved,
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`i.e., by
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`preserving signals during synthesis. Mentor’s argument that “nothing in this
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`passage is inconsistent with the ordinary meaning of ‘instrumentation’ as requiring
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`additional logic not present in the source code” applies the wrong legal standard.
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`Response at 36. The Board must give “instrumentation signal” its broadest
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`reasonable construction, not one that
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`is merely “[not]
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`inconsistent” with a
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`dictionary definition. 37 C.F.R. § 100(b).
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`Mentor’s requirement of additional
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`logic gates improperly reads in a
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`limitation from the specification. See, e.g., Response at 32. The principal figure
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`Mentor relies on (annotated Fig. 7, shown below) actually supports the Board’s
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`construction because it shows instrumentation signals that do not require additional
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`logic gates (e.g., SIG_TRACE1 and SIG_TRACE2). See also ’376 at 8:60-64.
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`Mentor’s myopic focus on two instrumentation signals that include additional
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`combinatorial logic gates (SIG_TRACE5 and SIG_TRACE6) to the exclusion of
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`other instrumentation signals that do not (e.g., SIG_TRACE1 and SIG_TRACE2)
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`illustrates its transparent and improper attempt to read in a limitation from the
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`specification. See, e.g., Liebel-Flarsheim Co., 358 F.3d at 906.
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`SIG_TRACE1 and SIG_TRACE2 in Fig. 10 are two more examples of
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`instrumentation signals
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`that do not
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`include additional gates.
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`The text
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`accompanying Fig. 10 explicitly states that SIG_TRACE1, SIG_TRACE2,
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`SIG_TRACE3, and SIG_TRACE4 are “instrumentation signals.” ’376 at 9:12-14.
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`When asked whether this text “state[s] that SIG_TRACE1 is an instrumentation
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`signal,” Dr. Sarrafzadeh’s response was that the passage “refers to [a] group of
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`signals, it does not talk about the signals individually.” Ex. 1019, Sarrafzadeh Tr.
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`at 44:13-17; see also id. at 42:13-45:22.
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`Even if Dr. Sarrafzadeh’s statement
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`were to be credited—which it should not—it does nothing to explain why the
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`specification subsequently specifically refers to SIG_TRACE1 in the singular as
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`an instrumentation signal. ’376 at 12:23-32.
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`Mentor’s argued construction also violates the well-established canon that
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`claims should not be construed to exclude a preferred embodiment. On-Line
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`Techs., Inc. v. Bodenseewerk Perkin-Elmer GmbH, 386 F.3d 1133, 1138 (Fed. Cir.
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`2004). As previously mentioned, the specification describes the alternative “cross-
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`reference” embodiment in multiple locations including the Abstract, Summary of
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`the Invention (e.g., col. 2:47-50), and Detailed Description (e.g., col. 5:32-45).
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`Mentor argues that the challenged claims exclude this embodiment because “rather
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`than adding instrumentation signals (and associated logic) to the specified circuit,
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`an external ‘cross-reference database’ uses ‘already existing signals’ to evaluate
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`whether a particular line of source code is active.” Response at 33; see also
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`Sarrafzadeh Dec., ¶ 35. Mentor’s explanation does nothing more than restate the
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`issue (i.e., whether already existing signals can be instrumentation signals).
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`3. Mentor’s extrinsic evidence cannot overcome the intrinsic
`record.
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`Mentor’s citation to extrinsic evidence cannot overcome the unambiguous
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`intrinsic evidence. Rolls-Royce, PLC v. United Techs. Corp., 603 F.3d 1325, 1337
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`(Fed. Cir. 2010). Apart from being extrinsic evidence, Mentor’s citation to
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`dictionary definitions of “instrumentation” are not persuasive for at least two
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`additional
`
`reasons:
`
`(1)
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`they purport
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`to define “instrumentation” instead of
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`“instrumentation signal” which is the disputed claim term and (2) they are from
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`publications in the field of computer software, not the logic verification field most
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`relevant to the challenged claims in the ’376 patent.
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`III. GREGORY ANTICIPATES THE CHALLENGED CLAIMS.
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`The Board instituted a trial on claims 1-9, 11, 28, and 29 of the ʼ376 patent.
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`Gregory anticipates each of these claims. Mentor asserts that Synopsys fails to
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`make “even a prima facie showing” that Gregory anticipates claims 3-9, 11, and
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`28-29 because Synopsys cites to both Figs. 8-10 (disclosing the use of a single
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`probe) and Figs. 12-19 (disclosing the use of multiple probes) for support.
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`Response at 40-41. Read in context, Gregory Figs. 12-19 illustrate a convenient
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`extension of the single probe statements of Figs. 8-10 to identify multiple
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`statements and is thus easily distinguished from the Net MoneyIN, Inc. v. VeriSign,
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`Inc. case relied on by Mentor which involved “two separate protocols.” 545 F.3d
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`1359, 1371 (Fed. Cir. 2008). Tellingly, at other places in its Response Mentor
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`admits that the “example presented in FIGS. 16 and 18 operates in much the same
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`way as the single probe statement presented in FIGS. 6-10.” Response at 55.
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`A. Gregory Anticipates Claim 1.
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`1. Gregory satisfies the “instrumentation signal” limitation.
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`Under its construction, the Board determined that “Gregory discloses [the
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`instrumentation signal] limitation by describing that the translation, or synthesis
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`process, injects information into the resulting netlist when a probe is encountered,
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`which results in components of the final circuit that are traceably related to the
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`source code.” Paper 16 at 24. Mentor does not seriously dispute the Board’s
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`finding that Gregory satisfies the “instrumentation signal” limitation as construed
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`by the Board. See, e.g., Response at 42 (admitting that Gregory “[preserves]
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`circuit components in order to provide a traceable relation to source HDL code.”).
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`Rather, Mentor argues only that Gregory does not meet the “instrumentation
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`signal” limitation under Mentor’s proposed construction. Response at 41-46.
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`Because the Board’s construction is correct, Mentor’s argument must fail.
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`Mentor’s argument that Gregory does not disclose additional logic gates
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`under Mentor’s narrow construction is also flawed. Mentor incorrectly argues that
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`the block probe example in Gregory Fig. 18 does not disclose instrumentation
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`signals because it merely re-labels signals. Response at 55-56. Gregory’s
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`additional logic gates are apparent by observing that the instrumented circuit of
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`Fig. 18 has two more logic gates than the corresponding uninstrumented circuit in
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`Fig. 14. A similar analysis applies to Gregory Figs. 7 and 10.
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`2. Gregory satisfies the “execution status” limitation.
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`The Board previously, and correctly, determined that Gregory also satisfies
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`the “execution status” limitation:
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`“Gregory discloses [the execution status]
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`limitation by describing that
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`the translation, or synthesis process,
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`injects
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`information into the resulting netlist when a probe is encountered, which results in
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`components of the final circuit that are traceably related to the source code.” Paper
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`16 at 24. It is telling that Mentor relies on an example generated by its expert that
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`is allegedly “equivalent to the circuit in FIG. 9” to argue that Gregory does not
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`meet
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`the “execution status” limitation. Response at 49. Whether Mentor’s
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`example satisfies the claim limitation is irrelevant. What matters is whether
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`Gregory satisfies the limitation, which it does.
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`Mentor implicitly—and improperly—offers an overly narrow construction
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`of the “execution status” limitation by arguing that looking solely at the “tempout”
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`signal in Gregory Fig. 9 does not indicate whether the “if” statement in Fig. 8 was
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`satisfied. Response at 46-50. In doing so, Mentor repeats the same error it made
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`when construing “instrumentation signal”—namely, excluding the alternate
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`embodiment. With respect to the alternate embodiment, the specification explains
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`that “already existing signals in the form of instrumentation logic [] can be
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`evaluated during simulation to determine whether a particular line of the RTL
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`source code is active.” ’376 at 5:35-38. Similarly, the specification subsequently
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`elaborates
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`that “[t]o verify the execution status of every branch,
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`the
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`instrumentation process need only ensure that each branch is instrumented either
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`explicitly or implicitly.” ’376 at 12:33-38.
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`Even if it were necessary to determine that the “C and B” condition in the
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`“if” statement of Gregory Fig. 8 were met
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`to satisfy the “execution status”
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`requirement, Gregory does so. The output of AND gate 232 in Fig. 9 indicates the
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`execution status of the “if” condition. Any argument that signals B and C cannot
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`be instrumentation signals ignores the alternate embodiment which specifically
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`contemplates implicit instrumentation and the use of already existing signals to
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`determine execution status. Moreover, claim 1 recites “a gate-level netlist
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`including at least one instrumentation signal.”
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`B. Gregory Anticipates Dependent Claims 2-4.
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`Claim 2. Mentor’s arguments regarding claim 2 are moot because Mentor
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`filed a Motion to Amend in which it “proposed substitute claim 37 [that] is not
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`contingent and the Board is requested to replace original claim 2 with substitute
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`claim 37.” Motion to Amend at 5. Regardless, Gregory anticipates claim 2.
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`Similar to its “execution status” argument in claim 1, Mentor argues that
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`Gregory’s “tempout [signal] does not result in ‘generating instrumentation logic …
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`as if the source code included a corresponding signal assignment statement within
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`a same executable branch of
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`the source code as the identified statement.’”
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`Response at 50-51 (emphasis in original). Mentor’s argument here fails for the
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`reasons explained above with respect to “execution status.”
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`Because Gregory generates instrumentation signals by preserving signal
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`assignment statements in the source code,
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`the claimed “corresponding signal
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`assignment statement” is necessarily present in the “same executable branch of the
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`source code as the identified statement.”
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`In other words, Gregory generates
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`instrumentation signals not only “as if” the source code included a corresponding
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`assignment
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`in the same source code branch but because such an assignment
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`actually exists in the source code branch. For example, the signal assignment
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`statement Z <= not(A or B) in Fig. 8 is inside the “if” statement.
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`IPR2012-00042
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`Claim 3. Mentor argues that Gregory is missing the “initializing a marker”
`
`limitation of claim 3 because “the cited feature in Gregory is a signal, not a
`
`variable.” Response at 51 (emphasis in original). Mentor’s argument fails because
`
`it does not use the broadest reasonable construction for the term “marker.”
`
`37 C.F.R. § 100(b). Mentor’s argument is premised on the distinction drawn in the
`
`VHDL Standard between signals and variables. Mentor argues:
`
`The VHDL Standard incorporated by reference into Gregory defines
`variables and signals.
`In VHDL, variables are declared by the term
`“VARIABLE” and are assigned values using the symbol “:=”.
`Signals, on the other hand, are declared with the term “SIGNAL” and
`are assigned values using the symbol “<=”.
`
`Response at 52 (internal cites omitted).
`
`However, nothing in claim 3 (or claim 1 from which claim 3 depends) limits
`
`claim 3 to VHDL.3
`
`Indeed, claim 3 uses the generic term “marker” rather than
`
`“variable.” Nor does the specification restrict claim 3 to VHDL. To the contrary,
`
`the ’376 patent specification provides numerous examples of
`
`instrumenting
`
`Verilog source code. See ’376 Figs. 8-10 and 15-16 (and related discussion).
`
`3 Even if claim 3 were limited to VHDL, which it is not, the specification uses
`See ’376 at 8:42-43 (“In one
`variables as only one example of a marker.
`embodiment, markers such as variable assignment statements are used …”).
`
`OHSUSA:754079484.5
`
`13
`
`
`
`Petitioner’s Reply to Patent Owner’s Response
`
`IPR2012-00042
`
`A broader construction than that offered by Mentor is further supported by
`
`the language in claim 1 which generically refers to “a register transfer level (RTL)
`
`synthesizable source code” without specifying that it is VHDL, Verilog, or any
`
`other type of RTL source code. Thus, Mentor’s proposed construction that
`
`“marker” is limited to the VHDL syntax for “variable” is incorrect because it fails
`
`to apply the broadest reasonable construction standard.
`
`Claim 4. Mentor does not separately argue the patentability of claim 4 and it
`
`will rise or fall with claim 3 from which it depends.
`
`C. Gregory Anticipates Claim 5.
`
`The only limitation Mentor
`
`argues
`
`is missing from claim 5 is
`
`“instrumentation signal.” For all the reasons explained above with respect to 1,
`
`Gregory satisfies the “instrumentation signal” limitation of claim 5.
`
`D. Gregory Anticipates Dependent Claims 6-9 And 11.
`
`Claim 6. Mentor makes two arguments why Gregory does not anticipate
`
`claim 6.
`
`First, Mentor argues that Gregory discloses a “signal assignment
`
`statement” which is not a “variable assignment statement” as required by claim 6.
`
`Response at 56-57. As explained with respect to claim 3, Mentor’s argument fails
`
`because it does not use the broadest
`
`reasonable construction of “variable
`
`assignment statement.” Second, Mentor argues that Gregory does not meet the
`
`“inserting” limitations of claim 6. The Board previously accepted the arguments in
`
`OHSUSA:754079484.5
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`14
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`
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`Petitioner’s Reply to Patent Owner’s Response
`
`IPR2012-00042
`
`Synopsys’ Petition that Gregory anticipates claim 6. Paper 16 at 28. Mentor has
`
`failed to overcome these arguments and the Board should invalidate claim 6.
`
`Claim 7. The Board previously accepted the arguments in Synopsys’
`
`Petition that Gregory anticipates claim 7. Paper 16 at 28. Mentor has failed to
`
`overcome these arguments and the Board should invalidate claim 7.
`
`Claims 8 and 9. Mentor does not separately argue the patentability of
`
`claims 8-9 and these claims will rise or fall with claim 5 from which they depend.
`
`Claim 11. Mentor does not separately argue claim 11 other than to contend
`
`that the Petition raised only an obviousness challenge. Response at 41. Mentor is
`
`incorrect; the Petition explicitly states that “Gregory (Ex. 1007) anticipates claims
`
`1-9, 11-14, 24-25 and 28-33 under section 102.” Petition at 4; see also id. at 12
`
`and 38. Thus, claim 11 will rise or fall with claim 5 from which it depends.
`
`E. Gregory Anticipates Claims 28-29.
`
`Mentor does not argue the patentability of claims 28-29 separately from
`
`claim 1 and these claims will rise or fall with claim 1. Response at 60.
`
`IV. CONCLUSION.
`
`For the foregoing reasons, Synopsys respectfully requests that the Board
`
`invalidate claims 1-9, 11, 28, and 29 of the ʼ376 patent as anticipated by Gregory.
`
`OHSUSA:754079484.5
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`15
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`
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`Petitioner’s Reply to Patent Owner’s Response
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`IPR2012-00042
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`Dated:
`
`September 6, 2013
`
`Respectfully submitted,
`
`By: /WilliamWright/
`
`William H. Wright
`CA Bar No. 161580
`Registration No. 36,312
`wwright@orrick.com
`ORRICK, HERRINGTON, &
`SUTCLIFFE LLP
`777 South Figueroa Street, Suite 3200
`Los Angeles, California 90017
`Tel: 213-629-2020
`Fax: 213-612-2499
`
`Travis Jensen
`CA Bar No. 259925
`Registration No. 60,087
`tjensen@orrick.com
`ORRICK, HERRINGTON, &
`SUTCLIFFE LLP
`1000 Marsh Road
`Menlo Park, CA 94025-1015
`Tel: 650-614-7400
`Fax: 650-614-7401
`
`Attorneys for Petitioner,
`Synopsys, Inc.
`
`OHSUSA:754079484.5
`
`16
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`Petitioner’s Reply to Patent Owner’s Response
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`IPR2012-00042
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`CERTIFICATE OF SERVICE
`
`The undersigned certifies e-mail service on the Patent Owner pursuant to 37
`
`C.F.R. § 42.6(e) and agreement of counsel of a true copy of the foregoing
`
`PETITIONER’S REPLY TO PATENT OWNER’S RESPONSE to counsel of
`
`record for Patent Owner as follows:
`
`Christopher L. McKee and Michael S. Cuviello
`
`Mentoripr@bannerwitcoff.com
`
`Dated:
`
`September 6, 2013
`
`By:
`
`/AnitaChou/
`Anita Chou
`
`OHSUSA:754079484.5
`
`17
`
`
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