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`SYNOPSYS 1014, Synopsys V. Mentor, IPR2012-00042
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`
`
`FIELD-PROGRAMMABLE GATE
`
`ARRAY TECHNOLOGY
`
`edited by
`
`Stephen M. Trimberger
`Xt'linx
`
`with contributions by
`
`I
`
`l
`
`1
`‘
`
`I
`
`ll
`1
`
`Xitinx
`
`Dennis McCarty
`Telle Whitney
`Acte!
`
`and
`
`StephenM.Trimberger
`RobertHartmann
`
`The Technical Staff of Altera Corporation
`
`edited by
`
`I5“
`
`KLUWER ACADEMIC PUBLISHERS
`Boston ! Dordrechtt' London
`
`-- —____
`
`
`
`2
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`SYNOPSYS 1014, Synopsys V. Mentor, IPR2012-00042
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`SYNOPSYS 1014, Synopsys v. Mentor, IPR2012-00042
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`__|_____
`
`
`
`to ross
`
`who had a vision
`
`Distributors for North America:
`Kiuwer Academic Publishers
`
`101 Philip Drive
`Assinippi Park
`Norwell, Massachusetts 02061 USA
`
`Distributors for all other countries:
`
`Kiuwer Academic Publishers Group
`Distribution Centre
`Post Office Box 322
`
`3300 AH Dordrecht, THE NETHERLANDS
`
`
`Library of Congress Cataloging-ln-Publlcation Data
`
`Field -programmable gate array technology 2‘ edited by Stephen M.
`Trimberger.
`p. cm.
`
`Includes bibliographical references and index.
`ISBN U-7923-9419»4 {acid-free paper)
`1. Gate array circuits. 2. Programmable logic devices.
`3. Programmable array logic.
`i. Trimberger, Stephen, 1955 -
`TK7895.G36F54
`1994
`621 .39'5--dc20
`
`93-39703
`CIP
`
`Copyright © 1994 by Kluwer Academic Publishers
`
`All rights reserved. No part ofthis publication may be reproduced, stored in a retrieval
`system or transmitted in any form or by any means, mechanical, photo—copying, recording,
`or otherwise, without the prior written permission of the publisher, Kluwcr Academic
`Publishers, 101 Philip Drive, Assinippi Park, Norwell, Massachusetts 02061.
`
`Printed on acid-free paper.
`
`Printed in the United States of America
`
`
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`64
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`FPGA Technology
`
`SRAM Programmable FPGAs
`
`65
`
`nets and paths with maximum delay values. These constraints can be provided as
`annotation in the schematic or in a separate design constraints file.
`
`intervention in FPGA partitioning can take the form of a CLBMAP, a
`Manual
`schematic-level constraint that forces the partitioner to accept a user-defined mapping
`for part of the logic. The CLBMAP is a cell in the library that a designer connects in
`parallel with the logic it is mapping. The CLBMAP represents no logic, but its
`connections are used to guide the partitioner to implement the mapped logic in a
`single CLB. A designer can go further, designing in tenns of CLBs with their
`programming.
`
`The XACT Design Editor {XDE) (figure 2.4.6) is an interactive graphical editor
`similar in concept to MPGA wiring editors. XDE contains both the logical and
`physical descriptions of the design. Users modify both descriptions simultaneously as
`they design the circuit. A designer can use XDE to pre-place and route CLBs or to do
`post-placement and routing fixup. XDE can also be used as a complete design system,
`allowing a designer to map the logic manually onto the device. XDE can accept a
`netlist as input. or a design can be created and implemented completely in XDE.
`
`
`
`Figure 2.4.6. XDE Screen.
`
`XDE includes the checking and editing functions required for manual design,
`including a design rules checker, a timing verifier and a router. XDE allows a designer
`to turn on or off individual pips in the interconnect, to set the functionality of function
`tables, and to control the functions in CLBs and IOBS.
`
`XDE provides the front-end interface to the debugging system as well. allowing
`Simple modifications of the design. It includes commands to generate probe points,
`internal signals routed out to unused pads to allow external access to internal nodes
`for debugging a design. The probe modifications are incorporated into a debugging
`version of the design that is then loaded into the FPGA for testing. XDE stores the
`probe points separately from the base design. so they can be eliminated easily when
`prototype debugging is complete.
`
`2.5. The Future
`
`FPGAs are similar to MPGAs in many respects, so there is a large body of knowledge
`that a researcher can draw upon to apply in this area. However, the space of FPGA
`architecture is large and relatively unexplored, providing many profitable areas for
`research. These unexplored areas may eventually yield significantly better FPGAs in
`terms of density and performance. Since software depends on the architecture, many
`software questions will opened or re-opened by FPGA architecture innovation.
`
`Programming Technology
`
`The CPLD-style array architectures, built with EPROM or EEPROM transistors.
`cannot be scaled beyond thousands of gates of logic. The array of transistors scales
`quadratically. as does static power consumption, while delays increase. All
`large-
`capacity EPROM devices show significantly degraded speed relative to smaller
`devices, as well as massive power requirements. Managing the size and power
`consumption requires a multi-level
`logic organization, such as the island-style
`architectures described in this chapter. EPROM transistors are only efficient when
`built in large arrays, so they become inefficient in these architectures. Recent attempts
`to extend EPROM-based architectures to large devices have separated the EPROM
`section into a straightforward memory array, and placed it next to an SRAM-based
`F'PGA, basically building an SRAM FPGA with a monolithic PROM.
`
`Large antifuse-programmed devices rely on very high reliability of the antifuses
`themselves. A single ten-thousand-gate antifusewbased FPGA may have over a
`million antifuses. Although only a few percent will actually be used by a design, the
`architecture relies on those few percent being correct. If they are not correct.
`the
`FPGA will fail to program correctly, and must be discarded. Discarding devices that
`fail to program is not a serious issue with small devices. where the parts cost ten
`dollars and programming yield is above 99 percent; but on large devices, the parts
`cost hundreds of dollars and the programming yield may be 80 percent. It is unlikely
`that customers will accept discarding 20% of their $500 FPGAs. The quality of
`antifuse manufacture limits the size of antifusc-based devices.
`
`SRAM-programmed devices have none of these drawbacks. They scale well with
`technology improvements and have very low power consumption. They can be built
`with very high quality and fully tested at the factory. For these reasons, the capacity of
`
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