`
`Luc Burgun
`VP, Synopsys Emulation Division
`Verification Group
`November, 2012
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`©Synopsys 2012
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`MG 2024
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`20+ billion gates
`installed so far
`
`October 4th, 2012
`
`What’s New:
`Synopsys Acquires EVE
`
`•
`
`#1 worldwide HW/SW co-
`emulation provider
`–
`450+ emulation systems shipped
`–
`60+ customers worldwide
`
`• Complements and strengthens
`Synopsys verification solution
`– Market-leading emulation
`performance, capacity, cost-per-gate
`Broadest library of transactor VIP
`–
`Large team of emulation experts
`–
`– World-wide presence
`
`• EVE is now part of Synopsys’
`Verification Business Unit
`–
`~140 employees (60% R&D)
`
`©Synopsys 2012
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`ZeBu Hardware Products Overview
`
`ZeBu-Server
`–
`Latest generation of FPGA-based emulators
`able to map very large designs
`– Eminently scalable
`– The new standard for Hardware / Software
`Co-Verification
`
`ZeBu-Blade2
`– Newest member of the ZeBu emulation family
`– The first based on Xilinx Virtex6-LX760
`FPGAs
`– A paradigm shift in emulation, from the lab to
`the desktop, for the entire design team
`
`ZeBu-Blade2 Fast ASIC
`Desktop Emulator
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`©Synopsys 2012
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`Evolution of Emulation…
`“Emulation” = Acceleration + In-Circuit Emulation
`1989
`1995
`2000
`2005
`
`In-Circuit Emulation Synthesizable Test
`Silicon
`Bench Emulation
`
`Co-Simulation
`
`Transaction Based
`Co-emulation
`
`RTL
`
`RTL
`
`TB
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`RTL
`
`Simulator
`
`RTL
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`System
`Models
`
`Video
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`Ethernet
`
`USB
`
`MIPI
`
`I2S
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`• Emulation systems initially only did “In-Circuit Emulation”
`• The market is moving more towards Transaction-Based Verification
`• Emulators now do: Co-simulation, Transaction-Based Ver., STB, In-Circuit
`
`©Synopsys 2012
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`Design Size by Technology Node-
`Derived from ITRS Data
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`M-gates
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`1400
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`1200
`
`1000
`
`800
`
`600
`
`400
`
`200
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`0
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`130
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`90
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`65
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`45
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`32
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`22
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`©Synopsys 2012
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`Tech Node, nm
`5
`CConfidential
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`MG 2024
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`Hi vol MPU
`Hi Perf MPU
`Network
`Cons. Stationary
`Cons. Portable
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`Consumer
`Portable
`at 150M gates
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`
`
`ITRS Drivers, 2010 Update, Consumer
`Portable Devices
`
`No. of
`Processors
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`©Synopsys 2012
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`Growth in SoC Consumer Stationary
`Complexity – 75 Processors Is Coming!!
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`©Synopsys 2012
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`MG 2024
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`Pwr Consumption Going Off the Charts
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`©Synopsys 2012
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`Verification Process Challenge
`
`• Scale in size
`•
`Improve throughput
`• Maintain or reduce absolute design and verification cost
`on a per project basis
`Increase accessibility to more users
`•
`• Reduce the complexity of the traceability and debug
`usage model
`Improve traceability and debug cycle time
`•
`• Make Power Mgmt and Power Estimation integral to
`verification
`
`©Synopsys 2012
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`System-Level Verification Requires
`Merger of ESL Methodology & Hardware,
`
`HW-SW Co-verification
`Methodologies
`
`Project Phases
`
`FAST SoC
`HW-SW Co-verification
`Model
`
`High Speed
`Transaction-level
`Application Debug
`Platforms
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`©Synopsys 2012
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`MG 2024
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`Verification Environment Must Move to
`System-Level
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`ESL
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`RTL
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`©Synopsys 2012
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`RTL and SW Verification Need to Merge
`into System-Level Verification
`Transaction &
`Frame/Packet View
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`Waveform generation
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`SW Debugger
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`zRun
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`Signal access
`
`ICE
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`Memory accessessssss SVASVA
`
`
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`Transactorsctors
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`ESL/SystemC
`
`Comprehensive HW
`Verification
`
`Integration with SW
`Environments
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`©Synopsys 2012
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`Need to Link Virtual Models with
`Implementation Models in Hardware
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`ZeBu Host PC
`
`ZeBu Emulator
`RTB
`SoC
`
`Memory
`
`AXI BUS
`
`DSP
`Core
`
`IP
`Core
`
`HDMI
`Interface
`
`UART
`Interface
`
`DS-5 Debugger
`
`API
`BFM
`
`e-zTest AXI Master e Tes Master
`
`
`TLM-2.0
`
`Connection
`Built-in ISS
`
`Cortex
`A9
`Model
`
`HDMI Display
`
`UART Terminal
`
`API
`BFM
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`e-zTest HDMI Sinke zTe I SiS nk
`
`
`API
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`BFM
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`
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`e-zTest UARTT ART
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`
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`©Synopsys 2012
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`MG 2024
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`Ultimately Migrate to Full Cycle-Acurate
`SoC in Accelerated ESL Verification
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`©Synopsys 2012
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`The Next Generations of Verification
`
`• Test Benches generate real data processed through
`transaction-based IP
`• Capacity must scale with IC Technology Roadmap or it
`will never keep up with design size growth at bleeding
`edge
`Intelligent SW-HW cockpit-type views of the SoC activity
`must evolve providing “insight-level” information
`• All problems and their impacts must be deterministic --
`repeatable and reproducible
`• Power verification is integral to verification process
`
`•
`
`©Synopsys 2012
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`MG 2024
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