`
`Luc Burgun
`VP, Synopsys Emulation Division
`Verification Group
`November, 2012
`
`©Synopsys 2012
`
`1
`
`1
`
`MG 2024
`
`
`
`20+ billion gates
`installed so far
`
`October 4th, 2012
`
`What’s New:
`Synopsys Acquires EVE
`
`•
`
`#1 worldwide HW/SW co-
`emulation provider
`–
`450+ emulation systems shipped
`–
`60+ customers worldwide
`
`• Complements and strengthens
`Synopsys verification solution
`– Market-leading emulation
`performance, capacity, cost-per-gate
`Broadest library of transactor VIP
`–
`Large team of emulation experts
`–
`– World-wide presence
`
`• EVE is now part of Synopsys’
`Verification Business Unit
`–
`~140 employees (60% R&D)
`
`©Synopsys 2012
`
`2
`
`2
`
`MG 2024
`
`
`
`ZeBu Hardware Products Overview
`
`ZeBu-Server
`–
`Latest generation of FPGA-based emulators
`able to map very large designs
`– Eminently scalable
`– The new standard for Hardware / Software
`Co-Verification
`
`ZeBu-Blade2
`– Newest member of the ZeBu emulation family
`– The first based on Xilinx Virtex6-LX760
`FPGAs
`– A paradigm shift in emulation, from the lab to
`the desktop, for the entire design team
`
`ZeBu-Blade2 Fast ASIC
`Desktop Emulator
`
`©Synopsys 2012
`
`3
`
`3
`
`MG 2024
`
`
`
`Evolution of Emulation…
`“Emulation” = Acceleration + In-Circuit Emulation
`1989
`1995
`2000
`2005
`
`In-Circuit Emulation Synthesizable Test
`Silicon
`Bench Emulation
`
`Co-Simulation
`
`Transaction Based
`Co-emulation
`
`RTL
`
`RTL
`
`TB
`
`RTL
`
`Simulator
`
`RTL
`
`System
`Models
`
`Video
`
`Ethernet
`
`USB
`
`MIPI
`
`I2S
`
`• Emulation systems initially only did “In-Circuit Emulation”
`• The market is moving more towards Transaction-Based Verification
`• Emulators now do: Co-simulation, Transaction-Based Ver., STB, In-Circuit
`
`©Synopsys 2012
`
`4
`
`4
`
`MG 2024
`
`
`
`Design Size by Technology Node-
`Derived from ITRS Data
`
`M-gates
`
`1400
`
`1200
`
`1000
`
`800
`
`600
`
`400
`
`200
`
`0
`
`130
`
`90
`
`65
`
`45
`
`32
`
`22
`
`©Synopsys 2012
`
`5
`
`Tech Node, nm
`5
`CConfidential
`
`MG 2024
`
`Hi vol MPU
`Hi Perf MPU
`Network
`Cons. Stationary
`Cons. Portable
`
`Consumer
`Portable
`at 150M gates
`
`
`
`ITRS Drivers, 2010 Update, Consumer
`Portable Devices
`
`No. of
`Processors
`
`©Synopsys 2012
`
`6
`
`6
`
`MG 2024
`
`
`
`Growth in SoC Consumer Stationary
`Complexity – 75 Processors Is Coming!!
`
`©Synopsys 2012
`
`7
`
`7
`
`MG 2024
`
`
`
`Pwr Consumption Going Off the Charts
`
`©Synopsys 2012
`
`8
`
`8
`
`MG 2024
`
`
`
`Verification Process Challenge
`
`• Scale in size
`•
`Improve throughput
`• Maintain or reduce absolute design and verification cost
`on a per project basis
`Increase accessibility to more users
`•
`• Reduce the complexity of the traceability and debug
`usage model
`Improve traceability and debug cycle time
`•
`• Make Power Mgmt and Power Estimation integral to
`verification
`
`©Synopsys 2012
`
`9
`
`9
`
`MG 2024
`
`
`
`System-Level Verification Requires
`Merger of ESL Methodology & Hardware,
`
`HW-SW Co-verification
`Methodologies
`
`Project Phases
`
`FAST SoC
`HW-SW Co-verification
`Model
`
`High Speed
`Transaction-level
`Application Debug
`Platforms
`
`©Synopsys 2012
`
`10
`
`10
`
`MG 2024
`
`
`
`Verification Environment Must Move to
`System-Level
`
`ESL
`
`RTL
`
`©Synopsys 2012
`
`11
`
`11
`
`MG 2024
`
`
`
`RTL and SW Verification Need to Merge
`into System-Level Verification
`Transaction &
`Frame/Packet View
`
`Waveform generation
`
`SW Debugger
`
`zRun
`
`Signal access
`
`ICE
`
`Memory accessessssss SVASVA
`
`
`
`Transactorsctors
`
`ESL/SystemC
`
`Comprehensive HW
`Verification
`
`Integration with SW
`Environments
`
`©Synopsys 2012
`
`12
`
`12
`
`MG 2024
`
`
`
`Need to Link Virtual Models with
`Implementation Models in Hardware
`
`ZeBu Host PC
`
`ZeBu Emulator
`RTB
`SoC
`
`Memory
`
`AXI BUS
`
`DSP
`Core
`
`IP
`Core
`
`HDMI
`Interface
`
`UART
`Interface
`
`DS-5 Debugger
`
`API
`BFM
`
`e-zTest AXI Master e Tes Master
`
`
`TLM-2.0
`
`Connection
`Built-in ISS
`
`Cortex
`A9
`Model
`
`HDMI Display
`
`UART Terminal
`
`API
`BFM
`
`e-zTest HDMI Sinke zTe I SiS nk
`
`
`API
`
`BFM
`
`
`
`e-zTest UARTT ART
`
`
`
`©Synopsys 2012
`
`13
`
`13
`
`MG 2024
`
`
`
`Ultimately Migrate to Full Cycle-Acurate
`SoC in Accelerated ESL Verification
`
`©Synopsys 2012
`
`14
`
`14
`
`MG 2024
`
`
`
`The Next Generations of Verification
`
`• Test Benches generate real data processed through
`transaction-based IP
`• Capacity must scale with IC Technology Roadmap or it
`will never keep up with design size growth at bleeding
`edge
`Intelligent SW-HW cockpit-type views of the SoC activity
`must evolve providing “insight-level” information
`• All problems and their impacts must be deterministic --
`repeatable and reproducible
`• Power verification is integral to verification process
`
`•
`
`©Synopsys 2012
`
`15
`
`15
`
`MG 2024
`
`
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