`
`
`
`
`
`For:
`
`
`
`
`In re U.S. Patent No. 6,947,882
`Application No.:
`
` Filed:
`Sept. 24, 1999
` Issued:
`Sept. 20, 2005
`
`
`Inventors:
`Frederic Reblewski
`Olivier Lepape
`Jean Barbier
`
`Patent Owner: Mentor Graphics
`Corporation
`
`REGIONALLY TIME
`MULTIPLEXED
`EMULATION SYSTEM
`
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`
`
`
`
`
`Trial No.
`
`
`
`
`
`
`
`
`
`IPR 2012-00041
`
`Atty. Dkt. No.
`
`
`007121.00005
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Mail Stop PATENT BOARD
`Patent Trial and Appeal Board
`United States Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`PRELIMINARY RESPONSE BY PATENT OWNER
`UNDER 37 C.F.R. § 42.107
`
`
`
`

`

`Preliminary Response By Patent Owner
`
`
`
`IPR 2012-00041
`
`I.
`
`TABLE OF CONTENTS
`There Is No Reasonable Likelihood of Petitioner Prevailing As
`To A Challenged Claim of the `882 Patent ..................................................... 1
`
`A.
`
`B.
`
`Technology Background ....................................................................... 2
`
`Introduction To and Overview of Patent Owner’s
`Response To Petitioner’s Invalidity Arguments ................................... 3
`
`1.
`
`2.
`
`3.
`
`4.
`
`5.
`
`6.
`
`7.
`
`Is Deficient For Failing To
`The Petition
`Adequately Explain The Relevance Of The
`References To The Claims As Required By 37
`C.F.R. § 104(B)(5) ...................................................................... 4
`
`The Petition Relies On Prior Art That Is The Same
`As Or Substantially The Same As Prior Art
`Considered In The Original Prosecution .................................... 7
`
`Sample ‘191 (SYNOPSYS 1002) ............................................... 8
`
`Chen (SYNOPSYS 1003) ......................................................... 10
`
`Sample ‘760 (SYSNOPSYS 1004) ........................................... 11
`
`Agarwal (SYNOPSYS 1005) .................................................... 12
`
`Obviousness In View Of Sample ‘191, Sample
`‘760, And Agarwal .................................................................... 12
`
`C.
`
`Patent Owner’s Response To Petitioner’s Invalidity
`Arguments ........................................................................................... 13
`
`1.
`
`There Is No Reasonable Likelihood Of Claims 1-4
`Being Found To Be Anticipated Or Rendered
`Obvious By Sample ‘191 (SYNOPSYS 1002). ........................ 13
`
`
`
`i
`
`

`

`Preliminary Response By Patent Owner
`
`
`
`IPR 2012-00041
`
`2.
`
`3.
`
`4.
`
`There Is No Reasonable Likelihood Of Claims 5-
`14 And 17-20 Being Found To Be Anticipated Or
`Rendered Obvious By Sample ‘191 (SYNOPSYS
`1002). ........................................................................................ 22
`
`There Is No Reasonable Likelihood Of Claims 5-8
`And 17-20 Being Found To Be Anticipated Or
`Rendered Obvious By Sample ‘760 (SYNOPSYS
`1004). ........................................................................................ 26
`
`There Is No Reasonable Likelihood Of Claims 5-8,
`17, And 20 Being Found To Be Anticipated Or
`Rendered Obvious Agarwal (SYNOPSYS 1005). .................... 30
`
`II.
`
`Conclusion ..................................................................................................... 35
`
`
`
`
`
`ii
`
`

`

`Preliminary Response By Patent Owner
`
`
`
`IPR 2012-00041
`
`PRELIMINARY RESPONSE BY PATENT OWNER
`UNDER 37 C.F.R. § 42.107
`
`
`
`Patent Owner Mentor Graphics Corporation (hereafter “Patent Owner”)
`hereby respectfully submits this Preliminary Response to the Petition seeking inter
`partes review in this matter. This filing is timely under 35 U.S.C. § 313 and 37
`C.F.R. § 42.107 , as it is being filed within three months of the September 28, 2012
`mailing date of the Notice granting the Petition a filing date of September 26,
`2012.
`
`A trial should not be instituted in this matter as none of the references relied
`upon by Petitioner in its Petition gives rise to a reasonable likelihood of Petitioner
`prevailing with respect to a challenged claim of the U.S. Patent No. 6,947,882 (the
``882 patent), either alone or in any combination with each other.
`
`I.
`
`There Is No Reasonable Likelihood of Petitioner Prevailing
`As To A Challenged Claim of the `882 Patent
`“The Director may not authorize an inter partes review to be instituted
`unless the Director determines that the information presented in the petition filed
`under section 311 . . . shows that there is a reasonable likelihood that the petitioner
`would prevail with respect to at least 1 of the claims challenged . . . .” 35 U.S.C. §
`314(a). As discussed below, all the anticipation rejections proposed in the Petition
`are deficient for failing to set forth each and every feature arranged as recited by
`the respective claims of the ’882 Patent, and thus do not establish a prima facie
`case of anticipation.
`Further, all the obviousness rejections proposed in the Petition lack
`articulated reasoning with a rational underpinning to support a legal conclusion of
`obviousness. KSR Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 418 (2007) (quoting In
`re Kahn, 441 F.3d 977, 988 (Fed. Cir. 2006)). Indeed, the Petition barely provides
`
`
`
`1
`
`

`

`Preliminary Response By Patent Owner
`
`
`
`IPR 2012-00041
`
`“mere conclusory statement[s]” (id.) that the claims are obvious, let alone provide
`cogent reasoning as to why a person of ordinary skill in the art would modify or
`combine the cited documents in the manner recited by the respective claims of the
`’882 Patent. See, e.g., Petition at 13-14: “At a minimum, these claims would have
`been obvious to a person of ordinary skill in the art in view of [cited document].”
`For at least these reasons, the Petition does not show a reasonable likelihood
`of prevailing with respect to even a single one of the challenged claims, and inter
`partes review should not be instituted.
`
`Technology Background
`
`A.
`The `882 patent concerns emulation systems for emulating integrated
`electrical circuit designs. As described in the Background section of the patent,
`“[a] circuit design to be emulated is ‘realized’ on the emulation system by
`compiling a ‘formal’ description of the circuit design, and mapping the circuit
`design onto the logic elements (LEs) of the FPGAs [field programmable gate
`arrays] and the routing chips.” `882 patent (SYNOPSYS 1001) at 1:17-20.
`Time multiplexing of multiple logical signals onto a single pin is a technique
`that had previously been used to reduce the number of interconnects required
`between FPGA chips and routing chips of the emulation system, including
`input/output pins on the chips. The challenged claims of the `882 patent are
`directed to emulation systems that overcome shortcomings in the known emulation
`systems employing time multiplexing of signals.
`In particular, the known systems were constrained by virtue of the clocking
`architectures they employed. Systems such as the “Virtual Wires” system
`described in the Babb et al. article discussed in the Background section of the `882
`patent employed a single clock globally distributed throughout the system and used
`for both clocking the user design (emulation clock) and routing the signals over the
`
`
`
`2
`
`

`

`Preliminary Response By Patent Owner
`
`
`
`IPR 2012-00041
`
`interconnects with time multiplexing. The inventors of the `882 patent departed
`from this known approach, instead employing clocking architectures with plural
`clock signals that are independent of each other, e.g., first and second multiplexed
`interconnections employing clock signals which are independent of each other, and
`the provision of a routing clock signal which is independent of a clock signal used
`for clocking reconfigurable logic elements.
`
`B.
`Introduction To and Overview of Patent Owner’s Response To
`Petitioner’s Invalidity Arguments
`
`The ‘882 patent describes example circuit emulation systems (or emulators)
`that have multiple reconfigurable logic devices (e.g., FPGAs) coupled together by
`interconnects (e.g., wires). In the emulators, the interconnects transfer signal
`values from one reconfigurable logic device to another across the interconnects
`using a routing clock signal. The Petition challenges the validity of claims 1-14
`and 17-20.
`Claims 1-4 are directed to an emulation system including, inter alia, a
`reconfigurable logic device coupled with two other reconfigurable logic devices
`through two time multiplexed interconnects, respectively. In claims 1-4, the
`clocking of the two time multiplexed interconnects is independent. Claims 5-14
`and 17-20 are directed to an emulator for emulating a circuit design including,
`inter alia, input/output circuitry that use at least one signal routing clock signal, a
`first set of reconfigurable logic elements (RLEs) that uses a first clock signal, and a
`second set of RLEs that uses a second clock signal. The signal routing clock signal
`is independent from the first and second clock signals.
`Petitioner relies upon four references:
`• Sample et al., U.S. Patent No. 5,960,191 (SYNOPSYS 1002)
`(hereinafter “Sample ‘191);
`
`
`
`3
`
`

`

`Preliminary Response By Patent Owner
`
`
`
`IPR 2012-00041
`
`• Chen et al., U.S. Patent No. 5,475,830 (SYNOPSYS 1003)
`(hereinafter “Chen”) (cited as part of Sample ‘191)
`• Sample et al., U.S. Patent No. 6,020,760 (SYNOPSYS 1004)
`(hereinafter “Sample ‘760”); and
`• Agarwal et. al., U.S. Patent No. 5,761,484 (SYNOPSYS 1005)
`(hereinafter “Agarwal”)
`Sample ‘191, Sample ‘760, and Agarwal are each directed to multiplexing
`multiple signals over a common physical interconnect using a routing clock, but
`none discloses or renders obvious any of the challenged claims, including the
`“independent” aspects of the clock signals as recited in these claims. Chen is
`directed to the partitioning of a circuit design across multiple programmable logic
`devices and interconnects of an emulator for the purpose of emulating the circuit
`design. Chen does not address the subject of clocking multiplexed interconnects or
`the clocking of input/output circuitry, and thus, does not support the Petitioner’s
`contentions.
`
`1. The Petition Is Deficient For Failing To Adequately Explain The
`Relevance Of The References To The Claims As Required By 37
`C.F.R. § 104(B)(5)
`
`37 C.F.R. § 104(b)(5) states (emphasis added): “the petition must set
`forth: . . . (5) The exhibit number of the supporting evidence relied upon to
`support the challenge and the relevance of the evidence to the challenge raised,
`including identifying specific portions of the evidence that support the
`challenge. The Board may exclude or give no weight to the evidence where a
`party has failed to state its relevance or to identify specific portions of the
`evidence that support the challenge.”
`To comply with § 104(b)(5), the Petition “must set forth . . . the relevance of
`the evidence to the challenge raised.” The wording of the rule indicates that the
`
`
`
`4
`
`

`

`Preliminary Response By Patent Owner
`
`
`
`IPR 2012-00041
`
`identification of specific portions of the evidence is part of this requirement, but
`does not alone satisfy the requirement.
`The Petition provides a deficient discussion and explanation of the relevance
`of the relied upon portions of Sample ‘191, Chen, Sample ‘760, and Agarwal to the
`identified claim elements. For example, the Petition provides no explanation of
`how the references show each and every element “arranged as required by the
`claim” as required for a proper anticipation rejection. See MPEP 2131; Net
`MoneyIN, Inc. v. VeriSign, Inc., 545 F.3d 1359, 1369 (Fed. Cir. 2008) (“Because
`the hallmark of anticipation is prior invention, the prior art reference—in order to
`anticipate under 35 U.S.C. § 102—must not only disclose all elements of the claim
`within the four corners of the document, but must also disclose those elements
`‘arranged as in the claim.’” (citation omitted)). In fact, the Petition actually omits
`the “arranged as required by the claim” requirement for anticipation. See Petition
`at 11-14 (representing that § 102 unpatentability only requires that the reference
`explicitly or inherently disclose each and every element).
`Further, the Petition includes claim charts that merely recite disjointed
`quotations from the references. There is no explanation anywhere in the Petition
`of specifically how the items discussed in the quotations are being applied by the
`Petitioner or why the highlighted language corresponds to (or is otherwise relevant
`to) the claim elements.
`A few example deficiencies are highlighted below:
`• Claim element 1[d] refers to a “first time multiplexed interconnection
`coupled to and situated between the first plurality of reconfigurable logic
`devices and the second plurality of reconfigurable logic devices.” The
`Sample ‘191 claim chart refers to a quotation that mentions “multiplexer
`chips” but the Petition provides no explanation of what portions of the
`quoted materials correspond to these precise elements.
`
`
`
`5
`
`

`

`Preliminary Response By Patent Owner
`
`
`
`IPR 2012-00041
`
`• Claim element 1[e] refers to a “second time multiplexed interconnection
`coupled to and situated between the second plurality of reconfigurable
`logic devices and the third plurality of reconfigurable logic devices.” For
`claim element 1[e], the Sample ‘191 claim chart merely refers back to
`claim element 1[d], and the Petition again provides no explanation of
`what portions of the quoted materials correspond to these precise
`elements.
`• Claim element 1[f] states that the “clocking of the second time
`multiplexed interconnection is independent of clocking of the first time
`multiplexed interconnect.” The Sample ‘191 claim chart refers to a
`quotation that discusses an “Asynchronous Clock Signal 144,” but the
`Petition provides no explanation of how or whether the signal 144 is used
`in connection with the elements in Sample ‘191 identified as elements
`1[a] through 1[e].
`• The quotes from Sample ‘191 for claim element 1[f] also include the
`statement that “A High Speed Asynchronous Clock Signal 144 is
`distributed to all chips in the system.” If the Asynchronous Clock Signal
`144 is distributed to “all chips,” how can it possibly be relied upon to
`show that the “clocking of the second time multiplexed interconnection is
`independent of clocking of the first time multiplexed interconnect”? The
`Petition provides no explanation.
`• The quotes from Sample ‘191 for claim element 1[f] also include
`reference to “a combination of clocks” and “thirty-two distinct clock
`sources.” But the Petition provides no explanation of how or whether
`these “clocks” and “clock sources” have anything to do with claim
`elements 1[a] to 1[e]. For example, where is it established in Sample
`‘191 that any of the referred-to “clocks” and “clock sources” are used by
`6
`
`
`
`

`

`Preliminary Response By Patent Owner
`
`
`
`IPR 2012-00041
`
`the “multiplexer chips” of Sample ‘191 relied on for claim elements 1[d]
`and 1[e]?
`• The Sample ‘191 claim chart and associated discussion includes similar
`defects for claim 5.
`• The Chen, Sample ‘760, and Agarwal claim charts and accompanying
`discussions in the Petition similarly fail to provide any explanations of
`how the quoted language corresponds to the precise elements and
`relationships recited in claims 1 and 5, as well as the other claims of the
`‘882 patent.
`
`2. The Petition Relies On Prior Art That Is The Same As Or
`Substantially The Same As Prior Art Considered In The Original
`Prosecution
`
`35 U.S.C. § 325 states: “In determining whether to institute or order a
`proceeding under this chapter, chapter 30, or chapter 31, the Director may take into
`account whether, and reject the Petition or request because, the same or
`substantially the same prior art or arguments were presented to the Office.”
`Chapter 31 of 35 U.S.C. comprises the statutory framework for inter partes review.
`The Petition relies on prior art that is the same or substantially the same as
`the prior art considered during prosecution. In particular, Sample ‘191 was
`considered (and even applied) by the Examiner; Chen is incorporated by reference
`into Sample ‘191; and Agarwal was considered by the Examiner. Although
`Sample ‘760 was not considered during prosecution, its disclosure is similar to
`(and no more relevant than) Sample `191.
`Further, the Petition does not present Sample ‘191, Chen, and Agarwal in a
`new light. As explained above, the Petition fails to provide any meaningful
`discussion or explanation of the relevance of Sample ‘191, Chen, or Agarwal to the
`elements of the claims. Instead, the Petition includes claim charts that merely
`
`
`
`7
`
`

`

`Preliminary Response By Patent Owner
`
`
`
`IPR 2012-00041
`
`recite disjointed quotations from the references. Merely providing quotations with
`some highlighting from the “old” art does nothing to present the art in a “new”
`light. Instead, by quoting passages from the “old” art without any meaningful
`explanation or discussion, the Petition has done nothing more than present the art
`in the same “old” light already considered by the Examiner, who properly allowed
`the challenged claims.
`
`3. Sample ‘191 (SYNOPSYS 1002)
`Sample ‘191, considered during prosecution of the ‘882 patent, describes
`multiple embodiments of multiplexed interconnects of an emulator, with each
`interconnect using a global clock to transfer signals between FPGAs. With respect
`to certain embodiments, Sample ‘191 uses the term “asynchronous” to describe the
`global clock at different chips or at different pins, and the Petitioner improperly
`relies on this term in attempt to show that the routing clock signals are
`“independent” as recited in claims 1 and 5. In these cases, however, Sample ‘191
`discloses only one global clock signal, a single globally distributed clock signal —
`“asynchronous clock signal 144.” In this sense, the term “asynchronous” in
`Sample’ 191 is used merely to indicate that the single global clock arrives at
`different physical locations in the circuit with different delays caused by different
`wire lengths the clock traverses from a point of origin. The different delays result
`in the same transition of the global clock signal occurring at two different times at
`two different physical locations (e.g., at two different flip-flops). The arrival time
`difference is referred to as “clock skew.”
`In Sample ‘191, some embodiments use a low skew master clock where each
`global clock transition is synchronized at all of the flip flops. Sample ‘191
`(SYNOPSYS 1002) at 11:4-15. In other embodiments the Petitioner relies on, no
`adjustment is made to account for clock skew, and thus the clock remains skewed
`
`
`
`8
`
`

`

`Preliminary Response By Patent Owner
`
`
`
`IPR 2012-00041
`
`at the destinations (it remains “asynchronous” as that term is used in Sample ‘191).
`To be sure, however, there is only one routing clock signal with no independent
`second clock signal. See Sample ‘191 (SYNOPSYS 1002) at 11:2-6 and 41-43.
`The amount of clock skew may not be known to the designer at the time of
`design due to a number of practical considerations, such as the variations in the
`manufacturing process that affect signal propagation delay. Once an integrated
`circuit is manufactured however, the clock skew is fixed and measurable. Even if
`one were to consider the arrival of the clock at different locations as different clock
`signals, a clock transition at one clock destination does not occur without the same
`clock transition occurring at the other clock destinations. Accordingly, the arrivals
`of the clock transition at different locations have a measurable relationship and are,
`thus, not independent.
`Sample ‘191 has the additional shortcoming with respect to claim 1 that the
`embodiments the Petitioner alleges to have “independent” clocks, do not time
`multiplex the signals across the interconnect, and therefore do not have a “time
`multiplexed” interconnect as called for in claim 1. Instead, the embodiments
`described by Sample ‘191 as asynchronous rely on methods of data encoding to
`transmit the signals across the interconnect.
`Still further, Sample ‘191 was applied as a basis of rejecting the disputed
`claims during the original prosecution. As described in the Petition, the examiner
`applied Sample ‘191 in the rejection of claims 1 and 5 (application claims 13 and
`23), but analyzed the rejection based on features of a different claim that was
`eventually canceled. Petition at 8. Applicants traversed the rejection based on the
`examiner’s mistake, and the examiner rightfully withdrew the rejection. The
`Petitioner dismisses the rejection as an oversight, and thus alleges that the
`examiner’s consideration is not pertinent to the question now put forth of whether
`there is a reasonable likelihood that Sample ‘191 renders the claims anticipated or
`
`
`
`9
`
`

`

`Preliminary Response By Patent Owner
`
`
`
`IPR 2012-00041
`
`obvious. To the contrary, the Petitioner’s own description of the ‘882 patent file
`history makes clear that the examiner was quite familiar with the contents of
`Sample ‘191, and that the examiner was obligated to consider whether Sample
`‘191 anticipated or rendered obvious the disputed claims before withdrawing the
`rejection.
`
`4. Chen (SYNOPSYS 1003)
`Chen, which is incorporated by reference in Sample ‘191, and thus
`considered by Petitioner as part of Sample ‘191, discloses methods of partitioning
`a circuit design into multiple different FPGAs of an emulator. The Petitioner relies
`on one sentence in Chen referring to asynchronous clock signals as teaching
`independent clocks. Petition at 25. The Chen reference to “asynchronous” merely
`refers to an assumption for the purpose of clock tree analysis that different clock
`trees of a distributed clock are asynchronous. However, Chen does not disclose
`that the trees are actually asynchronous, much less independent as asserted in the
`Petition.
`Further, no clock in Chen is disclosed as being a routing clock of a
`multiplexed interconnect. Sample ‘191 explicitly states, “the techniques disclosed
`[in Chen] have not been used in combination with any type of time-multiplexing.”
`Sample ‘191(SYNOPSYS 1002) at 2:36-38. Sample ‘191 does not provide any
`guidance how Chen might be used with time multiplexing, other than to show
`generally how to distribute a low skew master clock in a synchronous system. Id.
`at 15:51-62, 19:16-29. Such a synchronous system would not include independent
`clocks, and thus, Chen fails to support the proposition for which Petitioner cites the
`reference (i.e., independent clocking).
`
`
`
`10
`
`

`

`Preliminary Response By Patent Owner
`
`
`
`IPR 2012-00041
`
`5. Sample ‘760 (SYSNOPSYS 1004)
`Sample ‘760 describes a time multiplexing interconnect coupled between
`two FPGAs. To show the “independent” clock signal feature of claim 5, the
`Petitioner relies on a statement in Sample ‘760 that the time multiplexing by the
`I/O interconnect circuit is asynchronous to the signals being time multiplexed.
`Sample ‘760 is similar to Sample ‘191 in that the term “asynchronous” as used
`therein refers to the skew of a global clock at different physical locations in a
`circuit. Sample ’760 does not use “asynchronous” to mean “independent” as in
`claim 5, where the signal routing clock signal is independent of a clock signal for
`clocking reconfigurable logic elements.
`Sample ‘760 discloses two I/O clocks, I/O CLK (0) and I/O CLK(1), which
`are identical to each other but out of phase by a half clock cycle, global to all
`FPGA’s in the system, and global to all signals in the FPGAs. Sample ‘760 further
`discloses that the signals being multiplexed are not synchronized to the global
`clocks at the I/O circuitry. This does not imply independence as suggested by the
`Petitioner, but instead shows that the two clocks, which are global to all signals,
`have some skew (as explained with respect to Sample ‘191). The Sample ‘760
`clock signals and logic signals are not synchronized at the I/O circuitry of the time
`multiplexed interconnect, because when they reach the I/O circuitry, there is skew
`between the different routes of the global clock signals and also skew between the
`different routes of the logic signals that switch relative to the global clock signals.
`The skews add together such that when the logic signals and the clock signals meet
`at the flip flops in the I/O circuitry, their respective transitions no longer occur at
`the same time. But such transitions still depend on the global clock signal, and
`thus, are not independent. Nothing in Sample ‘760 teaches or suggests that
`“asynchronous” as used therein refers to “independent” clocks as recited in claim
`5.
`
`
`
`11
`
`

`

`Preliminary Response By Patent Owner
`
`
`
`IPR 2012-00041
`
`6. Agarwal (SYNOPSYS 1005)
`Agarwal, which was considered during the prosecution of the ‘882 patent,
`discloses another time multiplexing interconnect system acknowledged in the
`background section of the ‘882 patent. 1 Agarwal explicitly discloses that the time
`multiplexing of logical outputs onto a single physical output is limited to a single
`global clock assumed for the system. Agarwal further disclose that asynchronous
`signals “must still be ‘hardwired’ to dedicated FPGA pins.” The Petitioner
`attempts to show that Agarwal includes a pipeline clock (the alleged claim 5
`routing clock) that is independent from an emulation clock (the alleged claim 5
`first clock for RLEs), because the pipeline clock runs at many times the speed of
`the emulation clock. However, in addition to the explicit disclosure that the
`Agarwal system uses a single global clock, the Agarwal pipeline clock period
`subdivides the emulation clock period by the number of logical signals to be
`multiplexed. Such clock division, however, does not make a clock signal
`“independent” as recited in the claims, but rather reflects the dependence of the
`pipeline clock signal on the emulation clock signal.
`
`7. Obviousness In View Of Sample ‘191, Sample ‘760, And Agarwal
`In addition to the Petitioner attempting to show that each cited reference
`anticipates the claims, the Petitioner further makes conclusory statements alleging
`the references render the claims obvious. The Petitioner, however, fails to state
`any ground or rationale to support such a finding, and thus, fails to even put forth a
`
`
`1 The ‘882 patent in the Background section addresses a paper by Jonathan Babb
`et al. (including the inventors of the Agarwal patent), that discloses the “Virtual
`Wires” emulation system that is also the subject of the Agarwal patent.
`
`
`
`12
`
`

`

`Preliminary Response By Patent Owner
`
`
`
`IPR 2012-00041
`
`prima facie case of obviousness. Indeed, the cited references teach away from the
`combination of features recited in the challenged claims.
`None of the references relied upon by Petitioner gives rise to a reasonable
`likelihood of Petitioner prevailing with respect to at least one of the challenged
`claims of the `882 patent.
`
`C.
`
`Patent Owner’s Response To Petitioner’s Invalidity Arguments
`1. There Is No Reasonable Likelihood Of Claims 1-4 Being Found
`To Be Anticipated Or Rendered Obvious By Sample ‘191
`(SYNOPSYS 1002).
`
`Claim 1 reads as follows:
`
`1. An emulation system comprising:
`a first plurality of reconfigurable logic devices;
`a second plurality of reconfigurable logic devices;
`a third plurality of reconfigurable logic devices;
`a first time multiplexed interconnection coupled to
`and situated between the first plurality of reconfigurable
`logic devices and the second plurality of reconfigurable
`logic devices; and
`a second time multiplexed interconnection coupled
`to and situated between
`the second plurality of
`reconfigurable logic devices and the third plurality of
`reconfigurable logic devices, wherein clocking of the
`second time multiplexed interconnection is independent
`of clocking of the first time multiplexed interconnection.
`
`
`
`13
`
`

`

`Preliminary Response By Patent Owner
`
`
`
`IPR 2012-00041
`
`(Emphasis added.) According to the emphasized portion, the claimed emulation
`system include two time multiplexed interconnects that are clocked independent
`from one another. The ‘882 patent states, for example:
`
`Using time multiplexing, multiple logical outputs
`of an FPGA share a single physical output with only one
`of the logical outputs being able to output a signal on the
`in any given clock cycle.
`single physical output
`Similarly, a physical input to an FPGA is shared by
`multiple logical inputs with only one of the logical inputs
`being able to receive an input signal on the physical
`input in any given clock cycle"
`
`SYNOPSIS 1001 at 1:36-45 (emphasis added). Thus, using time multiplexing,
`each interconnect carries only one logical signal in any given respective clock
`cycle of the interconnect, and each clock cycle of the first interconnect occurs
`independent of each clock cycle of the second interconnect.
`
`Sample ‘191 discloses two classes of signal transmission, but each class fails
`to disclose a system that includes “time multiplexed” interconnects in conjunction
`with “independent” clocking of the interconnects.
`The first class includes time-multiplexing schemes described in the abstract
`and illustrated in FIGS. 2-7. These schemes are similar to the prior art solutions
`discussed in the ‘882 patent (1:46:49) in that all of the multiplexed interconnects
`are clocked by a single low skew routing clock that triggers all routing flip-flops
`(e.g., registers) simultaneously. Such schemes fail to disclose the “independent”
`clocking of claim 1 (and claims 2-4 depending therefrom).
`The second class of signal transmission schemes includes schemes
`illustrated in FIGS. 8-10, which are not time multiplexing schemes at all, but
`
`
`
`14
`
`

`

`Preliminary Response By Patent Owner
`
`
`
`IPR 2012-00041
`
`instead are data encoding schemes. While FIG. 8 is the specific embodiment cited
`by the Petitioner for disclosing the claim 1 features, both classes are discussed
`below for completeness. FIG. 2 (showing the first class) and FIG. 8 (showing the
`second class) are reproduced below.
`In FIG. 2, Signal A (40) and Signal B (42) are multiplexed onto External
`Signal (46), synchronously with Mux Clock (44) and Divided Clock (50). Id. at
`7:60 -8:13. Mux Clock (44) is a low skew master multiplexing clock that must be
`distributed to all chips. Id. at 11:2:21. In particular, Sample ‘191 states: “In the
`simple form of time-multiplexing described above [including FIGS. 2-7], a master
`multiplexing clock must be distributed with low skew to all logic chips 10 and
`Mux chips 12 in the system.” Id. at 11:2-6.
`Divided Clock (50) is a divided version of Mux Clock (44) generated by
`clock divider 68 shown in FIG. 3. Id. at 8:16:18.
`
`
`
`15
`
`
`
`

`

`Preliminary Response By Patent Owner
`
`
`
`IPR 2012-00041
`
`When Divided Clock (50) is high, External Signal (46) carries Signal A (40),
`and when Divided Clock (505) is low, External Signal (46) carries Signal B (42).
`Id. at 9-13. Sample ‘191 states, “The clock divider 68 is reset periodically by the
`SYNC-Signal 48 to ensure that all the clock dividers in the system are
`synchronized.” Id. at 8:22-24. Thus, with all divider clocks in the system
`synchronized to a low skew master clock, the Sample ‘191 time multiplexing
`scheme illustrated in FIG. 2 does not include independent clocking of different
`time multiplexed interconnects as recited in claim 1. As noted above, Sample ‘191
`teaches that for time multiplexed interconnects, a low skew master multiplexing
`clock for the entire system is a requirement. Again, Sample ‘191 expressly states:
`“In the simple form of time-multiplexing described above [including FIGS. 2-7], a
`master multiplexing clock must be distributed with low skew to all logic chips
`10 and Mux chips 12 in the system.” Id. at 11:2-6 (emphasis added). Time
`multiplexed interconnects with independent clocking are thus prohibited in Sample
`‘191.
`
`FIGS. 3-7 illustrate embodiments similar or related to the time multiplexing
`scheme of FIG. 2, and similarly require system synchronization of the multiplexing
`clock signal distributed to all logical chips. See e.g., id. at 9:32-34, 11:1-6, 11:13-
`15.
`
`In contrast to the time multiplexing schemes of FIGS. 2-7, FIG. 8 cited by
`Petitioner illustrates another class of signal transmission that relies on encoding
`multiple si