(12) United States Patent
`(10) Patent N0.:
`US 6,737,698 B1
`
`Paul et al.
`(45) Date of Patent:
`May 18, 2004
`
`USOO6737698B1
`
`(54) SHIELDED CAPACITOR STRUCTURE
`
`(75)
`
`Inventors: Susanne AI Paul, Austin, TX (Us);
`Timothy J_ Dupuis, Austin, TX (US);
`-
`-
`-
`All M' leneJad’ Berkeley’ CAGE)
`(73) Assignee: Silicon Laboratories, Inc., Austin, TX
`(US)
`
`(*) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. No.: 10/094359
`
`(22)
`
`Filed:
`
`Mar. 11, 2002
`
`Int. Cl.7 .............................................. H01L 27/108
`(51)
`(52) US. Cl.
`........................ 257/306; 257/306; 257/307
`(58) Field of Search ................................. 257/306, 307,
`257/308, 309; 174/521, 35 R; 438/669,
`393; 396/84; 361/313
`
`(56)
`
`References Cited
`U S PATENT DOCUMENTS
`.
`.
`7/1971 Barber
`3,593,319 A
`9/1989 Cole .......................... 361/328
`4,870,541 A *
`Z133% Elihyama et al‘
`39:3??? 2
`casu
`a
`7
`6/1993 Scott
`.......................... 361/313
`5,220,483 A *
`9/1996 Conder et al.
`..... 174/35 R
`5,552,563 A *
`
`.................... 257/306
`5,583,359 A * 12/1996 Ng et al.
`
`............. 174/52.1
`
`6/1997 Kubota etal.
`5,635,669 A *
`8/1998 Correale, Jr.
`5,789,807 A
`3/1999 Nakajima et al.
`5,880,024 A *
`8/1999 Stolmeijer et al.
`5,939,766 A
`5/2000 Poh ............................ 438/393
`6,066,537 A *
`3/2001 Linder et al.
`..... 257/306
`6,198,123 B1 *
`
`6/2002 Sowlatl et al.
`.............. 257/300
`6,410,954 B1 *
`OTHER PUBLICATIONS
`
`........... 438/669
`
`Sarnavati. Hirad et al., “Fractal Capacitors”, Feb. 6, 1998,
`pp. 256—257. ISSCC98/Session 16/ TD Advanced Radio
`Frequency Circuits/Paper FP 16.6 Digest of Technical
`Papers.
`
`Sarnavati, Hirad et al., “Fractal Capacitors”, Dec. 1998, pp.
`2035—2041, IEEE Journal of Solid—State Circuits, vol. 33,
`No. 12.
`
`>1 cited by examiner
`
`Primary Examiner—David Nelms
`Assistant Examiner—Thinh T Nguyen
`(74) Attorney, Agent, or Firm—Johnson & Assoc.
`
`ABSTRACT
`(57)
`Arnethod and apparatus if provided for shielding a capacitor
`structure formed in a semiconductor device. In a capacitor
`formed in an integrated circuit, one or more shields are
`disposed around layers of conductive strips to shield the
`capacitor. The shields confine the electric fields between the
`.
`.
`.
`hmns 0fthe Shlelds‘
`
`44 Claims, 7 Drawing Sheets
`
`METAL 4—>
`
`METAL 3—+
`
`METAL 2-—>
`
`METAL 1—->
`
`A
`_130_4
`
`A
`_____1304
`
`B
`129.6
`
`B
`1m
`
`A
`M
`
`A
`l3_04.
`
`1308
`
`V
`
`B
`flfi
`
`B
`13.015
`
`1310
`
`V
`
`IVM 1006
`
`IPR of US. Pat. No. 7,994,609
`
`

`

`US. Patent
`
`May 18, 20
`
`04
`
`Shee
`
`t 1 0f
`
`7
`
`US 6,737,698 B1
`
`nl’fn!
`\ //ll
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`
`
`
`
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`Eli; A El
`
`ZCMQWTZW)
`lgm‘jggg
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`alimwm Um)
`glléEJE
`
`m mwrmii
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`
`
`FIG. 2 (Prior Art)
`
`

`

`U.S. Patent
`
`1
`
`4002
`
`7f02
`
`US 6,737,698 B1
`
`89@W%
`WA4_A|MHH"Al
`
`\
`
`a3ABm.4smmALLAH34—F
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`401 \
`
`400
`
`METAL 4+
`
`METAL 3+
`
`METAL 2+
`
`METAL 1->
`
`
`
`
`
`

`

`US. Patent
`
`May 18, 2004
`
`Sheet 3 0f 7
`
`US 6,737,698 B1
`
`500 ’\
`
`METAL 4—»
`
`A
`
`METAL 3—.
`
`A
`
`B
`
`METAL 2—->
`
`A
`M
`
`B
`M
`
`A
`M
`
`A
`53$
`
`METAL 1 —>
`
`B
`
`600 N
`
`METAL 4——+
`
`FIG. 5
`
`A
`
`m
`
`B
`éQfi
`
`'3
`5&6
`
`fl
`
`§0_&
`
`ET
`M M3”
`
`A
`
`m
`
`B
`
`5&5
`
`A
`
`50.4
`
`B
`
`gag
`
`METAL 2—>
`
`A
`@
`
`B
`606
`
`A
`_60_4
`
`B
`M
`
`METAL 1—»
`
`B
`
`FIG. 6
`
`

`

`US. Patent
`
`May 18, 2004
`
`Sheet 4 0f 7
`
`US 6,737,698 B1
`
`IIIIIIIJ
`
`A 2
`
`911
`
`A
`
`M
`
`A 2
`
`95
`
`METAL 3
`
`M ETAL 2
`
`METAL 1 -’
`
`6
`
`B
`76
`
` mTEM
`
`

`

`US. Patent
`
`May 18, 2004
`
`Sheet 5 0f 7
`
`US 6,737,698 B1
`
`METAL 2—>
`
`METAL 1—»
`
`9.9.4
`
`B
`LOG
`
`1ooor\A
`
`METAL 3—»
`
`METAL 2—+
`
`A
`mi
`
`B
`100.
`
`FIG. 9
`
`B
`9&6
`
`A
`9_04
`
`B
`19%
`
`A
`M
`
`A
`M
`
`B
`20.6
`
`A
`10.05
`
`B
`1QQ§
`
`METAL 1 —-+
`
`3
`
`FIG. 10
`
`B
`9_06
`
`A
`2.0.4
`
`3
`100
`
`A
`101M
`
`1 10
`
`

`

`US. Patent
`
`May 18, 2004
`
`Sheet 6 0f 7
`
`US 6,737,698 B1
`
`M
`
`B
`m;
`
`A
`L191
`
`11M
`
`1208
`
`12_o_6
`
`B
`120_6
`
`A
`11%
`
`A
`
`C C .
`
`METAL N—>
`
`_
`L
`META N 1"
`
`A
`mg
`
`B
`
`METAL 2—+
`
`B
`11_0_5
`
`A
`Mi
`
`B
`llQQ
`
`METAL 1 —->
`
`B
`
`FIG. 11
`
`METAL 4—*
`
`B
`
`ETAL
`
`M
`
`3—.
`
`A
`1%
`
`B
`me
`
`METAL 2 -—>
`
`A
`flag
`
`A
`1%
`
`METAL 1 —>
`
`3
`
`FIG. 12
`
`

`

`US. Patent
`
`May 18, 2004
`
`Sheet 7 0f 7
`
`US 6,737,698 B1
`
`2 '3>I" TI'0.)oco
`
`V
`
`ME
`
`L _.
`TA 3
`
`A
`m4
`
`METAL2-—>
`
`A
`w
`
`METAL1——>
`
`B
`13_0@
`
`B
`13%
`
`A
`13%
`
`A
`1 04
`
`3
`mg
`
`B
`1%
`
`m2
`
`‘7
`
`FIG. 13
`
`

`

`US 6,737,698 B1
`
`1
`SHIELDED CAPACITOR STRUCTURE
`
`FIELD OF THE INVENTION
`
`In
`This invention relates to the field of capacitors.
`particular, this invention relates to shielded capacitor struc-
`tures in integrated circuits.
`
`BACKGROUND OF THE INVENTION
`
`There are numerous applications for capacitors formed on
`integrated circuits. In many of these applications, such as
`with high frequency integrated circuits, metal-to-metal
`capacitors are often used because they have a number of
`advantages over other types of capacitors, such as those
`formed from gate oxide. For example, metal-to-metal
`capacitors provide a higher quality factor than gate-oxide
`capacitors, and the quality factor is independent of the dc
`voltage of the capacitor. Also, metal-to-metal capacitors
`provide better linearity than gate-oxide capacitors.
`Typical prior art metal-to-metal capacitors use parallel
`plate structures where the vertical distance between the
`parallel plates is much less than the lateral dimensions of the
`plates. In this case, fringing electric fields are present at the
`edges of the capacitor plates, but most of the electric fields
`are confined to the region between the capacitor plates.
`Another type of prior art capacitor takes advantage of the
`reduced size of intralayer metal spacings. In this type of
`capacitor, vertically spaced fingers are connected to alternate
`capacitor nodes to provide a higher capacitance density than
`parallel plate structures. FIG. 1 is a perspective side view of
`a prior art vertical finger capacitor 100. Note that FIG. 1
`shows the spatial relationship between the capacitor fingers
`and does not show the remainder of the capacitor or the
`integrated circuit.
`FIG. 1 shows a capacitor 100 formed between nodes A
`and B (not shown). The capacitor 100 includes a first set of
`fingers connected to node A and a second set of fingers
`connected to node B. The capacitor fingers shown in FIG. 1
`are formed in four levels of metal in an integrated circuit. As
`shown, the fingers alternate between nodesA and B such that
`each A finger on the second and third levels of metal is
`surrounded by four neighboring B fingers and each B finger
`on the second and third levels of metal is surrounded by four
`neighboring A fingers. This structure provides greatest
`capacitance density when each finger is made from a
`minimum-width line of metal and a minimum spacing
`separates adjacent fingers.
`FIG. 2 is a diagram illustrating the electric fields for the
`capacitor structure shown in FIG. 1. As shown, significant
`electric fields are present around the capacitor fingers. There
`are several disadvantages with prior art capacitors such as
`the capacitor shown in FIGS. 1 and 2. First, the electric fields
`present around the capacitor can interact with materials
`present around the fingers and cause loss in these materials,
`which reduces the quality factor of the capacitor. Second, the
`capacitance of the capacitor shown in FIGS. 1 and 2 is
`difficult to predict because it is impacted by the properties of
`materials around the fingers, which may be different than the
`properties of the dielectric present between the fingers.
`
`SUMMARY OF THE INVENTION
`
`An apparatus of the invention is provided for a capacitor
`structure formed on a semiconductor substrate for providing
`capacitance between a first node and a second node com-
`prising: one or more layers of conductive strips, said con-
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`2
`ductive strips in each layer alternately connected to the first
`and second nodes, and a conductive plate disposed above or
`beneath the lowest of the one or more layers of conductive
`strips.
`invention provides a
`One embodiment of the present
`capacitor structure formed on a semiconductor substrate for
`providing capacitance between a first node and a second
`node comprising: one or more layers of conductive strips,
`each of said conductive strips in each layer being connected
`to one of the first or second nodes, and a conductive shield
`disposed adjacent to the capacitor structure for shielding the
`capacitor structure.
`Other objects, features, and advantages of the present
`invention will be apparent from the accompanying drawings
`and from the detailed description that follows below.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The present invention is illustrated by way of example
`and not
`limitation in the figures of the accompanying
`drawings, in which like references indicate similar elements
`and in which:
`
`FIG. 1 is a perspective side view of a prior art vertical
`finger capacitor.
`FIG. 2 is a diagram illustrating the electric fields for the
`capacitor structure shown in FIG. 1.
`FIG. 3 is a schematic diagram of a power amplifier
`formed on an integrated circuit that may utilize the capacitor
`structures of the present invention.
`FIG. 4 is sectional view of an example of a capacitor
`structure of the present invention.
`FIGS. 5—13 show additional examples of shielded capaci-
`tors of the present invention.
`DETAILED DESCRIPTION
`
`invention solves the problems discussed
`The present
`above by providing shielding to a capacitor structure formed
`in a semiconductor device. In general, the present invention
`provides a capacitor formed in an integrated circuit with one
`or more layers of conductive strips (i.e., capacitor fingers)
`connected to one of two nodes of the capacitor. One or more
`shields are disposed adjacent to the layers of conductive
`strips and are also connected to one of the nodes. The shields
`confine the electric fields between the nodes between the
`
`limits of the shields. As described below, the present inven-
`tion may include numerous variations within the spirit and
`scope of the invention.
`In order to provide a context for understanding this
`description, the following illustrates one example of a typi-
`cal application of the present invention. The present inven-
`tion may be used in any desired application, such as with
`high frequency integrated circuits.
`In one example,
`the
`present
`invention may be used with a power amplifier
`formed on an integrated circuit. FIG. 3 is a schematic
`diagram of a power amplifier 302 formed on an integrated
`circuit for use with a wireless transmission system such as
`a wireless telephone or other device. The power amplifier
`302 includes capacitors C1 and C2, which may be imple-
`mented using the shielded capacitor structure of the present
`invention. In the case of a wireless telephone application, the
`invention may be applied to GSM, CDMA, PCS, DCS, etc.,
`or other wireless systems. Of course, the present invention
`may be used in any application where a shielded capacitor
`structure is desirable.
`
`FIG. 4 is sectional view of an example of a capacitor
`structure of the present invention. FIG. 4 shows a capacitor
`
`

`

`US 6,737,698 B1
`
`3
`400 formed on a silicon substrate 402 as part of an integrated
`circuit 401 (other components of the integrated circuit 401
`are not shown). Note that the structure of the integrated
`circuit 401 extends beyond what is shown in FIG. 4. For
`example,
`the structure of the integrated circuit 401 may
`extend past the capacitor 400, as shown in FIG. 4. The
`integrated circuit 401 may also include components placed
`above or below the capacitor 400. Similarly, this also applies
`to the embodiments shown in FIGS. 5—13 (described below),
`even though FIGS. 5—13 only show the capacitors.
`The capacitor 400 is built using four layers of metal,
`designated as METAL 1, METAL 2, METAL 3, and METAL
`4. Formed in the METAL 2 layer is a first row of conductive
`strips. A first set of conductive strips 404 is connected to
`node Aof the capacitor. Similarly, a second set of conductive
`strips 406 is connected to node B of the capacitor. In the
`example shown in FIG. 4, the conductive strips 404 and 406
`alternate, although other configurations may also be used. A
`second row of conductive strips is formed in the METAL 3
`layer. The second row of conductive strips also has first and
`second sets of conductive strips 404 and 406 connected to
`nodes A and B of the capacitor. In the example shown in
`FIG. 4, the conductive strips 404 in the METAL 3 layer are
`positioned above conductive strips 406 in the METAL 2
`layer. FIG. 4 also shows a first shield 408 formed in the
`METAL 4 layer above the conductive strips. The shield 408
`is formed by a solid conductive plate and is connected to
`node A of the capacitor. Asecond shield 410 is formed in the
`METAL 1 layer below the conductive strips. The shield 410
`is formed by a solid conductive plate and is connected to
`node B of the capacitor. A dielectric material, or insulating
`layers, surrounds and separates the various metal layers.
`FIG. 4 also illustrates the electric fields present in the
`capacitor 400. As shown, the shields 408 and 410 confine the
`electric fields from node A to node B (as illustrated by the
`arrows) within the limits of the shields 408 and 410. One
`advantage of the capacitor structure shown in FIG. 4 is that
`the capacitance value of the capacitor 400 can be more
`accurately predicted because it
`involves only the metal
`conductors and the dielectric insulator between them. Also,
`the electric field from nodes A to B does not pass through
`materials such as the Silicon substrate 402 below the first
`
`metal layer or components above the top metal layer. One
`disadvantage of the capacitor structure shown in FIG. 4,
`compared to a prior art non-shielded capacitor taking up the
`same area,
`is that
`it has less capacitance per unit area
`because there is little field between the “A” shield 408 and
`
`the “A” conductive strips 404 located below it. Similarly
`there is little field between the “B” shield 410 and the “B”
`
`conductive strips 406 located above it. The capacitor struc-
`ture of FIG. 4 has shunt capacitance from the shield 410 to
`any conductors below the first metal layer and from the
`shield 408 to any conductors above the topmost metal layer.
`However, this shunt capacitance does not affect value of the
`capacitance between nodes A and B and may not need to be
`predicted as accurately. In most cases, shunt capacitance to
`the shield 408 is very small but that to the shield 410 from
`the underlying Silicon substrate 402 is fairly large. So, this
`structure is useful in cases where shunt capacitance from
`node B is less critical than shunt capacitance from node A.
`Ashielded capacitor structure of the present invention can
`take on many configurations in addition to the example
`shown in FIG. 4. FIGS. 5—13 show additional examples of
`shielded capacitors of the present invention. Note that, in
`addition to the examples given, other embodiments are also
`possible. In addition, various combinations of configurations
`are also possible.
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`4
`FIG. 5 shows a capacitor 500, which is similar to the
`capacitor 400 shown in FIG. 4, except that the conductive
`strips 504 and 506 are arranged differently. Like FIG. 4, FIG.
`5 includes a first shield 508 formed in the METAL 4 layer
`and a second shield 510 formed in the METAL 1 layer. The
`conductive strips 504 connected to node A in the METAL 3
`layer are positioned above the conductive strips 504 con-
`nected to node A in the METAL 2 layer. Similarly, the
`conductive strips 506 connected to node B in the METAL 3
`layer are positioned above the conductive strips 506 con-
`nected to node B in the METAL 2 layer.
`FIG. 6 shows an example of a capacitor 600 where the
`conductive strips 604 and 606 are not all the same size and
`not all aligned. The capacitor 600 may be used, for example,
`when the process-specified minimum widths of conductors
`in one metal layer (e.g., METAL 2) is different from that in
`another metal layer (e.g., METAL 3). Conductive strips in
`various layers can therefore have the same or different
`widths and spacing.
`FIG. 7 shows an example of a capacitor 700 where the
`shields 708 and 710 are comprised of conductive strips 704
`and 706 rather than a continuous metal plate. The shields
`708 and 710 are illustrated by a dashed box around the
`conductive strips formed in the METAL 1 and METAL 4
`layers.
`in
`FIG. 8 shows an example of a capacitor 800 that,
`addition to the top shield 808 and the bottom shield 810, has
`a side shield 812. The side shield 812 is formed by conduc-
`tive strips 804 formed on the METAL 1, 2, and 3 layers and
`connected to node A. In this example, the conductive strips
`804 of the side shield 812 are connected to each other, and
`to the top shield 808, by vias 814. Of course, the side shield
`812 could also be made from conductive strips 806 con-
`nected to node B. If desired, a side shield could be formed
`on both sides of the capacitor 800, or used without top and/or
`bottom shields.
`
`FIG. 9 shows an example of a capacitor 900 similar to the
`capacitor 400 shown in FIG. 4 with only a top shield 908.
`Similarly, FIG. 10 shows a capacitor 1000 with only a
`bottom shield 1010. In some applications, only one shield
`may be necessary. For example, when the properties and
`geometries of materials above the topmost capacitor metal
`layer are well known, but isolation from the substrate is
`desirable, then a structure can be used that includes only the
`lower shield plate 1010 (FIG. 10). However, if the properties
`and geometries of materials above the topmost capacitor
`metal layer make an upper shield desirable, and a lower
`shield is not desirable, then a structure can be used that
`includes only the upper shield plate 908 (FIG. 9).
`A capacitor structure of the present invention may be
`formed using any number of layers of conductive strips.
`FIG. 11 shows an example of a capacitor 1100 formed on N
`metal layers and having N—2 layers of conductive strips 1104
`and 1106.
`
`The shields of the present invention may take on numer-
`ous forms in addition to the examples described above. For
`example, FIG. 12 shows an example of a capacitor 1200
`where the top shield 1208 and bottom shield 1210 are
`connected to the same node (node B in this example). FIG.
`13 shows an example of a capacitor 1300 where the top and
`bottom shields 1308 and 1310 are connected to a third node,
`shown in this example as reference voltage (e.g., ground)
`rather than to nodes A or B.
`
`the invention is
`In the preceding detailed description,
`described with reference to specific exemplary embodiments
`thereof. Various modifications and changes may be made
`
`

`

`US 6,737,698 B1
`
`5
`thereto without departing from the broader spirit and scope
`of the invention as set forth in the claims. The specification
`and drawings are, accordingly, to be regarded in an illus-
`trative rather than a restrictive sense.
`What is claimed is:
`1. A capacitor structure formed on a semiconductor sub-
`strate for providing capacitance between a first node and a
`second node comprising:
`a plurality of layers of conductive strips, said conductive
`strips in each layer alternately connected to the first and
`second nodes, and
`a conductive plate disposed beneath the lowest of the
`plurality of layers of conductive strips, wherein said
`conductive plate is connected to one of the nodes.
`2. The capacitor structure of claim 1, wherein said con-
`ductive plate is connected to the first node.
`3. The capacitor structure of claim 1, wherein said con-
`ductive plate is connected to the second node.
`4. The capacitor structure of claim 1, wherein all of said
`conductive strips have the same width and spacing.
`5. The capacitor structure of claim 1, wherein the plurality
`of layers of conductive strips are aligned so that strips
`connected to the first node lie above strips connected to the
`second node.
`6. The capacitor structure of claim 1, wherein the plurality
`of layers of conductive strip are aligned so that strips
`connected to the first node lie above strips connected to the
`first node.
`
`7. The capacitor structure of claim 1, further comprising
`a second conductive plate disposed above the highest of the
`plurality of layers of conductive strips.
`8. The capacitor structure of claim 7, wherein said second
`conductive plate is connected to the second node.
`9. The capacitor structure of claim 7, wherein said second
`conductive plate is connected to the first node.
`10. The capacitor structure of claim 7, wherein said
`second conductive plate is connected to a third node.
`11. The capacitor structure of claim 7, wherein said
`second conductive plate is connected to a reference voltage.
`12. The capacitor structure of claim 7, wherein said
`second conductive plate is connected to ground.
`13. The capacitor structure of claim 1, further comprising
`a second conductive plate disposed above the highest of the
`plurality of layers of conductive strips, said conductive plate
`connected to the first node.
`
`14. The capacitor structure of claim 1, wherein the con-
`ductive plate is comprised of a solid planar conductive
`material.
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`15. The capacitor structure of claim 1, wherein the con-
`ductive plate is comprised of a plurality of conductive strips
`connected to the first node.
`
`50
`
`16. The capacitor structure of claim 1, further comprising
`a conducting side plate disposed to the side of the plurality
`of layers of conductive strips.
`17. The capacitor structure of claim 16, wherein the
`conducting side plate is comprised of one or more conduc-
`tive strips connected together and connected to the conduc-
`tive plate by vias.
`18. The capacitor structure of claim 16, wherein the
`conductive side plate is connected to the first node.
`19. The capacitor structure of claim 16, wherein the
`conductive side plate is connected to the second node.
`20. The capacitor structure of claim 16, wherein the
`conductive side plate is connected to a third node.
`21. The capacitor structure of claim 16, wherein the
`conductive side plate is connected to a reference voltage.
`22. The capacitor structure of claim 16, wherein the
`conductive side plate is connected to ground.
`
`55
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`60
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`65
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`6
`23. The capacitor structure of claim 1, wherein the capaci-
`tor structure forms a metal-to-metal capacitor.
`24. A capacitor structure formed on a semiconductor
`substrate for providing capacitance between a first node and
`a second node comprising:
`a plurality of layers of conductive strip, said conductive
`strips in each layer alternately connected to the first and
`second nodes, and
`a conductive plate disposed above the highest of the
`plurality or layers of conductive strips, wherein said
`conductive plate is connected to one of the nodes.
`25. The capacitor structure of claim 24, wherein said
`conductive plate is connected to the first node.
`26. The capacitor structure of claim 24, wherein said
`conductive plate is connected to the second node.
`27. The capacitor structure of claim 24, wherein all of said
`conductive strips have the same width and spacing.
`28. The capacitor structure of claim 24, wherein the
`plurality of layers of conductive strips are aligned so that
`strips connected to the first node lie above strips connected
`to the second node.
`29. The capacitor structure of claim 24, wherein the
`plurality of layers of conductive strips are aligned so that
`strips connected to the first node lie above strips connected
`to the first node.
`30. The capacitor structure of claim 24, wherein the
`conductive plate is comprised of a solid planar conductive
`material.
`31. The capacitor structure of claim 24, wherein the
`conductive plate is comprised of a plurality of conductive
`strips connected to the first node.
`32. The capacitor structure of claim 24, further compris-
`ing a conducting side plate disposed to the side of the one or
`more layers of conductive strips.
`33. The capacitor structure of claim 32, wherein the
`conducting side plate is comprised of one or more conduc-
`tive strips connected together and connected to the conduc-
`tive plate by vias.
`34. The capacitor structure of claim 32, wherein the
`conductive side plate is connected to the first node.
`35. A capacitor structure formed on a semiconductor
`substrate for providing capacitance between a first node and
`a second node comprising:
`one or more layers of conductive strips, each layer having
`a plurality of conductive strips, and each of said con-
`ductive strips in each layer being connected to one of
`the first or second nodes, and
`a conductive shield disposed adjacent to the capacitor
`structure for shielding the capacitor structure.
`36. The capacitor structure of claim 35, wherein the
`conductive shield is disposed below the capacitor structure.
`37. The capacitor structure of claim 35, wherein the
`conductive shield is disposed above the capacitor structure.
`38. The capacitor structure of claim 35, wherein the
`conductive shield is disposed to the side of the capacitor
`structure.
`
`39. The capacitor structure of claim 35, wherein the
`conductive shield is connected to one of the first or second
`nodes.
`
`40. The capacitor structure of claim 35, wherein the
`conductive shield is connected to a reference voltage.
`41. The capacitor structure of claim 35, wherein the
`conductive shield is connected to ground.
`42. The capacitor structure of claim 35, further compris-
`ing a second conductive shield disposed adjacent to the
`capacitor structure for shielding the capacitor structure.
`43. The capacitor structure of claim 1, wherein conductive
`strips in a first layer of conductive strips have a different
`
`

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`US 6,737,698 B1
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`7
`Width and spacing than conductive strips in a second layer
`of conductive strips.
`44. The capacitor structure of claim 24, wherein conduc-
`tive strips in a first layer of conductive strips have a different
`
`8
`Width and spacing than conductive strips in a second layer
`of conductive strips.
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