X-3004 US
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`12/276,289
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`PATENT
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`Conf. No.: 3744
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`IN THE UNITED STATES PATENT OFFICE
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`Applicant:
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`Patrick J. Quinn
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`Assignee:
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`Xilinx, Inc.
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`Title:
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`SHIELDING FOR INTEGRATED CAPACITORS
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`Serial No.:
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`12/276,289
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`Filed:
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`November 21, 2008
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`Examiner:
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`Errol V. Fernandes
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`Art Unit:
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`2894
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`Docket No.: X-3004 US
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`Conf. No.:
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`3744
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`Mail Stop Amendment
`COMMISSIONER FOR PATENTS
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`PO. Box 1450
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`Alexandria, Virginia 22313-1450
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`AMENDMENT
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`Dear Sir:
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`In response to the Office Action mailed on October 27, 2010, please amend the
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`application as follows.
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`Amendments to the claims begin on page 2 of this paper.
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`Remarks begin on page 7 of this paper.
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`1
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`IPR of US. Pat. No. 7,994,609
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`IVM 1005
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`

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`X-3004 US
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`12/276,289
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`CLAIMS LISTING
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`PATENT
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`Conf. No.: 3744
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`This listing of claims will replace all prior versions and listings of claims in the
`application:
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`IN THE CLAIMS
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`1.
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`(Currently Amended) A capacitor in an integrated circuit (“IC”) comprising:
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`a core capacitor portion having a first plurality of conductive elements
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`electrically connected to and forming a first part of a first node of the capacitor formed
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`in a first conductive layer of the IC and a second plurality of conductive elements
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`electrically connected to and forming a first part of a second node of the capacitor
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`formed in the first conductive layer, the first plurality of conductive elements alternating
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`with the second plurality of conductive elements in the first conductive layer, and a
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`third plurality of conductive elements electrically connected to and forming a second
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`part of the first node formed in a second conductive layer adjacent to the first
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`conductive layer, at least portions of some of the second plurality of conductive
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`elements overlying and vertically coupling to at least portions of some of the third
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`plurality of conductive elements; [[and]]
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`a shield capacitor portion having a fourth plurality of conductive elements
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`formed in at least the first conductive layer of the IC, the second conductive layer of
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`the IC, a third conductive layer of the IC, and a fourth conductive layer of the IC, the
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`first conductive layer and the second conductive layer each being between the third
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`conductive layer and the fourth conductive layer, the shield capacitor portion being
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`electrically connected to and forming a second part of the second node of the
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`capacitor and surrounding the first plurality of conductive elements and the third
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`plurality of conductive elements; and
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`a reference shield electrically connected to a reference node of the IC other
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`than the second node of the capacitor, the shield capacitor portion being disposed
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`between the reference shield and the core capacitor portion.
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`2.
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`(Original) The capacitor of claim 1 wherein the third conductive layer is a metal
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`layer of the IC and the fourth conductive layer is a poly layer of the IC, the shield
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`

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`PATENT
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`Conf. No.: 3744
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`capacitor portion including a first node shield plate formed in the metal layer from a
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`plurality of metal stripes and a second node shield plate formed in the poly layer.
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`3.
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`(Original) The capacitor of claim 1 wherein the shield capacitor portion includes a
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`first node shield plate formed in the third conductive layer and a second node shield
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`plate formed in the fourth conductive layer and further comprising a first conductive
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`curtain extending from the first node shield plate to the second node shield plate and a
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`second conductive curtain extending from the first node shield plate to the second
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`node shield plate.
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`4.
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`(Original) The capacitor of claim 1 wherein the capacitor is a switching capacitor,
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`the first node is a top node of the switching capacitor and the second node is a bottom
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`node of the switching capacitor.
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`5. (Canceled)
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`6.
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`(Currently Amended) IliheA capacitor—ef—elaim—5 in an inte rated circuit “IC”
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`comprising:
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`a core capacitor portion having a first plurality of conductive elements
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`electrically connected to and forming a first part of a first node of the capacitor formed
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`in a first conductive layer of the IC and a second plurality of conductive elements
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`electrically connected to and forming a first part of a second node of the capacitor
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`formed in the first conductive layer, the first plurality of conductive elements alternating
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`with the second plurality of conductive elements in the first conductive layer, and a
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`third plurality of conductive elements electrically connected to and forming a second
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`part of the first node formed in a second conductive layer adiacent to the first
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`conductive layer, at least portions of some of the second plurality of conductive
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`elements overlying and vertically coupling to at least portions of some of the third
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`plurality of conductive elements,
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`a shield capacitor portion having a fourth plurality of conductive elements
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`formed in at least the first conductive layer of the IC, the second conductive layer of
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`the IC, a third conductive layer of the IC, and a fourth conductive layer of the IC, the
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`

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`12/276,289
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`PATENT
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`Conf. No.: 3744
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`first conductive layer and the second conductive layer each being between the third
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`conductive layer and the fourth conductive layer, the shield capacitor portion being
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`electrically connected to and forming a second part of the second node of the
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`capacitor and surrounding the first plurality of conductive elements and the third
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`plurality of conductive elements, and
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`a reference shield electrically connected to a reference node of the IC other
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`than the second node of the capacitor, the shield capacitor portion being disposed
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`between the reference shield and the core capacitor portionI wherein the reference
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`shield includes a substrate portion of a substrate of the IC, a first conductive curtain
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`extending from the substrate portion, and a second conductive curtain extending from
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`the substrate portion.
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`7.
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`(Original) The capacitor of claim 6 wherein the substrate portion comprises an N-
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`well of the substrate of the IC.
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`8. (Previously Presented) The capacitor of claim 6 wherein the reference shield is a
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`first cup shield having an open top.
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`9.
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`(Currently Amended) The capacitor of claim [[5]] 1 wherein the reference node is a
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`VDD node.
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`10.
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`(Withdrawn) The capacitor of claim 5 wherein the reference node is an analog
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`ground node.
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`11.
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`(Original) The capacitor of claim 1 wherein the first plurality of conductive
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`elements comprises a first plurality of conductive strips extending along a first
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`direction, the second plurality of conductive elements comprises a second plurality of
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`conductive strips extending along the first direction, and the third plurality of conductive
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`elements comprises a third plurality of conductive strips extending along a second
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`direction orthogonal to the first direction.
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`

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`12/276,289
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`PATENT
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`Conf. No.: 3744
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`12.
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`(Original) The capacitor of claim 11 wherein each of the conductive elements in
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`the third plurality of conductive elements is adjacent to a conductive element
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`electrically connected to and forming a third part of the first node.
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`13.
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`(Original) The capacitor of claim 12 further comprising a fourth plurality of
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`conductive elements formed in a fifth conductive layer of the IC disposed between the
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`fourth conductive layer and the second conductive layer and electrically connected to
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`and forming a fourth part of the first node, the fourth plurality of conductive elements
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`extending along the first direction, and
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`a fifth plurality of conductive elements electrically connected to and forming a third part
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`of the second node formed in the fifth conductive layer extending along the first
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`direction alternating with the fourth plurality of conductive elements in the fifth
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`conductive layer.
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`14.
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`(Withdrawn) The capacitor of claim 1 wherein the first plurality of conductive
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`elements comprises a first plurality of conductive strips extending along a first
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`direction, the second plurality of conductive elements comprises a second plurality of
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`conductive strips extending along the first direction, and the third plurality of conductive
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`elements comprises a third plurality of conductive strips extending along the first
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`direction.
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`15.
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`(Withdrawn) The capacitor of claim 14 further comprising a fourth plurality of
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`conductive strips electrically connected to and forming a third part of the second node
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`extending along the first direction and alternating with the third plurality of conductive
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`strips in the second conductive layer.
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`16. (Canceled)
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`17. (Canceled)
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`18. (Canceled)
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`12/276,289
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`PATENT
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`Conf. No.: 3744
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`19. (Currently Amended) A capacitor in an integrated circuit (“IC”) comprising:
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`a first plate formed in a first conductive layer of the IC;
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`a second plate formed in a substrate of the IC;
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`a gate dielectric layer disposed between the first plate and the second plate;
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`a shield plate formed in a second conductive layer of the IC having a perimeter
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`electrically connected the second plate so as to form an electrical shield around the
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`first plate,'a_nd
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`a plurality of contacts formed between the shield plate and the second plate;
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`wherein the shield plate has a gap through which an electrical contact to the
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`first plate extends, and the shield plate, the plurality of contacts, and the second plate
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`provide electrical shielding for the first plate.
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`20.
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`(Original) The capacitor of claim 19 wherein the first conductive layer is a first
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`poly layer, the substrate comprises silicon and second plate is formed in an N-well of
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`the substrate and the shield plate is formed in a second poly layer of the IC.
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`21.
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`(Currently Amended) The capacitor of claim [[5]] 1 further comprising a second
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`reference shield connected to a second reference node of the IC, the reference shield
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`being disposed between the second reference shield and the shield capacitor portion.
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`22. (Previously Presented) The capacitor of claim 8 further comprising a second
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`reference shield connected to a second reference node of the IC, the second
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`reference shield including a second reference shield plate extending across the open
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`top of the first cup shield.
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`23. (Previously Presented) The capacitor of claim 22 wherein the second reference
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`shield is a second cup shield.
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`

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`X-3004 US
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`12/276,289
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`PATENT
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`Conf. No.: 3744
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`REMARKS
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`In the Office Action mailed on October 27, 2010, Claims 1, 3, 4 and 11-13 are
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`rejected under 35 USC §102(b) as being anticipated by Fong et al. (U.S. Patent
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`7,259,956, “Fong”). Claim 2 is rejected under 35 USC §103(a) as being upatentable
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`over Fong and further in view of Hajimiri (US. Patent 6,690,570). Claims 19-20 are
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`rejected under 35 USC §103(a) as being unpatentable over Stribely et al. (U.S. Patent
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`6,933,551, “Stribley”) in view of Anthony (US. Patent 7,439,570).
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`Applicant gratefully acknowledges the allowability of Claims 5-9 and 21-23 as
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`being dependent upon a rejected base claim, but allowable if rewritten in independent
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`form including all of the elements of the base claim and any intervening claims.
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`Applicant has amended Claims 1 and 6 to put the claims in a condition for
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`allowance.
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`In particular, Applicant has amended Claim 1 to include the elements of
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`Claim 5. Applicant has also amended Claims 9 to 21 to now depend from Claim 1.
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`Applicant has amended Claim 6 to include the elements of Claims 1 and 5. Applicant
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`respectfully submits that Claims 1- 4, 6-9 and 11-13 are now allowable.
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`In response to the rejection of Claims 19-20, Applicant has amended
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`independent Claim 19 to distinguish over the combination of references.
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`In particular,
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`Applicant has amended Claim 19 to include “a plurality of contacts formed between the
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`shield plate and the second plate.” Applicant has further amended Claim 19 to
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`indicate that “the shield plate has a gap through which an electrical contact to the first
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`plate extends,” and that “the shield plate, the plurality of contacts, and the second
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`plate provide electrical shielding for the first plate.”
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`Support for the amendment to Claim 19 may be found, for example, in Figs. 48,
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`and paragraphs [0050]-[0054]. No new matter has been added by the amendments.
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`Applicant respectfully submits that the claims as amended clearly distinguish
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`over the combination of Stribley in view of Anthony. Stribley teaches a compact, high
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`yield integrated circuit package.
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`In particular, in order to reduce the area of an IC
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`having capacitors, capacitance per unit area is maximized using a combined layer
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`capacitor. However, problems are often encountered during the fabrication process,
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`where excess charge may destroy a dielectric layer positioned between capacitor
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`plates.
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`In order to overcome these problems, Stribley teaches the use of first and
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`PATENT
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`Conf. No.: 3744
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`second conductive plates, with an “overlapped region” of the second conductive plate
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`that extends beyond the first conductive plate, such as overlapped region 10 shown in
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`Fig. 1 of Stribley cited in the Office Action. The capacitor is arranged so that the
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`electrical breakdown voltage between the overlap portion and the diffused plate 10 is
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`lower than the electrical breakdown voltage between the first and second conductive
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`plates.
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`(Stribley, col. 3, lines 24-30). Accordingly, the arrangement of Stribley uses
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`the doped region of the substrate as a plate (i.e. the minus plate) of the capacitor.
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`In contrast, Anthony teaches away from the use of a substrate as a capacitor
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`plate. Rather, Anthony teaches the use of additional metal layers to shield the
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`capacitor terminal 21.
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`In addition to the self shielding arrangement of Fig. 2 of
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`Anthony which shields terminal 22, an additional shield 37 is provided in the
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`embodiment of Figs. 3 and 4 to shield the capacitor terminal 21. While the
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`embodiment of Fig. 4 uses the diffused layer 46 as a portion of the shield for the
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`capacitor terminal 21, the diffused region 46 does not function as a capacitor plate.
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`More importantly, Stribley expressly teaches away from the use of additional
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`elements to provide shielding. That is, the goal of Stribley is to produce compact
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`circuit capacitors.
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`(Stribley, col. 1, lines 29-43). Adding a shield of Anthony to Stribley
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`would require that additional layers be added. Such additional layers are not desirable
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`in Stribley. Further, the substrate of Anthony, such as in Fig. 4, is used as an isolation
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`layer, and not as a capacitor plate as shown in Stribley. Accordingly, Applicant
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`respectfully submits that Anthony could not be properly combined with Stribley.
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`While the references are not properly combined, any combination would not
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`lead to the claims. Stribley teaches the use of the substrate as a capacitor plate, while
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`Anthony teaches that the substrate should be used separate from the capacitor as an
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`isolation layer. Neither reference teaches a plurality of contacts formed between the
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`shield plate and a second plate of the capacitor as claimed. Further, neither reference
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`teaches that a shield plate has a gap through which an electrical contact to a first plate
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`extends, or that a shield plate, a plurality of contacts, and a second plate provide
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`electrical shielding for a first plate as claimed in Claim 19. Applicant respectfully
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`submits that Claim 19 clearly distinguishes over the references, and thus requests
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`reconsideration of the rejection of Claims 19-20 in view of the amendments.
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`X-3004 US
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`12/276,289
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`PATENT
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`Conf. No.: 3744
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`W
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`Claims 19-20 as amended clearly distinguish over the combination of Stibley
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`and Anthony, and all claims should now be in a condition for allowance.
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`If the Examiner has any questions or believes a telephone conference would
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`resolve any outstanding issues, the Examiner is cordially invited to telephone the
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`undersigned at (408) 879-4682.
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`Respectfully submitted,
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`/Thomas George, 45,740/
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`Thomas George
`Attorney for Applicant
`Reg. No. 45,740
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`/ hereby certify that this correspondence is being filed via EFS-Web with
`the United States Patent & Trademark Office on January 201 2011.
`/Katherine Stofer/
`Katherine Stofer
`
`