X—3004 US
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`PATENT
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`SHIELDING FOR INTEGRATED CAPACITORS
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`RELATED APPLICATIONS
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`[0001]
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`This patent application is being concurrently filed with commonly owned US.
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`Patent Application entitled INTEGRATED CAPACITOR WITH TARTAN CROSS
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`SECTION by Patrick J. Quinn; and with commonly owned US. Patent Application
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`entitled INTEGRATED CAPACITOR WITH INTERLINKED LATERAL FINS by Patrick
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`J. Quinn; and with commonly owned US. Patent Application entitled INTEGRATED
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`CAPACITOR WITH CABLED PLATES by Patrick J. Quinn; and with commonly owned
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`US. Patent Application entitled INTEGRATED CAPACITOR WITH ARRAY OF
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`CROSSES by Patrick J. Quinn; and with commonly owned US. Patent Application
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`entitled INTEGRATED CAPACITOR WITH ALTERNATING LAYERED SEGMENTS by
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`Jan L. de Jong et al., the disclosures of which are each hereby incorporated by
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`reference in their entireties for all purposes.
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`FIELD OF THE INVENTION
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`[0002]
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`The present invention relates to capacitors formed in integrated circuits
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`(“le”) commonly referred to as integrated capacitors.
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`BACKGROUND
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`[0003] Methods of fabricating le typically include a front-end sequence of
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`processing, in which various electrical devices such as transistors are formed in a
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`semiconductor substrate, and a back-end sequence of processing, generally including
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`forming alternating layers of dielectric material and patterned conductive material
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`(typically metal) with conductive vias or other techniques being used to interconnect
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`the metal layers to form a three-dimensional wiring structure that connects electrical
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`devices to other electrical devices and to terminals of the IC.
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`[0004]
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`Capacitors are used in IC systems for a variety of purposes.
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`In many
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`instances, it is desirable to incorporate (integrate) a capacitor in the IC chip. A simple
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`approach is to form two conductive plates with an intervening dielectric; however, this
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`consumes a relatively large area for the capacitance obtained. One technique for
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`increasing the capacitance of a given area is to use multiple conductive plates, each
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`1
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`IVM 1003
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`IPR of US. Pat. No. 7,994,609
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`PATENT
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`conductive plate separated from the proximate p|ate(s) by dielectric. Further
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`techniques use conducting strips, also called conductive lines, conductive fingers, or
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`conductive traces, that are alternately connected to the first and second capacitor
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`terminals (nodes). Sidewall coupling between the conductive strips provides
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`capacitance. Layers of conducting strips, either offset or arranged in vertical
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`congruency, can be added to further increase the capacitance of an integrated
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`capacitor structure.
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`[0005]
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`One capacitor has a number of conductive strips in successive layers
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`connected to the first node alternating with an equal number of conductive strips
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`connected to the second node of the integrated capacitor. The conductive strips are
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`offset a half cell on successive layers, so that a conductive strip connected to the first
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`node has conductive strips connected to the second node above and on both sides of
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`it. Providing an equal number of conductive strips in a layer for each node balances
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`the coupling of each node to the substrate, which is desirable in some applications, but
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`undesirable in others, such as switching applications where it is desirable to have less
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`coupling at one node.
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`In order to reduce coupling to the substrate, a thick layer of
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`silicon dioxide is used between the substrate and the first layer of conductive strips.
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`This may be difficult to integrate in a standard CMOS fabrication sequence and might
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`require additional steps to be added to the standard process flow. The overlapping
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`parallel conductive strips are connected at their ends using buss strips that consume
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`additional surface area.
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`[0006]
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`Another approach to providing an integrated capacitor is to have conductive
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`strips in a layer connected to alternate nodes of the capacitor with overlapping
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`conductive strips connected to the same node. This forms essentially a curtain of
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`conductive strips and interconnecting vias connected to the first node of the capacitor
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`with adjacent curtains of conductive strips and interconnecting vias connected to the
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`second node. Overlapping conductive strips connected to the same node avoids the
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`lost surface area associated with buss strips; however, inter-layer capacitance is
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`reduced because the upper strip is connected to the same node as the lower strip.
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`This effect is somewhat obviated because, as critical dimensions shrink, inter-strip
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`capacitance becomes more dominant than inter-layer capacitance.
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`In other words, the
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`dielectric layer separation between successive metal layers becomes increasingly
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`greater than the dielectric separation between conductive strips with decreasing critical
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`dimension.
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`[0007]
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`Conventional integrated capacitors are often susceptible to electronic noise,
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`which can affect the performance of the IC.
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`In some applications, such as a filter
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`capacitor application where one of the capacitor nodes (typically the bottom node) is
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`connected to ground or to a power supply voltage, some degree of noise is often
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`tolerable. However, in other applications, such as when the capacitor is used in a
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`signal path (i.e., as a coupling capacitor or a switched capacitor), noise coupling can
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`seriously degrade the performance of the circuit. Noise coupled onto a capacitor are
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`particularly problematic when very low analog voltages are coupled through the
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`capacitor, especially in a system on a chip, which often produce more electrical noise
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`than other types of ICS, such as a memory chip. Thus, integrated capacitors providing
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`better noise immunity are desired for used low-noise applications on an IC.
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`SUMMARY
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`[0008]
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`A capacitor in an integrated circuit (“IC”) includes a core capacitor portion
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`having a first plurality of conductive elements electrically connected to and forming
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`part of a first node of the capacitor formed in a first conductive layer of the IC and a
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`second plurality of conductive elements electrically connected to and forming part of a
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`second node of the capacitor formed in the first conductive layer. The first plurality of
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`conductive elements alternates with the second plurality of conductive elements in the
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`first conductive layer. A third plurality of conductive elements electrically connected to
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`and forming part of the first node is formed in a second conductive layer adjacent to
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`the first conductive layer, at least portions of some of the second plurality of
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`conductive elements overlying and vertically coupling to at least portions of some of
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`the third plurality of conductive elements. The capacitor also includes a shield
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`capacitor portion having a fourth plurality of conductive elements formed in at least the
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`first conductive layer of the IC, the second conductive layer of the IC, a third
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`conductive layer of the IC, and a fourth conductive layer. The first and second
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`conductive layers are between the third and fourth conductive layers. The shield
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`capacitor portion is electrically connected to and forms part of the second node of the
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`capacitor and surrounds the first and third pluralities of conductive elements.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`[0009]
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`Accompanying drawing(s) show exemplary embodiment(s) in accordance
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`with one or more aspects of the invention; however, the accompanying drawing(s)
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`should not be taken to limit the invention to the embodiment(s) shown, but are for
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`explanation and understanding only.
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`[0010]
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`FIG. 1
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`is a circuit diagram of a circuit using capacitors according to
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`embodiments of the invention.
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`[0011]
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`FIG. 2A is an isometric view of a portion of a shielded integrated capacitor
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`suitable for use in embodiments of the present invention.
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`[0012]
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`FIG. 2B is a side view of a integrated capacitor 220 in accordance with FIG.
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`2A.
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`[0013]
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`FIG. 2C is a side view of the integrated capacitor according to FIG. 2A with
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`a ground shield according to an embodiment.
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`[0014]
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`FIG. 2D is a side view of the integrated capacitor according to FIG. 2A with
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`an alternative ground shield according to another embodiment.
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`[0015]
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`FIG. 3A is a side view of an integrated capacitor with a bottom node shield
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`according to an alternative embodiment.
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`[0016]
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`FIG. 3B is a partial cutaway plan view of the M5 and M4 layers showing a
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`portion of the ground plate and underlying bottom node shield plate of FIG. 3A.
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`[0017]
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`FIG. 4A is side view of an integrated capacitor with a bottom node shield
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`according to yet another alternative embodiment.
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`[0018]
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`FIG. 4B is a cross section of a shielded integrated thin-dielectric capacitor in
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`an IC according to another embodiment.
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`[0019]
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`FIG. 5 is a plan view of an FPGA incorporating an integrated capacitor
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`according to an embodiment.
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`DETAILED DESCRIPTION
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`[0020]
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`FIG. 1
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`is a circuit diagram of a circuit 100 using capacitors 102, 104
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`according to embodiments of the invention. The top node 108 of capacitor 104 is
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`switchable to be connected to or disconnected from a high-impedance input 114 of
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`amplifier 116. The top node 106 of the feedback capacitor 102 is also connected to
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`the high-impedance input 114 of the amplifier 116 while the bottom node 110 is
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`connected to output 118 of the amplifier 116. The feedback capacitor 102 is
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`switchably shorted by closing switch 119. The coupling capacitor 104 has a top node
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`108 shielded by a bottom node shield 120 that essentially surrounds the top node 108
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`with conductive structures electrically connected to the bottom node and reduces
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`parasitic capacitive coupling of the top node 108 to other nodes of the circuit 100.
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`Connection to the top node 108 is made through a gap in the bottom node shield 120.
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`Although the bottom node shield is shown as being contiguous, in some embodiments
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`the bottom node shield is made up of several conductive elements, such as metal
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`filaments, metal vias, and polysilicon or silicide plates or strips, to form a conductive
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`cage around the top node, shielding the top node from electronic noise and from
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`coupling to other nodes of the IC.
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`In some embodiments, the bottom node shield
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`contributes to the overall capacitance of the integrated capacitor by coupling to the top
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`node. Note that a capacitor is generally thought of as a two terminal device, and the
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`“top” and “bottom” nodes as described herein generally correspond to these two
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`terminals of the capacitor. Thus, the structures described below may be thought of as
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`connecting (e.g., electrically) to one or the other node, or forming portions or parts of a
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`node. A node is not separate from the capacitive structures connected to it, but those
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`structures may form portions of a node.
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`[0021]
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`The feedback capacitor 102 has a top node 110 shielded by a bottom node
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`shield 122, and by an optional reference shield 124. The reference shield 124 is
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`connected to a relatively stable reference voltage present in the IC, such as analog
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`ground, digital ground, or VDD. The reference shield 124 essentially surrounds the
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`bottom node shield 120 and shields the bottom node from substantially coupling to
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`more than one voltage reference (e.g., the bottom node couples to VDD or ground, but
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`not both).
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`In other embodiments, a reference shield partially surrounds a bottom node
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`shield. The reference shield has a gap allowing electrical contact to be made to the
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`bottom node, as described above.
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`[0022]
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`The terms “top” node and “bottom” node do not necessarily relate to the
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`physical orientation of the nodes relative to the IC or other structure, but are used as
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`terms of convenience.
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`In some circuit applications, the top node of a capacitor
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`indicates the node that is connected to a high-impedance or high-gain port of an
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`amplifier or other device.
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`In a system-on-chip (“SoC”), the accuracy on an analog-to-
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`digital converter (“ADC”) is dependent on the ratio of the parasitic capacitance at the
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`top node (Ctop) to all other nodes except the bottom node and the capacitance (Csig)
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`that is the useful floating signal capacitance between both nodes.
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`It is desirable to
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`shield the top plate from ground currents or voltage supply fluctuations so that Ctop
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`remains low. Using the bottom node to essentially surround the top node isolates the
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`top node from coupling with other nodes in the circuit by essentially forming a portion
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`of Faraday shell around the top node, and in some embodiments, distancing the top
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`node from other conductive elements in the IC.
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`It is understood by those of skill in the
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`art that electrical connection to the top node is made through the bottom node shield,
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`and therefore the bottom node shield does not completely surround the top node.
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`[0023]
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`In some embodiments, some sides of the top node are left unshielded. For
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`example, an end of the top node that is physically distant from other nodes might be
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`left unshielded.
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`In other embodiments, integrated capacitors are used as design cells,
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`and adjacent integrated capacitors are connected in parallel to obtain a higher total
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`capacitance.
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`In some embodiments, the portions of the bottom node shield of
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`adjacent commonly-connected integrated capacitors are omitted, allowing higher
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`packing density.
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`[0024]
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`Complex le, such as programmable logic devices, often have several
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`patterned metal layers separated by layers of dielectric material formed over a
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`semiconductor substrate that are used for wiring connections and other functions
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`commonly called the “backend” of the IC. Some embodiments of the invention are
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`adaptable to existing CMOS process sequences by using masks that form the desired
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`patterns in the appropriate metal layers and vias through the inter-metal dielectric
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`(“IMD”) layers or inter-layer dielectric (“ILD”) in the backend of the IC. The vias are
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`formed using any of several known techniques, such as contact plug, damascene, or
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`dual damascene techniques. Similarly, the conductive strips are formed using any of
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`several known techniques, such as thin-film metal etch, thin-film metal lift-off,
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`damascene, and dual damascene techniques.
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`In some embodiments, one of the
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`conductive layers is a polysilicon or silicide layer.
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`In a further embodiment, a
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`conductive well in the semiconductor substrate forms a portion of a capacitor plate or a
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`shield.
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`[0025]
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`FIG. 2A is an isometric view of a portion 200 of an integrated capacitor
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`according to an embodiment of the present invention. A bottom plate conductive
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`matrix 202 includes a first bottom plate layer B made up of a first plurality of
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`conductive strips 204, 206 and a second bottom plate layer 8' made up of a sheet of
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`polysilicon or silicide, in what is commonly called a “poly” layer, all connected to the
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`bottom node of the integrated capacitor. The bottom node in this embodiment is the
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`capacitor node that is less susceptible to electronic noise than the top node when the
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`capacitor is used in a particular circuit application. A top plate conductive matrix 212 is
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`covered by the first bottom plate layer B and underlain by the second bottom plate
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`layer B' , which forms a partial Faraday shield around the top node.
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`[0026]
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`The first bottom plate layer is made up of strips, rather than a continuous
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`sheet, because of design layout rules familiar to those of skill in the art of IC
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`fabrication. Generally, each metal layer has minimum and maximum metal line widths
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`and minimum separations. Polysilicon and silicide layers typically have different
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`design and process rules than patterned metal layers, which allows forming the bottom
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`plate layer as a contiguous sheet of poly when the poly layer is used. Similarly, large
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`conductive areas can be formed in the semiconductor substrate (e.g., an N-well or a
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`P-well) to form a continuous conductive sheet.
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`In an alternative embodiment, the
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`second bottom plate layer is formed in a conductive well of the substrate. The
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`conductive well is separated from the poly layer by a relatively thin dielectric layer,
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`providing good electrical performance even though the N-well is generally less
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`conductive than a metal layer or poly layer. Using a conductive well to form part ofa
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`shield is further desirable because a moat can be formed around the portion of the
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`substrate in which the N-well or P-well is formed, which further isolates the N- or P-well
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`from stray currents. Use of a conductive well in a shield is also desirable because the
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`well is surrounded in a fairly symmetrical fashion by metal, leading to symmetrical
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`current flow through the well portion of the shield.
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`[0027]
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`The conductive strips 204, 206 in the top plate layer B are electrically
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`connected through vias (not shown, see, e.g., via 214) to transverse (i.e., generally
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`orthogonal) conductive strips (e.g., B4) in the lower layer so that interconnection
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`between conductive strips 204, 206 in the metal layer of the first bottom plate layer B
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`is not necessary. Alternatively, conductive cross members (cross-connects between
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`strips in the metal layer) are optionally included in the first bottom plate layer to
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`connect conductive strips in the layer, which improves shielding.
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`[0028]
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`Similarly, a top plate layer T is made up of a plurality of conductive strips
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`216, 218 connected to the top node of the integrated capacitor. The conductive strips
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`in the top plate layer T are transverse to conductive strips T1, T2, T3, T4, T5 above
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`the top plate layer T and transverse to conductive strips T6, T7, T8, T9, T10 below the
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`top plate layer, and conductive strips in the top plate layer T are electrically connected
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`to each other through vias and transverse conductive strips above and below the top
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`plate layer T.
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`In some embodiments, the conductive strips (e.g. T1, B1) are made
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`from a minimum-width metal line and are commonly referred to as “conductive
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`filaments” or “metal filaments” and provide high line densities and high lateral
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`capacitance. Lateral capacitance between conductive strips in the plate layers does
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`not contribute to the specific capacitance of the integrated capacitor because the metal
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`strips are connected to the same node, and conductive strips in the plate layers are
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`often wider than minimum metal line width.
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`[0029]
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`The plate layers B, T, B’ do not have alternating conductive strips, but
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`rather all the conductive strips in these layers are connected to either the top node or
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`the bottom node of the integrated capacitor. The configuration of a capacitor
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`according to FIG. 2A provides bottom plates B, B’ that shield the conductive elements
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`of the top plate because they are embedded between the first and second bottom
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`plate layers in the IC stack. Conductive curtains (see, FIG. 2B, ref. nums. 236, 238)
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`on the right and left sides of the top plate conductive matrix are formed of vias and
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`metal layers between the first bottom plate B and the second bottom plate B' and
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`extend along a third direction (e.g., the Z direction as illustrated in FIG. 2A) to form
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`essentially a conductive plane (in the plane defined by the Y and Z axes). The bottom
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`plate conductive matrix of the integrated capacitor loosely surrounds the top plate
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`conductive matrix of the integrated capacitor so that the top plate couples with the
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`bottom plate on the top, bottom, right side, and left side.
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`In a further embodiment,
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`additional conductive curtains are optionally added in the plane defined by the X and Z
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`axes to cover (shield) the ends of the top node conductive elements in these planes.
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`[0030]
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`FIG. 2B is a side view of a integrated capacitor 220 in accordance with FIG.
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`2A. The side view is taken along the direction of the arrow A in FIG. 2A. The
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`integrated capacitor has a core capacitor portion 201 and a shield capacitor portion
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`203. The shield capacitor portion 203 is basically a bottom node shield that has a first
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`shield layer B formed in the fifth metal layer M5 of a backend stack 222 of an IC that
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`includes metal layers M1, M2, M3, M4, M5 and intervening dielectric layers that have
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`vias (e.g., via 226) extending through the dielectric layers to connect metal layers.
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`The dielectric layers are not shown with hatching for clarity of illustration, as they are
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`well understood by those of skill in the art of IC processing.
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`[0031]
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`Integrated capacitors according to alternative embodiments include
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`additional metal layers. The integrated capacitor includes an optional reference shield,
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`which in this embodiment is a reference shield connected to VDD. The reference
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`shield includes a shield plate 224 made up of a conductive well (Nwell), formed in the
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`semiconductor substrate 226 of the IC, a top shield plate 225 formed in the M5 metal
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`layer, and conductive curtains 240, 242.
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`[0032]
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`The shield capacitor portion 203 forms a conductive sheath around the core
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`capacitor portion 201, which has interleaved top and bottom node conductive filaments
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`that provide high specific lateral capacitance in the M1 and M3 metal layers, and
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`vertical capacitance between the bottom node elements in M1 and M3 and the top
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`node elements in M2, which is adjacent to both M1 and M3. The shield capacitor
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`portion adds additional capacitance by coupling to the top node conductive elements in
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`M1, M2, and M3.
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`In a typical embodiment, each layer of interleaved filaments will
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`have hundreds of filaments and the lateral coupling between the filaments is a
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`significant portion of the total capacitance of the integrated capacitor.
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`[0033]
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`The second bottom plate layer B'
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`is formed in the poly layer of the IC.
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`In an
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`alternative embodiment, the second bottom plate layer is formed as strips in a metal
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`layer, such as M1 or M2, in a backend stack that has additional metal layers. Utilizing
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`the poly layer for the second bottom plate layer allows a shielded integrated capacitor
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`(without the optional VDD shield) to be formed in a four-metal-layer IC.
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`In an alternative
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`embodiment, a conductive well formed in the semiconductor substrate is used as the
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`second bottom plate layer, allowing an embodiment to be fabricated in three metal
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`layers of an IC, or allowing additional metal layers for increasing the specific
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`capacitance of a capacitor of a given area. The dielectric layer above the substrate
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`and poly layer (not separately shown) is commonly called an inter-layer dielectric
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`(“lLD”), and the conductive element 228 connecting the poly layer to the N+ conductive
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`area 230 of the substrate is commonly called a contact, as opposed to a via. A gate
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`dielectric layer (not separately shown) between the poly and the N-well is typically
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`much thinner than the lLD layer.
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`[0034]
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`FIG. 2B is not drawn to scale. Generally, the thicknesses of the IMD and
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`lLD layers are greater than the spacing between the interleaved conductive strips
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`(e.g., T1 and B1) in the interleaved layers M3 and M1.
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`In an exemplary embodiment,
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`the lLD layer is about 300 nm thick silicon oxide, while the dielectric layer between the
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`poly layer and M1 layer is about 100 nm thick and the higher layers are about 250 nm.
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`The minimum separation between metal traces in a layer is typically much smaller,
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`thus the sidewall capacitance between T1 and B1, for example, is greater than the
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`vertical capacitance between T1 and B. Similarly, the sidewall capacitance between
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`the ends of the top plate conductive matrix (e.g., T1, T4, T5, T8, and both ends of T)
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`and the conductive curtains 236, 238; and the end vias 250, 252 and curtain vias 254,
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`256 (and corresponding vias on other sides) provide additional capacitance that
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`compensates for the lack of interleaving in the M4, M2 and poly layers. As node
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`technology shrinks and the minimum dimension between conductive strips in the
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`interleaved layers decreases, the relative contribution of sidewall capacitance between
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`interleaved metal strips and vias to the overall capacitance increases.
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`[0035]
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`The optional reference shield includes a first shield layer 225 and the shield
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`plate 224 formed in the N-well that are connected through a series of vias, metal, poly,
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`and contacts. The vias, metal, poly, and contacts form a first shield curtain and a
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`second shield curtain that are basically the right and left vertical portions of the
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`reference shield.
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`In a further embodiment, third and fourth conductive curtains of the
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`bottom plate conductive matrix enclose the as-viewed front and back planes of the
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`bottom node shield and core capacitor. These features are not shown for purposes of
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`clarity of illustration, as they would be understood by one of ordinary skill in the art in
`
`light of the conductive and shield curtains illustrated in side view.
`
`[0036]
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`The reference shield is connected to a stable voltage reference, such as VDD
`
`or ground, to reduce coupling of the bottom node to more than one voltage node. For
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`example, the bottom node matrix couples essentially only to the top node and to VDD.
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`Negligible coupling of the other nodes of the IC to the bottom node occurs. Similarly, if
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`the shield were connected to ground instead of VDD, the bottom node would only
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`couple to the top node and ground.
`
`[0037]
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`It is generally undesirable for the bottom node to couple to VDD and ground
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`simultaneously because the bottom node would then act as a bridge between ground
`
`and VDD, and could couple undesirable switching currents between the two nodes, for
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`example. However, in some embodiments, limited coupling to both VDD and ground is
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`acceptable, particularly if coupling of the bottom node shield to a reference shield is
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`limited to conductive elements connected to an isolated portion of the substrate, or if
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`the ground node is an analog ground node that is reasonably well isolated from a
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`digital ground node.
`
`[0038]
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`A gap or similar feature (not shown, see FIG. 1) is provided in the shield to
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`allow circuit connection to the bottom node conductive matrix, and a second gap or
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`similarfeature is provided in the shield, and a third gap or similarfeature is provided in
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`the bottom plate conductive matrix to allow connection to the top node conductive
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`matrix.
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`In embodiments omitting front and back conductive curtains or shield curtains,
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`electrical connections to the conductive matrices can be brought out in the directions
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`orthogonal to the plane of the illustration sheet, for example. Bottom node shielding
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`can also be brought out along the top node connection to a switch, for example, to
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`further shield the top node.
`
`[0039]
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`FIG. 2C is a side view of the integrated capacitor 250 with a ground shield
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`256 (represented as a dashed line) according to an embodiment. The integrated
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`capacitor 250 includes a core capacitor portion 252 that includes conductive elements
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`(e.g., filaments) within a metal layer (e.g., M1, M3) alternatively connected to opposite
`
`nodes of the capacitor and a shield capacitor portion (bottom node shield) 254. For
`
`example, T1, T2, T3, and T4, alternate with B1, B2, and B3 in M3 and T5, T6, T7, and
`
`T8 alternate with B5, B6, and B7 in M1. Alternating conductive elements in the core
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`capacitor portion 252 provides significant lateral capacitance, which improves as
`
`fabrication dimensions are reduced and the conductive elements become closer
`
`together. Similar lateral capacitance is obtained between top node elements T1, T4,
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`T5, T8, and both ends of T and corresponding bottom node elements that form the
`
`reference shield. The shield capacitor portion 254 surrounds the core capacitor 252 to
`
`form a conductive cage that reduces coupling of the top node to other nodes of the IC.
`
`[0040]
`
`The integrated capacitor 250 produces good specific capacitance, which is
`
`essentially CSIG per unit area of silicon, from both the core capacitor portion 252 and
`
`also from coupling between top node elements in the core capacitor portion 252 and
`
`the shield capacitor portion 254.
`
`[0041]
`
`The integrated capacitor includes an optional ground shield 256 that partially
`
`surrounds the bottom node shield 254, basically forming a Faraday cup. The ground
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`shield reduces electronic noise generated in the IC that might otherwise couple to the
`
`bottom node or top node of the integrated capacitor 250.
`
`In a particular embodiment,
`
`a reference shield plate 257 is formed in the M5 layer, providing a low-resistance
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`ground path for connecting the ground shield 256 to one or more ground terminals of
`
`the IC.
`
`In a particular embodiment, the ground shield 256 is connected to the analog
`
`ground of the IC, rather than the digital ground to avoid high switching currents and
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`electrical noise that can be present on the digital ground. High switching currents on a
`
`digital ground node of an IC are particularly problematic for FPGAs, where entire
`
`blocks of the circuit are often switched on and off.
`
`[0042]
`
`A VDD shield cup 258 (represented as a dashed line) includes a shield plate
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`260 formed in an N-well in the semiconductor substrate 226. VDD bias is brought to
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`the N-well VDD shield through conductive curtains 262, 264 or alternatively through
`
`conductive pillars. Providing the VDD shield cup 258 further shields the top node and
`
`the bottom node of the integrated capacitor from electrical noise.
`
`In some le, the M5
`
`layer might only be a ground shield with no VDD interconnect allowed at M5.
`
`12
`
`

`

`X—3004 US
`
`PATENT
`
`[0043]
`
`FIG. 2D is a view of an integrated capacitor 270 with a ground shield
`
`according to another embodiment. The capacitor 270 includes a core capacitor
`
`portion 252 and a bottom node shield forming a shield capacitor portion 254 as
`
`described above in reference to Fle. 2A-2C. The shield capacitor portion 254
`
`surrounds the core capacitor portion 252 and isolates the core capacitor portion from
`
`electronic noise similarly to how an outer conductive sheath of a cable isolates the
`
`inner wires from electronic noise.
`
`In a further embodiment, the bottom node shield
`
`extends over the ends of the capacitor core not shown in this view (i.e., the ends that
`
`are in the plane of the view).
`
`In a particular embodiment, the ground shield is
`
`connected to analog ground, rather than to digital ground.
`
`In a particular
`
`embodiment, the portion of the substrate 226 in which the N-well 282 is formed and to
`
`which the conductive curtains 274, 276 of the ground shield are connected by P+
`
`regions 278, 280, are optionally formed in a moat (not shown) that isolates the moated
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`portion of the substrate from stray currents in other portions of the substrate. The
`
`ground shield and VDD shield forms a shield structure similar to double guard ring
`
`shielding, and are particularly desirable to shield the top node of the integrated
`
`capacitor in electrically noisy environments.
`
`In an alternative embodiment, the VDD
`
`shield is omitted.
`
`[0044]
`
`FIG. 3A is a side view of an integrated capacitor 300 according to an
`
`alternative embodiment. A core capacitor portion 304 includes conductive elements
`
`(e.g., filaments) within a metal layer (e.g., M1, M2, M3) alternatively connected
`
`opposite nodes of the capacitor. For example, T1, T2, T3, and T4 alternate with B1,
`
`B2, and B3 in M3, T5, T6, and T7 alternate with B4, B5, B6, and B7 in M2, and T8, T9,
`
`T10, T11 alternate with B8, B9, and B10 in M1. Top node elements T1, T4, T8, and
`
`T11 also laterally couple with bottom node shield elements. Similarly, B4 vertically
`
`couples with T1 and T8, providing vertical capacitance that increases the specific
`
`capacflance.
`
`[0045]
`
`Alternating conductive elements in the core capacitor portion 304 provides
`
`lateral capacitance, which improves as fabrication dimensions are reduced and the
`
`conductive elements become closer together. While it would be generally desirable
`
`that each end element in a metal layer laterally couple with a conductive filament
`
`13
`
`

`

`X—3004 US
`
`PATENT
`
`electrically connected to the opposite node of the integrated capacitor, in an actual
`
`device there may be hundreds of parallel conductive filaments in each metal layer, and
`
`the few row ends that are not opposite polarity may have relatively little detrimental
`
`effect.
`
`[0046]
`
`A ground shield 306 includes ground shield conductive curtains 308, 310,
`
`that essentially surround the core capacitor portion 304 and shield capacitor portion
`
`302 of the integrated capacitor. The ground shield conductive curtains 308, 310,
`
`include poly elements 312, 314 and contacts 316, 318 to P+ regions 320, 322 in the
`
`substrate 226.
`
`In an exemplary application, the ground plate 256 in the M5 layer is
`
`connected