throbber
IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`In re inter partes review of:
`
`U.S. Patent 7,994,609 to Quinn
`
`Atty. Docket: 3059.701IPRO
`
`Filed: Herewith
`
`For: SHIELDING FOR
`
`INTEGRATED CAPACITORS
`
`Declaration of Morgan Johnson
`in Support of Petition for Inter Partes Review of U.S. Patent No. 7,994,609
`
`1, Morgan Johnson, declare as follows:
`
`1.
`
`I have been retained by Sterne, Kessler, Goldstein, and Fox PLLC on
`
`behalf of
`
`Intellectual Ventures Management, LLC (“Intellectual Ventures
`
`Management”)
`
`for
`
`the above-captioned inter parres review proceeding.
`
`I
`
`understand that this proceeding iEVOIV€S U.S. Patent No. 7,994,609 (“the ‘609
`
`Patent”) entitled “Shielding for Integrated Capacitors,” and that the ‘609 Patent is
`
`currently assigned to Xilinx, Inc.
`
`2.
`
`I have reviewed and am familiar with the specification of the ‘609
`
`Patent filed on November 21, 2008 and issued on August 9, 2011. A copy of the
`
`‘609 Patent is provided as IVM 1001.
`
`I will cite to the specification using the
`
`following format: (‘609 Patent, 1:1-10). This example citation points to the ‘609
`
`patent specification at column 1, lines 1-10.
`
`IVM 1002
`
`IPR ofU.S. Pat. No. 7,994,609
`
`

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`- 2 -
`
`3.
`
`I have reviewed and am familiar with U.S. Patent No. 6,737,698 to
`
`Paul et al. (hereinafter “Paul”), U.S. Patent No. 7,439,570 to Anthony (hereinafter
`
`“Anthony”), U.S. Patent No. 7,286,071 to Hsueh et al. (hereinafter “Hsueh”), U.S.
`
`Patent No. 6,903,918 to Brennan (hereinafter “Brennan”), U.S. Patent No.
`
`7,238,981 to Marotta (hereinafter “Marotta”), and U.S. Patent Application
`
`Publication No. 2008/0128857 to Bi (hereinafter “Bi”).
`
`4.
`
`I am familiar with the technology at issue as of the November 21,
`
`2008 filing date of the ‘609 Patent.
`
`5.
`
`I have been asked to provide my technical review, analysis, insights,
`
`and opinions regarding the above-noted references that form the basis for the
`
`grounds of rejection set forth
`
`the Petition for Inter Partes Review of the ‘609
`
`Patent.
`
`I.
`
`Quaiifications
`
`6.
`
`I have more than 29 years of experience in the electronic interconnect
`
`and semiconductor industries.
`
`7.
`
`I earned a Bachelor of Science degree in Graphics from the University
`
`of Oregon. My studies included subjects in advanced mathematics related to
`
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`_ 3 -
`
`geodesic domes.
`
`I also attended The Art Center College of Design in Pasadena,
`
`California, where I majored in Industrial Design.
`
`8.
`
`I currently serve as Chief Scientist at Advanced Inquiry Systems, Inc.
`
`(AISI), a company that I founded in 2003. As Chief Scientist, my research focuses
`
`on tools and interfaces for full-wafer testing of products such as NAND and NOR
`
`flash, Dynamic Random Access Memory (DRAM), and certain logic devices. My
`
`research is additionally driven by the semiconductor industry’s demand for highly-
`
`parallel wafer testing of System-on—Chips (SOCS), such as processors for mobile
`
`devices. Through my research, AISI has implemented a device that achieves
`
`contact with up to 500,000 pads per wafer during tests. AISI was founded on my
`
`patented work in this area and benefits from over 30 issued patents.
`
`9.
`
`I co-founded Prototype Solutions Corporation in 1994, a company
`
`focused on using advanced interconnect and packaging technology to provide
`
`quick—turn prototypes and hardware emulation using programmable logic devices
`
`such as Field Programmable Gate Arrays (FPGAS). The technology is used to
`
`prototype highly—complex Central Processing Units (CPUs), Graphic Processing
`
`Units (GPUS), System on Chips (SOCS), and Application Specific Integrated
`
`Circuits (ASICS).
`
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`10.
`
`I founded LaserPath Corp. in 1983. Laserpath was a semiconductor
`
`company focused on laser programmable semiconductor gate arrays.
`
`The
`
`foundation of this technology was based on my inventions and patents. LaserPath
`
`achieved over 200 design wins in the first 9 months of sales—setting a record.
`
`LaserPath’s technology included Gate Arrays programmed with a laser in a
`
`ceramic package, tested, and delivered to customer in as little as two hours and
`
`more typically within 5 business days. This rapid Gate Array turnaround time and
`
`large number of design wins drastically shifted the ASIC business from a 12-week
`
`delivery to a new standard of 3- week delivery.
`
`11.
`
`From 1981 to 1982, I researched controlled impedance, instant turn-
`
`around circuit boards for the Cray 2 computer system. My research was funded by
`
`Cray Computer Corporation—Boulder, Colorado Team. This research was the
`
`genesis for my later-developed technology that evolved into LaserPath.
`
`12.
`
`In addition to my semiconductor industry experience, I am an inventor
`
`on 36 U.S. patents
`
`related to interconnects,
`
`high—speed connectors,
`
`and
`
`semiconductors.
`
`13. My Curriculum Vitae is attached as IVM 1012, which contains further
`
`details on my education, experience, publications, patents, and other qualifications
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`to render an expert opinion. My work on this case is being billed at a rate of
`
`$300.00 per hour, with reimbursement for actual expenses. My compensation is
`
`not contingent upon the outcome of this inter partes review.
`
`II. My Understanding of Qbviousness
`
`14.
`
`It is my understanding that a claimed invention is unpatentable if the
`
`differences between the invention and the prior art are such that the subject matter
`
`as a whole would have been obvious at the time the invention was made to a
`
`person having ordinary skill in the art to which the subject matter pertains.
`
`15.
`
`It is my understanding that "obviousness" is a question of law based
`
`on underlying factual issues including the content of the prior art and the level of
`
`skill
`
`in the art.
`
`I understand that for a single reference or a combination of
`
`references to anticipate the claimed invention, a person of ordinary skill in the art
`
`must have been able to arrive at the claims by altering or combining the applied
`
`references.
`
`16.
`
`I also understand that when considering the obviousness of a patent
`
`claim, one should consider whether a teaching, suggestion, or motivation to
`
`combine the references exists so as to avoid impermissibly applying hindsight
`
`when considereng the prior art.
`
`I understand this test should not be rigidly applied,
`
`but that the test can be important to avoid such hindsight.
`
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`III. Background of the ‘609 Patent
`
`17.
`
`The ‘609 Patent relates to shielding for integrated capacitors.
`
`In
`
`particular, the ‘609 Patent describes configurations of shielded capacitors formed
`
`in integrated circuits (“ICs”). (‘609 Patent, 1:25-27).
`
`18.
`
`The ‘609 Patent describes a capacitor in an IC having a core capacitor
`
`portion, which is comprised of multiple layers of conductive elements. (‘609
`
`Patent, 2:46-61). The ‘609 Patent discloses that the core capacitor portion is
`
`surrounded by a shield capacitor portion and a reference shield. (‘609 Patent, 2:61-
`
`3:3 and 6:25-31). The shield capacitor portion is also described as having multiple
`
`conductive elements formed in different metal
`
`layers. (‘609 Patent, 2:61-3:3).
`
`Additionally, the shield capacitor portion is described as being disposed between
`
`the reference shield and the core capacitor portion. (‘609 Patent, 6:25-31). Further,
`
`the ‘609 Patent discloses that the shielded capacitor described therein is intended to
`
`reduce electronic noise such that
`
`the electronic noise does not affect
`
`the
`
`performance of the IC. (‘609 Patent, 2:26-42).
`
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`IV.
`
`Level of Ordinary Skill in the Art
`
`19.
`
`Based on the technologies disclosed in the ‘609 patent, I believe one
`
`of ordinary skill in the art would have a B.S. degree in Electrical Engineering or
`
`equivalent training as well as 3-5 years of experience in the field of circuit design
`
`V.
`
`U.S. Patent No. 6,737,698 to Paul, et al
`
`20. U.S. Patent No. 6,737,698 to Paul, et al, titled “Shielded Capacitor
`
`Structure” (“Paul”) issued on May 18, 2004 which is over 4 years prior to the filing
`
`date of the ‘609 Patent. A copy of Paul is provided as IVM 1006.
`
`21.
`
`Paul seeks to address problems of prior art vertical finger capacitor
`
`structures. FIGS.
`
`1 and 2 of Paul (reproduced below) depict a prior art Vertical
`
`finger capacitor. Capacitor 100 “includes a first set of fingers connected to node A
`
`and a second set of fingers connected to node B.” (Paul, 1:38-40.) The fingers in
`
`each level of the capacitor “alternate between nodes A and B such that each A
`
`finger on the second and third levels of metal is surrounded by four neighboring B
`
`fingers and each B finger on the second and third levels of metal is surrounded by
`
`four neighboring A fingers.” (Paul, 1:40-45.)
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`xi
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`22.
`
`FIG. 2 of Paul illustrates the electric fields for the prior art capacitor
`
`structure of FIG. 1. As shown in FIG. 2, “significant electric fields are present
`
`around the capacitor fingers.” (Paul, 1:51-52.) Paul describes disadvantages with
`
`these prior art capacitor structures. For example, “the electric fields present around
`
`the capacitor can interact with materials present around the fingers and cause loss
`
`in these materials, which reduces the quality factor of the capacitor.” (Paul, 1:54-
`
`57.) Paul solves the problems of the prior art capacitor “by providing shielding to
`
`a capacitor structure formed in a semiconductor device.” (Paul, 2:37-39.)
`
`23.
`
`Paul describes various configurations of a capacitor “formed in an
`
`integrated circuit with one or more layers of conductive strips (i.e., capacitor
`
`fingers) connected to one of two nodes of the capacitor.” (Paul, 2:40-42.) The
`
`configurations disclosed in Paul include “[o]ne or more shields
`
`adjacent to the
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`layers of conductive strips and are also connected to one of the nodes.”
`
`(Paul,
`
`2:42-44.) The shields of Paul “confine the electric fields between the nodes
`
`between the limits of the shields.” (Paul, 2:44-46.)
`
`A. Paul Renders Independent Claim 1 Obvious.
`
`24.
`
`In my opinion, a person of ordinary skill in the art would find claim 1
`
`obvious in view of the teachings of Paul. Independent claim 1 of the ‘609 Patent is
`
`reproduced below (with labels added for ease of discussion).
`
`[P] A capacitor
`comprising:
`
`in an integrated circuit
`
`("IC")
`
`[A] a core capacitor portion having a first plurality of
`conductive
`elements
`electrically connected to and
`forming a first part of a first node of the capacitor formed
`in a first conductive layer of the IC and a second
`plurality of conductive elements electrically connected to
`and forming a first part of a second node of the capacitor
`formed in the first conductive layer, the first plurality of
`conductive elements alternating with the second plurality
`of conductive elements in the first conductive layer, and
`a third plurality of conductive elements electrically
`connected to and forming a second part of the first node
`formed in a second conductive layer adjacent to the first
`conductive layer, at least portions of some of the second
`plurality of conductive elements overlying and vertically
`coupling to at least portions of some of the third plurality
`of conductive elements;
`
`[B] a shield capacitor portion having a fourth plurality
`of conductive elements formed in at
`least
`the first
`
`conductive layer of the IC, the second conductive layer
`of the IC, a third conductive layer of the IC, and a fourth
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`conductive layer of the IC, the first conductive layer and
`the second conductive layer each being between the third
`conductive layer and the fourth conductive layer,
`the
`shield capacitor portion being electrically connected to
`and forming a second part of the second node of the
`capacitor
`and
`surrounding
`the
`first
`plurality of
`conductive elements and the third plurality of conductive
`elements; and
`
`[C] a reference shield electrically connected to a
`reference node of the IC other than the second node of
`the capacitor, the shield capacitor portion being disposed
`between the reference shield and the core capacitor
`
`portion.
`
`25.
`
`Paul discloses “a capacitor in an integrated circuit.” Specifically,
`
`Paul describes that in “a capacitor formed in an integrated circuit, one or more
`
`shields are disposed around layers of conductive strips to shield the capacitor.”
`
`(Paul, Abstract.)
`
`26.
`
`FIG. 4 of Paul (reproduced below) discloses a sectional view of a
`
`capacitor structure. The capacitor 400 is built “using four layers of metal.” (Paul,
`
`3:11-13.)
`
`In a first row of conductive strips (in METAL 2 layer), a “first set of
`
`conductive strips 404 is connected to node A of the capacitor” and “a second set of
`
`conductive strips 406 is connected to node B of the capacitor.” (Paul, 3:13-16.)
`
`The conductive strips 404 and 406 alternate.
`
`(Paul, 3:17-18.) A second row of
`
`conductive strips in METAL 3 also includes first and second alternating sets of
`
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`conductive strips 404 and 406 connected to nodes A and B of the capacitor. (Paul,
`
`-11-
`
`3:20-22.)
`
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`27.
`
`The capacitor 400 of Paul further includes “a first shield 408 formed
`
`in METAL 4 layer above the conductive strips” and a second shield 410 “formed
`
`in the METAL 1 layer below the conductive strips.” (Paul, 3:25-29.)
`
`28.
`
`Paul discloses additional configurations for a shielded capacitor. Paul
`
`explains that Various combinations of the configurations disclosed are possible.
`
`(Paul, 3:66-67.)
`
`29.
`
`FIG. 8 of Paul includes the structure of FIG. 4 as well as a side shield
`
`“formed by conductive strips 804 formed on the METAL 1, 2, and 3 layers and
`
`connected to node A.”
`
`(Paul, 4:26-30.) FIG. A.l annotates FIG. 8 of Paul to
`
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`_ 12 _
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`illustrate how the capacitor elements of Paul map to the limitations of claim 1[A].
`
`The rows of conductive strips in METAL 2 and METAL 3 of Paul form “a core
`
`capacitor portion” of the capacitor. Node B of the capacitor is the “first node of
`
`the capacitor” and Node A of the capacitor is the “second node ofthe capacitor.”
`
`30.
`
`The METAL 3 layer of Paul
`
`is equivalent
`
`to the recited “first
`
`conductive layer of the I .” A row of conductive strips is formed in the METAL
`
`3 layer of Paul. The set of conductive steips 806 in METAL 3 layer is equivalent
`
`to the “first plurality of conductive elements electrically connected to andforming
`
`a first part ofa first node of the capacitorformed in a first conductive layer of the
`
`IC” recited in independent claim 1. The set of conductive strips 804 in METAL 3
`
`layer is equivalent to the “second plurality of conductive elements electrically
`
`connected to and forming a first part of a second node of the capacitor formed in
`
`the first conductive layer” recited in independent claim 1. As illustrated in FIG. 8
`
`of Paul, the conductive strips 804 and 806 alternate. The row of conductive strips
`
`formed in METAL 3 layer has a set of conductive strips 804 connected to a first
`
`node of the capacitor (node B) and a set of conductive strips 806 connected to a
`
`second node of the capacitor (node A).
`
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`-13-
`
`second phmralitj;
`of elements
`
`first plurality
`of elements
`
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`
`FIGURE A.1
`
`31.
`The METAL 2 layer of Paul includes a second row of conductive
`strips. The second row includes a set of conductive strips 806 connected to node
`
`B. As illustrated in FIG. 8 of Paul, one or more of the conductive strips 804 in
`
`METAL 3 layer connected to node A overlay and vertically couple to conductive
`
`strips in the set of conductive strips 806 connected to node B in METAL 2 layer.
`
`The set of conductive strips 804 in METAL 3 layer is equivalent to the “third
`
`plurality of conductive elements” of claim 1. Thus, Paul discloses “a third
`
`plurality of conductive elements electrically connected to and forming a second
`
`part of the first node formed in a second conductive layer adjacent to the first
`
`conductive layer, at least portions of some of the second plurality of conductive
`
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`_ 14 _
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`elements overlying and vertically coupling to at least portions ofsome of the third
`
`plurality ofconductive elements” recited in independent claim 1
`
`32.
`
`The capacitor shields 408 and 410 of Paul “confine the electric fields
`
`from node A to node B
`
`within the limits of the [top and bottom] shields.” (Paul,
`
`3:34-36).
`
`Shields 408 and 410 are equivalent to shields 808 and 810 of the
`
`capacitor structure illustrated in FIG. 8. The capacitor 800 depicted in FIG. 8 of
`
`Paul has a side shield 812 in addition to the top shield 808 and the bottom shield
`
`810.
`
`(Paul, 4:26-28.) FIG. 8 of Paul depicts a side shield on one side of the core
`
`capacitor portion. However, as described in Paul, “a side shield could be formed
`
`on both sides of the capacitor 800.”
`
`(Paul, 4:33-35.) FIG. 8 of Paul has been
`
`edited as shown in FIG. A.2 below to illustrate the modification of capacitor 800 to
`
`include a side shield on both sides of the capacitor.
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`
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`_ 15 _
`
`33.
`
`Top shield 808 is formed in METAL 4 layer of the capacitor. The
`
`METAL 4 layer is equivalent to “third conductive layer of the I .”
`
`“The side
`
`shield 812 is formed by conductive strips 804 formed on the METAL 1, 2, and 3
`
`layers and connected to node A.”
`
`(Paul, 4:28-30.) The METAL 1
`
`layer is
`
`equivalent to the “fourth conductive layer of the IC.” METAL 3 layer (first
`
`conductive layer of the IC) and METAL 2 layer (second conductive layer of the
`
`1C) are between the METAL 4 layer (third conductive layer of the 1C) and the
`
`METAL 1 layer (fourth conductive layer ofthe IC).
`
`34.
`
`The top shield 808 in combination with the first and second side
`
`shields 812 are “a fourth plurality of conductive elements formed in at least the
`
`first conductive layer of the IC,
`
`the second conductive layer of the IC, a third
`
`conductive layer of the IC, and a fourth conductive layer of the IC,” The capacitor
`
`of FIG. 8 in Paul depicts the top shield 808 connected to Node A (the recited
`
`second node) and the bottom shield 810 connected to Node B (the recited first
`
`node).
`
`Paul discloses that the top and bottom shields 808 and 810 may be
`
`connected to the same node such as node B.
`
`(Paul, 4:56-60.) Therefore, Paul also
`
`discloses “shield capacitor portion being electrically connected to and forming a
`
`second part of the second node of the capacitor” as recited in l[B]. FIG. A.3
`
`below annotates edited FIG. A.2 above to illustrate how the elements of edited
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`FIG. 8 map to the shield capacitor portion limitation of claim 1[B]. As illustrated
`
`in FIG. A.3, the shield capacitor portion formed of top shield 808, side-shields 812
`
`and bottom shield 810 “surround[s] the first plurality of conductive elements and
`
`the thirdplurality ofconductive elements” of the core capacitor portion.
`
`shield capacitor
`
`
`
`"fourth pl'l11'E|.lit’_§'
`of Elements
`
`_
`(edited and annotated)
`
`Figure A.3
`
`35.
`
`Paul discloses a capacitor configuration in which “the top and bottom
`
`shields 1308 and 1310 are connected to a third node, shown in this example as
`
`reference Voltage (e.g., ground).”
`
`(Paul, 4:60-63.) The top and bottom shields
`
`1308 and 1310 are “a reference shield connected to a reference node of the IC
`
`other than the second node of the capacitor.
`
`Paul does not explicitly illustrate a
`
`99
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`_ 17 _
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`capacitor having both a “shield capacitor portion” and a “reference shiel .”
`
`However, Paul discloses that “various combinations of configurations are also
`
`possible.” (Paul, 3:64-67).
`
`In particular, Faul discloses that “one or more shields
`
`are disposed around layers of conductive strips to shield the capacitor.” (Paul,
`
`Abstract). A person of ordinary skill in the art would have combined the core
`
`capacitor portion and shield capacitor portion of FIG. A.3 with the reference
`
`shield depicted in FIG. 13 of Paul. FIG. A.4 edits FIG. 13 of Paul to depict this
`
`combination.
`
`reference shield
`
`
`
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`
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`
`FIG. :3 (edited and annotated)
`
`Figure A.4
`
`Irzter Partes Review of U.S.P. 7,994,609
`
`3059.701IPRO
`
`

`
`-
`
`_
`
`36.
`
`The various configurations of Paul disclose each and every limitation
`
`of claim 1. Paul does not explicitly disclose each limitation integrated into a single
`
`capacitor structure. However, a person of ordinary skill in the art could combine
`
`the configurations of Paul according to known methods to yield predictable results.
`
`37. A chip designer of ordinary skill desiring the benefits of a capacitive
`
`element immediately coupled to one or more active elements on the die would, in
`
`the normal course of layout, have tended toward a symmetrical configuration as
`
`illustrated in FIG. A.3. The manifold benefits of physical structures that are
`
`symmetrical relate to chip fabrication masking, additive and subtractive processes
`
`as well as electrical performance. When die area allows, passive components such
`
`as capacitors and conductive elements such as interconnects can be advantageously
`
`drawn with symmetrical areas and volumes so as to achieve relatively constant
`
`ratios of conductors
`
`to
`
`dielectrics. This
`
`approach minimizes
`
`electrical
`
`discontinuities associated with sudden changes in conductor (net) cross section
`
`and/or fluctuations in dielectric—to-conductor spacing. Attention to this level of
`
`detail can, in certain chip fabrication sequences, reduce the probability of process
`
`induced defects and potentially increase conductor bandwidth. For these reasons, a
`
`person of ordinary skill in the art would have been motivated to combine the
`
`configurations disclosed in Paul in the manner discussed.
`
`Inter Partes Review of U.S.P. 7,994,609
`
`3059.70lIPRO
`
`

`
`B. Paul Renders Dependent Claim 3 (}bvious.
`
`_ 19 -
`
`38.
`
`In my opinion, a person of ordinary skill in the art would find claim 3
`
`obvious in view of the teachings of Paul. Dependent claim 3 of the ‘609 Patent is
`
`reproduced below.
`
`The capacitor of claim 1 wherein the shield capacitor
`portion includes a first node shield plate formed in the
`third conductive layer and a second node shield plate
`formed in the fourth conductive layer and further
`comprising a first conductive curtain extending from the
`first node shield plate to the second node shield plate and
`a second conductive curtain extending from the first node
`shield plate to the second node shield plate.
`
`39.
`
`The shield capacitor portion of Paul includes a top shield, depicted as
`
`408 in FIG. 4 of Paul and 808 in FIG. 8, and a bottom shield, depicted as 410 in
`
`FIG. 4 and 810 in FIG. 8. The “first shield 408 [is] formed in the METAL 4 layer
`
`above the conductive strips,” and the “second shield 410 is formed in the METAL
`
`1
`
`layer below the conductive strips.” (Paul, 3:25-31.) As discussed above, the
`
`METAL 4 and METAL 1
`
`layers of Paul (shown in annotated FIG. 4 above) are
`
`equivalent to the “third conductive layer” and the “fourth conductive layer,” “The
`
`shield 408 is formed by a solid conductive plate” and “shield 410 is formed by a
`
`solid conductive plate.” (Paul, 3:26-30.) As would be appreciated by a person of
`
`ordinary skill in the art, the upper shield 808 is a “first node shield plate” and the
`
`bottom shield 810 is a “second node shield plate.” Although the bottom shield is
`
`Inter Partes Review of U.S.P. 7,994,609
`
`3059.70lIPRO
`
`

`
`_ 20 _
`
`depicted as not extending beneath the side shield (curtain), a person of ordinary
`
`skill in the art would appreciate that the bottom shield could be extended.
`
`40.
`
`The ‘609 patent provides a description of a conductive curtain as
`
`“conductive filaments
`
`formed in successive metal
`
`layers connected with
`
`conductive vias to form essentially a conductive sheet extending perpendicular to
`
`and from the plane of illustration.” IVM 1001, 10:3-7. The configurations of Paul
`
`when combined disclose a conductive curtain as defined by the ‘609 Patent. FIG.
`
`A.4 depicts a capacitor configuration having a side shield “formed on both sides of
`
`the capacitor.” (Paul, 4:28-30.) “[T]he conductive strips 804 of the side shield 812
`
`are connected to each other, and to the top shield 808, by vias 814.” (Paul, 4:30-
`
`32.) FIG. B below annotates the capacitor configuration of FIG. A.4 to illustrate
`
`how the limitations of claim 3 map to the capacitor of FIG. A.4.
`
`41. A person of ordinary skill
`
`in the art would have combined the
`
`configurations as suggested by Paul to obtain the capacitor of claim 3. In addition
`
`to the enhanced isolation provided by FIG. B, the chip fabrication and electrical
`
`performance advantages of increased symmetry are further motivation for the
`
`combination.
`
`Inter Partes Review of U.S.P. 7,994,609
`
`3059.701IPRO
`
`

`
`-21-
`
`
`
`lstmde Shield P1393 ref:::re11c.r: shield
`
`i
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`
`,
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`3” “Gd? 55?“ Iiifitc He, 13 (edited am annotated)
`
`Figure B
`
`C. Paul Renders Dependent Claim 5 Obvious.
`
`42.
`
`In my opinion, a person of ordinary skill in the art would find claim 5
`
`obvious in View of the teachings of Paul. Dependent claim 5 of the ‘609 Patent is
`
`reproduced below.
`
`The capacitor of claim 1 wherein the reference node is a
`VDD node.
`
`43. As explained by Paul,
`
`in a capacitor configuration, “the top and
`
`bottom shields 1308 and 1310 are connected to a third node, shown in this example
`
`as a reference Voltage (e. g., ground) rather than to nodes A or B.” (Paul, 4:60-64.)
`
`Inter Partes Review of U.S.P. 7,994,609
`
`3059.70lIPRO
`
`

`
`_ 22 _
`
`Although Paul does not explicitly disclose VDD as an exemplary reference voltage,
`
`it would have been a routine and obvious design choice to use VDD as the reference
`
`node. The chip designer, depending on surrounding adjacent available structures,
`
`voltages and circuit requirements, simply would be motivated, in an ordinary and
`
`inevitable way, to see VDD as one of the available layout and/or electrical tools or
`
`variables available to effectively implement the target circuit. Because a person of
`
`ordinary skill in the art would appreciate that any voltage could be used as the
`
`reference node, the choice of VDD as the reference node would have been obvious
`
`to a person of ordinary skill in the art.
`
`D. Paul Renders Dependent Claim 12 Obvious.
`
`44.
`
`In my opinion, a person of ordinary skill in the art would find claim
`
`12 obvious in view of the teachings of Paul. Dependent claim 12 of the ‘609
`
`Patent is reproduced below.
`
`further comprising a second
`The capacitor of claim 1
`reference shield connected to a second reference node of
`
`the IC, the reference shield being disposed between the
`second reference shield and the shield capacitor portion.
`
`45.
`
`Paul discloses the use of both a capacitor shield and a reference
`
`shield.
`
`Paul explains that the “shields of the present invention may take on
`
`numerous forms in addition to the examples described above.” IVM 1006, 4:56-
`
`57.) For example, Paul discloses that “one or more shields are disposed around
`
`Inter Partes Review of U.S.P. 7,994,609
`
`3059.70lIPRO
`
`

`
`_ 23 _
`
`layers of conductive strips to shield the capacitor.” (Jones, Abstract.) Based on
`
`these disclosures in Paul, a person of ordinary skill in the art would combine the
`
`capacitor configurations disclosed by Paul to add a second reference shield above
`
`the first reference shield. FIG. C below depicts the capacitor structure of FIG. A.4
`
`modified to add a second reference shield. There are certain circuit designs where
`
`fluctuation in the capacitive values caused by relatively small discontinuities in the
`
`shielding of the capacitor would degrade the performance of the circuit either
`
`continuously or intermittently depending on the noise source strength, frequency
`
`and periodicity.
`
`In these cases, a person of ordinary skill in the art of chip design
`
`would, in the normal course of layout and in certain cases (eg, a full 3D field
`
`solver simulation of the local structures)
`
`invoke the “third node” approach
`
`manifested in FIG. C.
`
`Inter Partes Review of U.S.P. 7,994,609
`
`3059.70lIPRO
`
`

`
`.24.
`
`se: ond
`reference shield
`
`refer:-nee
`
`shield capacitor
`por1ion\m~‘| . _ . _ _ . _ . _ . _ . _ _ _ _ _ . _ _ . _ . _ _ . _ _ _ . _ . _ . _ .. . _ ..__
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`
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`
`BE 2"“ layer
`
`4thlaYe1
`
`
`"—'7‘—"—“-~—————-‘-——-——————-~————«——
`
`FIG, 13 (edited and annotated)
`
`Figure C
`
`VI. U.S. Patent No. No. 6,737,698 to Paul, et al in View of U.S. Fatent No.
`
`7,439,570 to Anthony
`
`46.
`
`U.S. Patent No. 7,439,570 to Anthony, titled “Metal-Insulator—Metal-
`
`Capacitors,” (“Anthony”) issued on October 21, 2008, prior to the filing date of the
`
`‘609 Patent. A copy of Anthony is provided as IVM 1007.
`
`47. Anthony discloses an interdigitated Metal-Insulator-Metal
`
`(MIM)
`
`capacitor that provides “self-shielding and accurate capacitance ratios with small
`
`capacitance values.”
`
`(Anthony, Abstract.) The capacitor structures of Anthony
`
`include “[c]ontinuous metal plates extend at least as far as the outermost fingers,
`
`occupying metal layers above and below the layer containing the fingers, and
`
`Inter Partes Review of U.S.P. 7,994,609
`
`3059.70llPRO
`
`

`
`_ 25 _
`
`separated from the fingers by layers of dielectric, with the plates connected to the
`
`outermost fingers. As a result, the first terminal shields the second terminal at all
`
`sides,
`
`thereby providing self-shielding to the capacitor.”
`
`(Anthony, 2:31-37.)
`
`Additional shielding “may be provided by layers above and below the capacitor.
`
`The shielding layers may be electrically isolated from the terminals and connected
`
`by a series of metal layers and Vias encompassing the capacitor.” (Anthony, 2:38-
`
`42.)
`
`A. Paul and Anthony Render Dependent Ciaim 2 Obvious.
`
`48.
`
`In my opinion, a person of ordinary skill in the art would find claim 2
`
`obvious in view of the teachings of Paul and Anthony. Dependent claim 2 of the
`
`‘609 Patent is reproduced below.
`
`The capacitor of claim 1 wherein the third conductive
`layer is a metal layer of the IC and the fourth conductive
`layer is a poly layer of the IC,
`the shield capacitor
`portion including a first node shield plate formed in the
`metal layer from a plurality of metal stripes and a second
`node shield plate formed in the poly layer.
`
`49.
`
`The capacitor of Paul includes a top shield 808 formed in METAL 4
`
`layer. METAL 4 layer of Paul is equivalent to the third conductive layer. Paul
`
`further explains that the top shield may be comprised of conductive strips 704.
`
`(Paul, 4:20-23 )(“FIG. 7 shows an example of a capacitor 700 where the shields
`
`Inter Partes Review of U.S.P. 7,994,609
`
`3059.70lIPRO
`
`

`
`_ 26 _
`
`708 and 710 are comprised of conductive strips 704 and 706 rather than a
`
`continuous metal plate.”).
`
`50.
`
`Paul also discloses a shield plate formed in the fourth layer of the IC.
`
`Paul does not disclose that the fourth layer is a polysilicon layer of the IC or that a
`
`second node shield is formed in the polysilicon layer.
`
`FIG. 3B of Anthony
`
`(reproduced below) illustrates a “[c]apacitor 30 [that] is surrounded by a shield
`
`‘w

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