`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`INTELLECTUAL VENTURES MANAGEMENT, LLC
`
`Petitioner
`
`V.
`
`XILINX, INC.
`
`Patent Owner
`
`Case IPR2012-00023
`
`Patent 7,994,609
`
`PETITICENER INTELLECTUAL VENTURES MANAGEMEN? LLC’S
`REPLY TO PATENT {§WNER’S RESPONSE
`
`
`
`Table of Contents
`
`1.
`
`Statement of relief requested ............................................................................ .. 1
`
`II.
`
`Original claims 1-19 are obvious over the art cited in the Petition. .............. .. 1
`
`A.
`
`Claim 2 is obvious over Paul and Anthony ................................................ .. 1
`
`1. The combination of Paul and Anthony discloses the limitations of claim 2.2
`
`2. The combination of Paul and Anthony disclose a shield plate that is part of
`
`the second node of the capacitor. ..................................................................... .. 3
`
`3. The combination of Paul and Anthony disclose a shield plate formed in a
`
`poly layer. ......................................................................................................... .. 4
`
`4. A person of ordinary skill in the art would have combined Paul and
`
`Anthony as set forth in the Petition. ................................................................. .. 5
`
`B.
`
`Claim 8 is obvious over Paul and Brennan ................................................ .. 6
`
`1. Claim 8 does not require the “second conductive layer” to be a so-called
`
`plate layer. ........................................................................................................ .. 8
`
`2. The distinction that Xilinx draws between “balanced” and “unbalanced”
`
`capacitors would not prevent one skilled in the art from combining Paul and
`
`Brennan as provided in the Petition. ................................................................ .. 9
`
`C.
`
`D.
`
`Claim 18 is obvious over Anthony in view ofMarotta ............................. .. 12
`
`Claim 19 is obvious over Anthony in view ofMarotta ............................. .. 13
`
`IV. Conclusion ................................................................................................... .. 15
`
`
`
`IPR2O 12-00023
`
`Patent 7,994,609
`
`Table sf Authoritées
`
`Cases
`
`See In re Keller, 642 F.2d 413 (CCPA 1981). ........................................................ .. 3
`
`
`
`Petitioner Intellectual Ventures Management, LLC (“IVM”) provides this
`
`reply under 37 C.F.R. § 42.23 to Patent Owner Xilinx’s Patent Owner’s Response
`
`dated May 7, 2013. Inter partes review of claims 1-19 of U.S. Patent No.
`
`7,994,609 was instituted on February 12, 2013.
`
`I.
`
`Stateazient of relief requested
`
`IVM seeks cancellation of claims 1-19 of the ’609 patent and denial of
`
`Xilinx’s First Motion to Amend filed May 7, 2013 (First Motion to Amend, Paper
`
`No. 17). An opposition to the Motion to Amend is being filed concurrently.
`
`ii.
`
`Original claims 1-19 are obvious over the art cited in the Petition.
`
`In its Patent Owner’s Response, Xilinx does not separately address any
`
`grounds of patentability instituted for independent claims 1 and 13 and their
`
`dependent claims 3-7, 9-12, and 14-17. Thus, Xilinx concedes that these claims are
`
`unpatentable over the instituted grounds. Xilinx, instead, focuses its reply solely on
`
`independent claim 18 and dependent claims 2, 8, and 19. But, as described below,
`
`the arguments presented by Xilinx are contradicted by the evidence of record,
`
`including the deposition testimony of its own expert, Dr. Blanchard.
`
`A.
`
`Claim 2 is obvious over Paul] and Anthony2
`
`1 U.S. Patent No. 6,737,698 (IVM1006).
`
`2 U.S. Patent No. 7,439,570 (IVM1007).
`
`
`
`IPR2012-00023
`
`Patent 7,994,609
`
`1.
`
`The combination of Paul and Anthony discloses
`limitations of claim 2.
`
`the
`
`Claim 2 recites “wherein the third conductive layer is a metal layer of the IC
`
`and the fourth conductive layer is a poly layer of the IC,
`
`the shield capacitor
`
`portion including a first node shield plate formed in the metal layer from a
`
`plurality ofmetal stripes and a second node shieldplateformed in the poly layer.”
`
`As explained in the Petition metal layer 1 and bottom shield plate 810, shown in
`
`FIG. 8 of Paul which is reproduced below with annotations in red, disclose a
`
`“fourth layer” and a “second node shield plate,” respectively. (Petition, Paper No.
`
`3, p. 24.)
`
`8m—\‘
`
`a
`
`..
`
`E
`
`"
`[W
`A
`secs
`
`51°
`
`A
`
`5
`
`A
`
`“J
`
`in
`
`FIG. 8
`
`
`
`
`
`a
`
`M
`2.1
`
`nd
`
`2 node
`sh1eld plate
`
`.
`
`MEl'AL4—*
`a12\:J__,{a17
`333,4 L “""
`Mm
`
`A
`7- _‘}§
`MW-*§|
`'33;
`‘M
`
`:
`
`414
`
`th
`4 layer
`
`MErAL1r>il ;
`:"’&i.._“:’il'
`
`Although Paul’s metal layer 1 is not a poly layer, Anthony teaches that the
`
`bottom layer of a capacitor can be formed in a poly layer instead of a metal layer:
`
`“[a]s an alternative to the use of a metal layer as shown in FIG. 3B...the bottom
`
`shield plate 36 can be implemented with a polysilicon or diffusion layer.” (IVM
`
`1007, 4:49-52.) Petitioner’s expert, Mr. Johnson, further explained in his First
`
`Declaration that one of ordinary skill in the art would have been motivated to
`
`
`
`modify Pau1’s capacitor to implement the shield plate in a polysilicon layer and the
`
`results would have been predictable. (IVM1002, 1] 50.)
`
`IPR20l2-00023
`
`Patent 7,994,609
`
`
`
`
`/.ma§uu
`
`_\
`
`F5’/‘<’l{’/’>‘
`
`
`
`
`
`“J
`
`36
`
`FIG. 3B
`
`Xilinx, in its Patent Owner Response, presents two arguments to overcome
`
`the obviousness of claim 2 over Paul and Anthony. First, Xilinx argues that neither
`
`Paul nor Anthony teach a “shield plate” that is “part of the second node of the
`
`capacitor.” Second, Xilinx argues that neither Paul nor Anthony teaches a “shield
`
`plate” that
`
`is “formed in the poly layer.” As set forth below, each of these
`
`arguments is misplaced.
`
`2.
`
`The combination of Paul and Anthony disclose a shieid
`plate that is part of the second node of the capacitor.
`
`In its Response, Xilinx argues that bottom shield plate 36 of Anthony is not
`
`connected to a node of the capacitor and therefore not “a second node shield plate,”
`
`as recited in claim 2:
`
`Thus, bottom shield plate 36/46 is a reference
`
`shield, and is never
`
`shown or suggested as being
`
`connected to or part of the capacitor node. This
`
`
`
`IPR2012-00023
`
`Patent 7,994,609
`
`configuration is different from claim 2 of the ‘609 patent,
`
`which recites a shield capacitor portion that
`
`is both
`
`“electrically connected to and forming a
`
`part of the
`
`second node of the capacitor” and that is formed in the
`
`poly layer.
`
`(Patent Owner Response, Paper No. 15, p.
`
`9.)
`
`Xilinx’s argument is legally deficient. Xilinx attacks only Anthony despite the
`
`obviousness ground being based on a combination of Paul and Anthony—namely
`
`Paul’s bottom shield plate 810 and Anthony’s poly layer. Xilinx does not reference
`
`or even address Petitioner’s position that Paul’s shield plate 810 discloses a shield
`
`plate connected to a capacitor node. Further, it is well settled that an obviousness
`
`ground cannot be rebutted by attacking a single reference when the ground is based
`
`on a combination of references. See In re Keller, 642 F.2d 413 (CCPA 1981).
`
`3.
`
`The combination of Paul and Anthony disclose a slgield
`
`plate formed in a poly layer.
`
`Xilinx also argued that Anthony does not disclose a shield plate formed in a
`
`poly layer:
`
`In other words, Anthony’s capacitor in FIG. 4 has
`
`a first plate 33 and a second plate 34 where both plates
`
`are formed of metal layers overlying the substrate, not in
`
`poly or in the diffiision. (Paper No. 15, p. 8)
`
`IVM disagrees. As noted above, Anthony clearly states that shield plate 36 (shown
`
`in FIG. 3B of Anthony) can be formed in a poly layer. (IVM 1007, 4:49-52.)
`
`-4-
`
`
`
`During his deposition, Xilinx’s expert, referencing this sentence of Anthony,
`
`agreed with IVM’s position:
`
`IPR20l2-00023
`
`Patent 7,994,609
`
`Q. Does Anthony disclose that a shield plate of a
`
`capacitor can be implemented in a polysilicon layer?
`
`A.
`
`It
`
`says: The bottom shield plate 36 can be
`
`implemented with a polysilicon layer.
`
`(Blanchard Deposition, IVM1 014, 51:21-24; see also IVM 1013 , ‘J 19.)
`
`4.
`
`A person of ordinary skill in the art would have combiéed
`Paul and Anthony as set forth in the Petition.
`
`One skilled in the art in 2008 would have appreciated that forming Paul’s
`
`bottom shield plate 810 in a poly layer instead of a metal layer could have been
`
`done and would have provided predictable benefits.
`
`(IVMlOl3,
`
`‘fl 20.) As
`
`explained by Mr. Johnson, design tools available in 2008 would have enabled one
`
`of ordinary skill
`
`in the art to form Paul’s layer 1
`
`in poly instead of metal.
`
`(IVMlOl3, ‘I 20.) During his deposition, Xilinx’s expert Dr. Blanchard agreed:
`
`Q. Okay. And would a designer of capacitors with
`
`ordinary skill in the art, having the design tools we spoke
`
`about, be able to modify the capacitor of Paul to
`
`have a shield plate to --
`
`to have Shield Plate 810
`
`implemented with a polysilicon layer?
`
`THE REPORTER: I'm sorry. Implemented --
`
`MS. GORDON: With a polysilicon layer.
`
`
`
`IPR2012-00023
`
`Patent 7,994,609
`
`A. I believe that such a designer could. I'm not
`
`sure the designer would, however. (IVM1014, 56:24-
`
`57:7.)
`
`Further, one skilled in the art would have been motivated to make this substitution
`
`to,
`
`for example, save a metal
`
`layer for another purpose or as a matter of
`
`convenience depending on where a signal may be coming from. (IVM10l3, fl 20.)
`
`Dr. Blanchard, referencing Anthony at 4:50, concurs:
`
`As with traffic out here in Dallas, sometimes you
`
`need to get from A to B, where A to B is across the street.
`
`So one way of accomplishing that
`
`is with an over- or
`
`underpass, and the over- or underpass that's discussed here
`
`would be in the layer of polycrystalline silicon, or perhaps
`
`one of a couple of reasons, one having to do with a layout,
`
`because all the other conductive layers were used up, so you
`
`need something here, or just out of convenience, a signal
`
`might be going to or coming off the poly layer associated
`
`with a gate or something else. And it's just convenient to
`
`use the interconnect at that location.
`
`(IVM1014, 52:14-25.)
`
`Thus, one skilled in the art would have been able and motivated to form Paul’s
`
`bottom shield plate 810 in a poly layer instead of a metal layer.
`
`B.
`
`€laim 8 is obvious over Paul and Brennan
`
`In its Patent Owner Response, Xilinx first argues that claim 8 requires a
`
`“plate layer,” i.e., a layer in which all conducting elements are coupled to the same
`
`-5-
`
`
`
`IPR2012-00023
`
`Patent 7,994,609
`
`node. (Paper No. 15, pp. 11-12.) Second, Xilinx argues against the combination of
`
`Paul and Brennan because this combination would change the “:fi.1nctional
`
`operation of the resulting capacitor” by changing a “balanced” capacitor into an
`
`“unbalanced capacitor.” (Paper No. 15, p. 15.)
`
`Claim 8 recites “wherein each of the conductive elements in the third
`
`plurality of conductive elements is aajacent to a conductive element electrically
`
`connected to and forming a third party of the first node.” As Mr. Johnson
`
`explained in his First Declaration, Paul discloses that the core capacitor portion can
`
`be formed out of “any number of layers of conductive strips.” (IVM1002, ‘T 77
`
`citing IVM1006, 4:51-52.) l\/Ir. Johnson fiirther explained that based on this
`
`teaching, the capacitor of Paul could be modified according to Brennan to form the
`
`capacitor shown in FIG. G of his Declaration, which is reproduced below. Mr.
`
`Johnson also explained that one of ordinary skill
`
`in the art would have been
`
`motivated to combine Paul and Brennan “because both relate to shielded capacitors
`
`and the results of the combination would have been predictable.” (IVM1002, ‘.1 75.)
`
`Indeed, according to Mr. Johnson, “[t]he combination discussed above might
`
`consume a certain amount of additional cubic microns over simpler capacitive
`
`layouts and the shielding aspect would further expand the size of the integrated
`
`capacitor but this would be more than offset by the overall layout reduction in 2D
`
`
`
`footprint and reduced cubic volume of the more compact, noise resistant layouts
`
`facilitated by said combination.” (IVMl002, €] 75.)
`
`IPR2012-00023
`
`Patent 7,994,609
`
`
`
`-Uhphnaliry of
`conductive elements
`
`...i;"§.'.“”;’;m°f...
`
`FIG. G of the Johnson Deciaration
`
`As explained below, Xilinx’s arguments in its Patent Owner Response for claim 8
`
`are premised on an overly narrow interpretation of claim 8. Even with this
`
`interpretation, Xilinx still does not dispute that the combination of Paul and
`
`Brennan disclose all the features of claim 8. Rather, Xilinx relies on an illusory
`
`difference between “balanced” and
`
`‘unbalanced” capacitors
`
`to attack the
`
`C
`
`combination of Paul and Brennan.
`
`1.
`
`Claim 8 does not require the “second conductive layer” to
`be a so-called plate Eayer.
`
`In its Response, Xilinx, referencing FIG. 2A of the ‘609, alleges that “[t]he
`
`claimed ‘second conductive layer’ (referred to as metal 2, or M2 in the patent) only
`
`includes conductive elements from the top node (T). The ‘609 patent refers to this
`
`
`
`IPR2012-00023
`
`Patent 7,994,609
`
`latter type of layer, where there are not alternating conductive elements, as a plate
`
`layer.” (Paper No. 15, p. 11.)
`
`Xilinx appears to assert that “adjacent” in claim 8 requires the conductive
`
`elements to be in the same layer—thereby requiring all of the elements in that layer
`
`be coupled to the same node, and thus making the layer a “plate layer.” Claim 8
`
`does not use the word “plate.” Further, one skilled in the art reading claim 8 would
`
`appreciate that a conductive element that is above or below a given conductive
`
`element is also “adjacen ” to that conductive element. (IVM10l3, ‘ll 21.) During his
`
`deposition, Xilinx’s expert Dr. Blanchard agreed that conductive elements above
`
`or below an element are adjacent to that element. Specifically, referencing FIG. 2B
`
`of the ‘609 Patent Dr. Blanchard agreed that elements B1, B2 of layer M3 and
`
`element B5 of layer Ml are all “adjacent” to element T of layer M2. (IVMlOl4,
`
`88:15-89:12.) Thus, claim 8’s recitation of “adjacent” does not require the “second
`
`conductive layer” of claim 8 to be a “plate” layer.
`
`2.
`
`The distinction that Xilinx draws between “balanced” and
`
`“unbalanced” capacitors would not prevent one skilled in
`the art from combining Paul and Brennan as provided in
`the Petition.
`
`In the Petition, IVM provided FIG. G of the Johnson Declaration (shown
`
`above) that shows how the combination of Paul and Brennan would teach all of the
`
`features of claim 8. Even under its overly narrow interpretation of claim 8, Xilinx
`
`
`
`IPR2012-00023
`
`Patent 7,994,609
`
`does not dispute that the combination teaches all of the features of claim 8. Rather,
`
`Xilinx alleges that “both Paul and Brennan are directed to balanced capacitors” and
`
`that “[t]he capacitor described in FIG. G [of the Johnson Declaration] has
`
`converted the balanced capacitor of Paul (and the balanced capacitor of Brennan)
`
`into an unbalanced [capacitor]” because more nodes are connected to node A than
`
`to node B. (Paper No. 15, pp. 14-15.) In doing so, the modification allegedly
`
`changes “the functional operation of the resulting capacitor in a way not previously
`
`described.” (Paper No. 15, p. 15.) Indeed, Xilinx argues that an “unbalanced”
`
`capacitor is a “switching capacitor.” Xilinx’s arguments fail for at
`
`least two
`
`reasons.
`
`First, Paul discloses both “balanced” and “unbalanced” capacitors. For
`
`example, FIG. 8 of Paul can be “balanced” or “unbalanced” depending on the
`
`distance between side shield 812 and strips 804 and 806. (IVM1013, 1] 22.) Dr.
`
`Blanchard agrees with Mr. Johnson that the capacitor shown in FIG. 8 of Paul
`
`could be unbalanced depending on its specific implementation. (IVM1014, 73:6-
`
`7423.)
`
`In response to questions from Xilinx’s counsel, Dr. Blanchard testified at
`
`deposition that the core capacitor portion of FIG. 8 of Paul is balanced. (IVM1014,
`
`92:14-93:16.) However, this testimony is irrelevant because Xilinx premises its
`
`argument on the entire capacitor being balanced not just a portion of the capacitor.
`
`-10-
`
`
`
`IPR2012-00023
`
`Patent 7,994,609
`
`Dr. Blanchard confirmed on re-direct that the capacitor shown in FIG. 8 of Paul, as
`
`a whole, could be balanced or unbalanced depending on the positioning of shield
`
`812.
`
`(IVM1014, 95:18-96:11.)
`
`Further, Dr. Blanchard only provided this
`
`testimony after consultation with Xilinx’s counsel during a break prior to
`
`conclusion of the deposition. (See IVM1014, 93:22-94:3.) Consultation with a
`
`witness regarding the substance of testimony prior to conclusion of the deposition
`
`violates the Testimony Guidelines provided in the Office Patent Trial Practice
`
`Guide. (Office Patent Trial Practice Guide, 77 Fed. Reg. 48756, 48772 (Aug. 14,
`
`2002) (APPENDIX D: Testimony Guidelines). As a result, IVM requests that the
`
`testimony of Dr. Blanchard elicited by Xilinx’s counsel be provided no weight.
`
`Second, whether a capacitor is a “switching” capacitor depends on the
`
`circuit in which it is implemented—whether it is coupled to a switch—not whether
`
`it
`
`is balanced or unbalanced.
`
`(IVM1013,
`
`
`
`23.) “Switching capacitors” are
`
`capacitors which add to or subtract from the capacitance of a circuit based on the
`
`state of a switch coupled to the capacitor. (IVM1013, TI 23; IVMl0l4, 84:1-ll.)
`
`For example,
`
`in FIG.
`
`1 of the ‘609 Patent, capacitor 104 is configured as a
`
`switching capacitor. (IVM 1013, 1] 23; IVM10l4, 8421-1 1.) Both a balanced and an
`
`unbalanced capacitor can be used for
`
`this application, albeit with certain
`
`performance ramifications. (IVM 1013, ‘H 24; IVMl0l4, 85:7-86:12.) Indeed, both
`
`before and after the modification, Paul’s capacitor functions as a capacitor. (IVM
`
`-11-
`
`
`
`IPR2012-00023
`
`Patent 7,994,609
`
`1013,
`
`24; IVM1014, 82:17-20.) Thus, the possibility of changing a “balanced”
`
`capacitor to an “unbalanced” capacitor would not prevent one skilled in the art
`
`from combining Paul and Brennan as shown in FIG. G of Mr. Johnson’s first
`
`declaration.
`
`C.
`
`Cfaim 18 is obvious over /fnthony in view offilarotta
`
`Claim 18 recites, in part, “a second plate formed in a substrate of the IC.” As
`
`explained in the Petition, bottom shield plate 46, shown in FIG. 4 of Marotta
`
`discloses a “second plate formed in a substrate of the IC.” (Paper No. 3, p. 46.)
`
`In its Patent Owner Response, Xilinx first argues that IVM improperly relies on
`
`Mr. Johnson’s first Declaration to teach this element. (Paper No. 15, p. 16.) But as
`
`IVM explained in the Petition, the ground of obviousness relies on two patents-
`
`Anthony and Marotta. Each of the elements of claim 18 is taught by the
`
`combination of Anthony and Marotta. Mr. Johnson’s declaration is provided to
`
`explain that one of ordinary skill
`
`in the art could have and would have been
`
`motivated to combine Anthony and Marotta. This use of expert testimony is not
`
`prohibited by 35 U.S.C. § 311(b). Indeed, Petitioner notes that the Board “expects
`
`that most petitions and motions will rely upon affidavits of experts.” (Office Patent
`
`Trial Practice Guide, 77 Fed. Reg. 48756, 48763 (Aug. 14, 2002) (II.A.4)).
`
`Second, Xilinx rehashes an argument that the Board rejected in its Decision
`
`to Institute. Specifically, Xilinx argues—without any support from its expert Dr.
`
`-12-
`
`
`
`IPR2012-00023
`
`Patent 7,994,609
`
`Blanchard—that “shield plate 36/46 of Anthony is not a plate of the capacitor, but
`
`is a reference shield.” (Paper No. 15, p. 16.) But as the Board explained in its
`
`Decision, “IVM’s annotated Figure 4 shows a bottom or second shield plate 46 and
`
`a first plate 34 that has a dielectric interposing the two plates and satisfies the
`
`claimed capacitor structure, regardless of what Anthony calls the structure.” (Paper
`
`No. 11, p. 12.) Xilinx provides no argument or evidence to rebut the Board’s
`
`explanation. Thus, at least for the same reasons provided in the Decision claim 18
`
`is obvious over Anthony in view of Marotta.
`
`D.
`
`Claim 19 is obvious over Anthony in view ofMarotta
`
`In its response, Xilinx provides two arguments to counter the instituted
`
`obviousness rejection of claim 19. As explained in detail below, each of these
`
`arguments is flawed. Claim 19 recites:
`
`The capacitor of claim 18 wherein the first
`
`conductive layer
`
`is a first poly layer,
`
`the substrate
`
`comprises silicon and second plate is formed in an N-
`
`well of the substrate and the shield plate is formed in a
`
`second poly layer of the IC.
`
`Referencing claim 18, from which claim 19 depends, the Petition explained that
`
`the plate in FIG. 4 of Anthony that includes plate 34 teaches a “first conductive
`
`layer.” (Paper No. 3, p. 45.) Xilinx does not dispute this point. (FIG. 4 of Anthony
`
`is reproduced below.)
`
`-13-
`
`
`
`IPR2012-00023
`
`Patent 7,994,609
`
`
`
`As further explained in the Petition, Anthony discloses that bottom shield plate 36
`
`(shown in FIG. 3B of Anthony, reproduced above) can be formed in a poly-silicon
`
`or diffusion region. (Paper No. 3, p. 51 citing IVMl007,4:49-53.) In view of this
`
`disclosure, the first conductive layer of Anthony in a poly layer. (Paper No. 3, p.
`
`51.) Mr. Johnson further explained that one skilled in the art would be able to make
`
`this modification using a “double poly” process. (IVM1002, fi[ 88.)
`
`Xilinx again argues that IVM improperly relies on Mr. Johnson’s first
`
`Declaration. Xilinx’s argument is misplaced. Mr. Johnson’s first Declaration was
`
`provided to explain how one skilled in the art would view Anthony and Marotta.
`
`Xilinx further argues that claim 19 is patentable over Anthony and Marotta
`
`because “a double-poly layer IC is not disclosed in the prior art.” (Paper No. 17, p.
`
`17.) IVM disagrees. As Mr. Johnson explained in his First Declaration, a “double
`
`poly” process was well known before 2008. (See IVMl002 ‘W 86-88.) Indeed,
`
`Xilinx’s own expert agrees, stating not only that a “double poly process” was
`
`likely known before 2008, but that the inventor of the ‘609 patent likely was not
`
`the first person to use a double poly process in a capacitor. (IVMl014, 60:4-12.)
`
`Thus, Xilinx’s allegation that double poly processes were not in the prior art is
`
`-14-
`
`
`
`IPR2012-00023
`
`Patent 7,994,609
`
`contradicted by both experts. These processes were well known to those of
`
`ordinary skill in the art. Thus, claim 19 is obvious over Anthony and Marotta.
`
`TV. Conclusion
`
`For at least the foregoing reasons, as well as those set forth in the Petition
`
`for
`
`Inter Partes Review filed September 17, 2012,
`
`Intellectual Ventures
`
`respectfiilly requests the cancellation of claims 1-19 of the ’609 patent.
`
`Respectfully submitted,
`
`1
`DATE: August 23, 2013 By:
`
`Lori A. Gordon, Lead Counsel (Reg. No. 50,633)
`Robert G. Sterne, Backup Counsel (Reg. No. 28,912)
`STERNE, KESSLER, GOLDSTEIN Fox P.L.L.C.
`1 100 New York Avenue, NW
`
`Washington, D.C. 20005
`(202) 371-2600
`
`Attorneys for Petitioner,
`Intellectual Ventures Blanagement, LLC
`
`-15-
`
`
`
`CERTIFICATE OF SERVICE
`
`I hereby certify that on this 23rd of August, 2013, a true and correct copy of
`
`the foregoing PETITIONER INTELLECTUAL VENTURES MANAGEMENT,
`
`LLC’S REPLY TO PATENT OWNER’S RESPONSE was served upon the
`
`following counsel for Patent Owner, Xilinx Inc.
`
`David M. O’Dell, Lead Counsel
`
`ATTN: IP DOCKETING
`
`HAYNES AND BOONE, LLP
`2323 Victory Avenue, Suite 700
`Dallas, TX 75219
`
`david.ode1l@haynesboone.com
`
`Thomas B. King
`HAYNES AND BOONE, LLP
`
`18100 Von Karman, Suite 750
`
`Irvine, CA 92612
`
`thomas.king@haynesboone.com
`
`
`RJ
`Lori A. Gordon, Lead Counsel (Reg. No. 50,633)
`
`STERNE, KESSLER, GOLDSTEIN Fox P.L.L.C.
`l 100 New York Avenue, NW
`
`Washington, D.C. 20005
`(202) 371-2600
`
`Attorney for Petitioner
`Intellectual Ventures Management, LLC