`
`
`
`IPR2012-0023
`Exhibit XLNX-2007
`Curriculum Vitae of
`Richard A. Blanchard, Ph.D.
`
`
`Expertise
`
` MOS and Bipolar Device Tech.
` Semiconductor Device Physics
` Microchip Fabrication & Analysis
` Electronic Systems
` Electrical & Electronic Failures
` ESD & EOS Failures
` Assembly & Packages
`
`
`
`
` CMOS, DMOS & BiCMOS Tech.
` Power IC’s & Power Electronics
` Printed Circuit Board Mfg.
` Printable Electronics, including
`LEDs
` Semiconductor Process & Control
` Patents & Trade Secrets
`
`
`
`Blanchard Associates
`
`
`Employment History
`
`From: 1991,
`2008-
`Present Mountain View, CA
`Position: 2008-Present: Industry Consultant and Expert Witness
`
`Blanchard Associates specializes in working with both
`start-ups and established companies in the development of
`new products as well as intellectual property. His projects
`have included the development of improved low voltage
`and high voltage MOS-gated devices and the development
`of printable electronics such as LEDs and discrete
`transistors. This work has included the identification of
`patentable material and work to protect this material. He is
`also an Exclusive Expert for SVEWG.
`
`
`
`From: 1998
`Silicon Valley Expert Witness Group, Inc.
`Mountain View, CA
`To:
`2007
`
`Position: Exclusive Expert and Consultant
`
`
`Silicon Valley Expert Witness Group, Inc. (SVEWG) is a
`high technology, “Silicon Valley” consulting company
`specializing in expert witness litigation support and
`
`To:
`
`
`
`
`
`1
`
`XLNX-2007
`
`

`

`Blanchard Curriculum Vitae
`IPR2012-00023
`
`technology consulting. SVEWG has an extensive roster of
`world-class technology experts used in the defense and
`promotion of intellectual property rights and other
`litigation disputes. SVEWG Principals offer extensive in-
`house technology, legal and business expertise and have
`direct access to senior litigation and technology
`consultants worldwide.
`
`
`From: 1991
`
`To:
`
`
`
`Failure Analysis Associates, Inc. (Now named
`“Exponent”)
`Menlo Park, CA
`1998
`Position: Principal Engineer & Division Manager
`
`Responsible for the Electrical/Electronic Division of
`Failure Analysis Associates providing consulting
`services to the electrical and electronics industry.
`Specific duties include:
` Semiconductor devices. Failure analysis and reverse
`engineering of solid-state electronic components and
`circuits. Semiconductor processing and
`semiconductor process equipment. Semiconductor
`manufacturing and process control.
` Failure analysis of electric and electronic systems,
`subsystems, and components, including causes of
`electrical fires
` Reliability modeling and lifetime prediction of
`electrical and electronic systems and subsystems
` Automotive electronics. Design of discrete devices
`and integrated circuits
` Power Electronics. Power MOS and Smart Power
`Technologies
`
`
`From: 1987
`IXYS Corporation
` San Jose, CA
`To:
`1991
`
`Position: Senior Vice President
`
`
`Responsible for the development of IC products.
`Established an in-house CAD capability. Recruited an
`IC design team and coordinated the definition and
`development of IXYS ICs. Identified, qualified and
`monitored the IC foundries that manufactured these
`circuits. Set up testing capability at IXYS. Coordinated
`
`
`
`2
`
`XLNX-2007
`
`

`

`Blanchard Curriculum Vitae
`IPR2012-00023
`
`assembly on IC’s. Worked on various MOSFET and
`IGBT device, test, and assembly problems.
`
`
`From: 1982
`Siliconix, Inc.
` Santa Clara, CA
`To:
`1987
`
`Position: Vice President, Engineering
`
`
`Other titles held at Siliconix, Inc. were Engineering
`Manager (1982-1983) and Director (1983-1984).
`Responsible for the development of advanced process
`technology and the design of both discrete devices
`(JFETs, lateral and vertical DMOS transistors) and
`integrated circuits (low and high voltage CMOS,
`D/CMOS and bipolar-JFET). Personally responsible for
`many key innovations and inventions in power MOS and
`D/CMOS IC technology and their assembly and test
`requirements. He submitted approximately 20 patent
`disclosures while employed at Siliconix, Inc. He holds
`the two key “trench FET” patents, of which he is the sole
`inventor.
`
`
`From: 1976
`Supertex, Inc.
` Sunnyvale, CA
`To:
`1982
`
`Position: Founder and Vice President, MOS Power Products
`
`
`Responsible for investigation of new semiconductor
`devices and new technologies. In charge of Power MOS
`device research, design and development. His work lead
`to the design and development of both the discrete power
`MOS device family and the high voltage IC (HVIC)
`family sold by Supertex, Inc. Responsible for an in-
`house assembly area as well as engineering aspects of
`power MOS and HVIC testing.
`
`
`From: 1976
`Cognition, Inc.
` Mountain View, CA
`To:
`1978
`
`Position: Founder and Consulting Engineer
`
`
`Responsible for developing the process technology for
`fabricating monolithic silicon pressure sensors. A process
`line was established for the manufacture of piezoresistive
`pressure sensors, including the precision etching of thin
`silicon diaphragms.
`
`
`
`3
`
`XLNX-2007
`
`

`

`Blanchard Curriculum Vitae
`IPR2012-00023
`
`
`From: 1974
`Foothill College
` Los Altos Hills, CA
`To:
`1978
`
`Position: Associate Professor, Assistant Division Chairman,
`Engineering & Technology Division
`Accomplishments included developing the curriculum
`for the Semiconductor Technology Program, and
`establishing a small processing facility for teaching
`students the fundamentals of semiconductor technology.
`Supervised approximately 60 instructors in the evening
`and off-campus programs.
`
`
`
`
`
`
`From: 1974
`To:
`1976
`
`Duties:
`
`Independent Consultant
` Los Altos Hills, CA
`Consultant to the semiconductor industry, including
`court appointed “Special Master” in the Fairchild
`Semiconductor Corporation v. National Semiconductor
`Corporation Isoplanar patent suit.
`
`
`From: 1970
`Fairchild Semiconductor
`Mountain View, CA
`To:
`1974
`
`Position: Senior Engineer, Department Manager
`
`
`Responsible for the fabrication of the integrated circuits
`in the Polaroid SX-70 camera. Technologies directly
`related to this work include standard bipolar technology,
`bipolar- MOS technology, silicon gate technology and
`flip-chip assembly technology.
`
`8,330,217
`
`8,133,768
`
`
`Patents
`Patent No. Date Issued Title
`8,330,213
`12/11/2012
`Power Semiconductor Devices, Methods, and Structures
`with Embedded Dielectric Layers Containing Permanent
`Charges
`12/11/2012 Devices, Methods, and Systems with MOS-Gated Trench-
`to-Trench Lateral, Current Flow
`03/13/2012 Method of Manufacturing a Light Emitting Photovoltaic or
`Other Electronic Apparatus and System
`Power Semiconductor Device Having a Voltage Sustaining
`Layer with a Terraced Trench Formation of Floating Islands
`Trench Device Structure and Fabrication
`
`8,049,271
`
`11/01/2011
`
`7,989,293
`
`08/02/2011
`
`
`
`4
`
`XLNX-2007
`
`

`

`Blanchard Curriculum Vitae
`IPR2012-00023
`
`11/02/2010
`
`Isolated Vertical Power Device Structure with Both N-
`Doped and P-Doped Trenches
`06/29/2010 High Voltage Power MOSFET Having Low On-Resistance
`06/15/2010 Method for Fabricating a Power Semiconductor Device
`Having a Voltage Sustaining Layer with a Terraced Trench
`Facilitating Formation of Floating Islands
`04/27/2010 Devices, Methods, and Systems with MOS-Gated Trench-
`to-Trench Lateral Current Flow
`Lateral High-Voltage Transistor with Vertically-Extended
`Voltage-Equalized Drift Region
`09/08/2009 Microelectromechanical Systems (MEMS) Device
`Including a Superlattice
`Power Semiconductor Device Having a Voltage Sustaining
`Region that Includes Doped Columns Formed by Terraced
`Trenches
`07/07/2009 High-Voltage Transistor Fabrication with Trench Etching
`Technique
`Low Capacitance Two-Terminal Barrier Controlled TVS
`Diodes
`05/19/2009 Method for Making a Semiconductor Device Including
`Regions of Band-Engineered Semiconductor Superlattice to
`Reduce Device-On Resistance
`Semiconductor Device Including a Memory Cell with a
`Negative Differential Resistance (NDR) Device
`Semiconductor Device Including Regions of Band-
`Engineered Semiconductor Superlattice to Reduce Device-
`On Resistance
`Technique for Forming the Deep Doped Regions in
`Superjunction Devices
`01/06/2009 Oxide-Bypassed Lateral High Voltage Structures and
`Methods
`Isolated Vertical Power Device Structure with Both N-
`Doped and P-Doped Trenches
`Lateral High-Voltage Transistor with Vertically-Extended
`Voltage-Equalized Drift Region
`Integrated Released Beam Layer Structure Fabricated in
`Trenches and Manufacturing Method Thereof
`Semiconductor Having Thick Dielectric Regions
`03/04/2008
`12/04/2007 Method for Fabricating a Power Semiconductor Device
`Having a Voltage Sustaining Layer with a Terraced Trench
`
`7,825,492
`
`7,745,885
`7,736,976
`
`7,705,397
`
`7,704,842
`
`7,586,165
`
`7,586,148
`
`7,557,394
`
`7,544,544
`
`7,535,041
`
`7,531,850
`
`7,531,829
`
`7,504,305
`
`7,473,966
`
`7,442,584
`
`7,411,249
`
`7,397,097
`
`7,339,252
`7,304,347
`
`04/27/2010
`
`09/08/2009
`
`06/09/2009
`
`05/12/2009
`
`05/12/2009
`
`03/17/2009
`
`10/28/2008
`
`08/12/2008
`
`07/08/2008
`
`
`
`5
`
`XLNX-2007
`
`

`

`Blanchard Curriculum Vitae
`IPR2012-00023
`
`7,244,970
`
`7,224,027
`
`7,202,494
`7,199,427
`7,138,289
`
`7,094,621
`
`7,091,552
`
`7,084,455
`
`7,067,376
`7,061,072
`7,023,069
`
`7,019,360
`
`7,015,104
`
`6,992,350
`6,949,432
`
`6,921,938
`
`6,906,529
`
`6,882,573
`6,861,337
`
`6,812,526
`
`07/17/2007
`
`08/22/2006
`
`08/01/2006
`
`Facilitating Formation of Floating Islands
`Low Capacitance Two-Terminal Barrier Controlled TVS
`Diodes
`05/29/2007 High Voltage Power MOSFET Having a Voltage Sustaining
`Region that Includes Doped Columns Formed by Trench
`Etching and Diffusion from Regions of Oppositely Doped
`Polysilicon
`FinFET Including a Superlattice
`04/10/2007
`04/03/2007 DMOS Device with a Programmable Threshold Voltage
`11/21/2006
`Technique for Fabricating Multilayer Color Sensing
`Photodetectors
`Fabrication on Diaphragms and “Floating” Regions of
`Single Crystal Semiconductor for MEMS Devices
`08/15/2006 High Voltage Power MOSFET Having a Voltage Sustaining
`Region that Includes Doped Columns Formed by Trench
`Etching and Ion Implantation
`Power Semiconductor Device Having a Voltage Sustaining
`Region that Includes Terraced Trench with Continuous
`Doped Columns Formed in an Epitaxial Layer
`06/27/2006 High Voltage power MOSFET Having Low On-Resistance
`06/13/2006
`Integrated Circuit Inductors Using Driven Shields
`04/04/2006 Method for Forming Thick Dielectric Regions Using Etched
`Trenches
`03/28/2006 High Voltage Power MOSFET Having a Voltage Sustaining
`Region that Includes Doped Columns Formed by Trench
`Etching Using an Etchant Gas that is also a Doping Source
`Technique for Forming the Deep Doped Columns in
`Superjunction
`01/31/2006 High Voltage Power MOSFET Having Low On-Resistance
`09/27/2005
`Trench DMOS Transistor Structure Having a Low
`Resistance Path to a Drain Contact Located on an Upper
`Surface
`07/26/2005 Double Diffused Field Effect Transistor Having Reduced
`On-Resistance
`06/14/2005 Capacitive Sensor Device With Electrically Configurable
`Pixels
`04/19/2005 DMOS Device with a Programmable Threshold Voltage
`03/01/2005 Method for Using a Surface Geometry for a MOS-Gated
`Device in the Manufacture of Dice Having Different Sizes
`Trench DMOS Transistor Structure Having a Low
`
`03/21/2006
`
`11/02/2004
`
`
`
`6
`
`XLNX-2007
`
`

`

`Blanchard Curriculum Vitae
`IPR2012-00023
`
`11/02/2004
`
`08/17/2004
`
`06/15/2004
`
`Resistance Path to a Drain Contact Located on an Upper
`Surface
`Technique for Fabricating MEMS Devices Having
`Diaphragms of “Floating” Regions of Single Crystal
`Material
`09/21/2004 Method of Making a Power Semiconductor Device
`09/14/2004
`Fabrication of Dielectrically Isolated Regions of Silicon in a
`Substrate
`Symmetric Trench MOSFET Device and Method of Making
`Same
`Photodiode Stacks for Photovoltaic Relays and the Method
`of Manufacturing the Same
`06/15/2004 High Voltage Power MOSFET Having a Voltage Sustaining
`Region that Includes Doped Columns Formed by Trench
`Etching Using an Etchant Gas that is also a Doping Source
`Two Terminal Programmable MOS-Gated Current Source
`05/11/2004
`05/04/2004 Minimum Sized Cellular MOS-Gated Device Geometry
`04/20/2004 MOSFET Device Having Geometry that Permits Frequent
`Body Contact
`Semiconductor Device Having a Schottky Diode
`04/20/2004
`03/30/2004 Double Diffused Field Effect Transistor Having Reduced
`On-Resistance
`Surface Geometry for a MOS-Gated Device that Allows the
`Manufacture of Dice Having Different Sizes
`03/23/2004 Method for Fabricating a High Voltage Power MOSFET
`Having a Voltage Sustaining Region that Includes Doped
`Columns Formed by Rapid Diffusion
`02/10/2004 Method of Forming a High Voltage Power MOSFET
`Having Low On-Resistance
`Power Semiconductor Device Having a Voltage Sustaining
`Region that Includes Doped Columns Formed with a Single
`Ion Implantation Step
`12/09/2003 High Voltage Power MOSFET Having Low On-Resistance
`12/02/2003 High Voltage Power MOSFET Having a Voltage Sustaining
`Region that Includes Doped Columns Formed by Trench
`Etching and Ion Implantation
`11/18/2003 Method for Fabricating a Power Semiconductor Device
`Having a Voltage Sustaining Layer with a Terraced Trench
`Facilitating Formation of Floating Islands
`09/30/2003 High Voltage Power MOSFET Having Low On-Resistance
`
`03/23/2004
`
`02/03/2004
`
`6,812,056
`
`6,794,251
`6,790,745
`
`6,777,745
`
`6,750,523
`
`6,750,104
`
`6,734,495
`6,730,963
`6,724,044
`
`6,724,039
`6,713,351
`
`6,710,414
`
`6,710,400
`
`6,689,662
`
`6,686,244
`
`6,660,571
`6,656,797
`
`6,649,477
`
`6,627,949
`
`
`
`7
`
`XLNX-2007
`
`

`

`Blanchard Curriculum Vitae
`IPR2012-00023
`
`6,624,494
`
`6,621,107
`
`6,593,619
`6,593,174
`
`6,576,516
`
`6,566,201
`
`6,538,279
`6,492,663
`6,479,352
`
`6,472,709
`
`6,468,866
`6,465,304
`
`6,432,775
`
`6,420,764
`
`6,403,427
`
`6,399,961
`
`6,369,426
`
`6,368,918
`
`6,331,794
`6,316,336
`
`09/16/2003
`
`10/29/2002
`
`08/13/2002
`
`09/23/2003 Method for Fabricating a Power Semiconductor Device
`Having a Floating Island Voltage Sustaining Layer
`Trench DMOS Transistor with Embedded Trench Schottky
`Rectifier
`07/15/2003 High Voltage Power MOSFET Having Low On-Resistance
`07/15/2003
`Field Effect Transistor Having Dielectrically Isolated
`Sources and Drains and Method for Making Same
`06/10/2003 High Voltage Power MOSFET Having a Voltage Sustaining
`Region that Includes Doped Columns Formed by Trench
`Etching and Diffusion from Regions of Oppositely Doped
`Polysilicon
`05/20/2003 Method for Fabricating a High Voltage Power MOSFET
`Having a Voltage Sustaining Region that Includes Doped
`Columns Formed by Rapid Diffusion
`03/25/2003 High-Side Switch with Depletion-Mode Device
`12/10/2002 Universal Source Geometry for MOS-Gated Power Devices
`11/12/2002 Method of Fabricating High Voltage Power MOSFET
`Having Low On-Resistance
`Trench DMOS Transistor Structure Having a Low
`Resistance Path to a Drain Contact Located on an Upper
`Surface
`Single Feature Size MOS Technology Power Device
`10/22/2002
`10/15/2002 Method for Fabricating a Power Semiconductor Device
`Having a Floating Island Voltage Sustaining Layer
`Trench DMOS Transistor Structure Having a Low
`Resistance Path to a Drain Contact Located on an Upper
`Surface
`Field Effect Transitor (sic. Transistor) Having Dielectrically
`Isolated Sources and Drains and Methods for Making Same
`Field Effect Transistor Having Dielectrically Isolated
`Sources and Drains and Method for Making Same
`Field Effect Transistor Having Dielectrically Isolated
`Sources and Drains and Method for Making Same
`Transistor with Integrated Photodetector for Conductivity
`Modulation
`04/09/2002 Method of Fabricating Nan (sic. an) Embedded Flash
`EEPROM with a Tunnel Oxide Grown on a Textured
`Substrate
`Phase Leg with Depletion-Mode Device
`12/18/2001
`11/13/2001 Method for Forming Buried Layers with Top-Side Contacts
`
`07/16/2002
`
`06/11/2002
`
`06/04/2002
`
`04/09/2002
`
`
`
`8
`
`XLNX-2007
`
`

`

`Blanchard Curriculum Vitae
`IPR2012-00023
`
`6,291,845
`6,272,050
`
`6,239,752
`6,225,662
`
`6,215,170
`
`6,198,114
`
`6,069,385
`6,064,109
`
`6,046,473
`
`6,011,298
`
`5,985,721
`5,981,998
`5,981,318
`5,960,277
`
`5,897,355
`
`5,869,371
`
`5,856,696
`
`5,821,136
`
`5,801,396
`
`5,798,549
`
`5,773,328
`5,756,386
`
`5,710,443
`
`05/29/2001
`05/01/2001
`
`04/10/2001
`
`03/06/2001
`
`and the Resulting Structure
`Fully-Dielectric-Isolated FET Technology
`09/18/2001
`08/07/2001 Method and Apparatus for Providing an Embedded Flash-
`EEPROM Technology
`Semiconductor Chip Package that is also an Antenna
`Semiconductor Structure with Heavily Doped Buried
`Breakdown Region
`Structure for Single Conductor Acting as Ground and
`Capacitor Plate Electrode Using Reduced Area
`Field Effect Transistor Having Dielectrically Isolated
`Sources and Drains and Method for Making Same
`Trench MOS-Gated Device
`Ballast Resistance for Producing Varied Emitter Current
`Flow Along the Emitter’s Injecting Edge
`Structure and Process for Reducing the On-Resistance of
`MOS-Gated Power Devices
`01/04/2000 High Voltage Termination with Buried Field-Shaping
`Region
`Single Feature Size MOS Technology Power Device
`11/16/1999
`Single Feature Size MOS Technology Power Device
`11/09/1999
`Fully-Dielectric-Isolated FET Technology
`11/09/1999
`09/28/1999 Method of Making a Merged Device with Aligned Trench
`FET and Buried Emitter Patterns
`05/27/1999 Method of Manufacturing Insulated Gate Semiconductor
`Device to Improve Ruggedness
`Structure and Process for Reducing the On-Resistance of
`MOS-gated Power Devices
`Field Effect Transistor Having Dielectrically Isolated
`Sources and Drains
`Inverted Field-Effect Device with Polycrystalline
`Silicon/Germanium Channel
`Inverted Field-Effect Device with Polycrystalline
`09/01/1998
`Silicon/Germanium Channel
`
`08/25/1998 Conductive Layer Overlaid Self-Aligned MOS-Gated
`Semiconductor Devices
`06/30/1998 Method Of Making A Fully-Dielectric-Isolated FET
`05/26/1998 Method of Making Trench MOS-Gated Device with A
`Minimum Number of Masks
`01/20/1998 Merged Device with Aligned Trench FET and Buried
`Emitter Patterns
`
`05/30/2000
`05/16/2000
`
`04/04/2000
`
`02/09/1999
`
`01/05/1999
`
`10/13/1998
`
`
`
`9
`
`XLNX-2007
`
`

`

`Blanchard Curriculum Vitae
`IPR2012-00023
`
`5,708,289
`5,701,023
`
`5,691,555
`
`5,668,025
`
`5,663,079
`
`5,648,670
`
`5,640,037
`5,637,889
`
`5,591,655
`
`5,589,415
`
`5,576,245
`
`5,574,301
`
`5,528,063
`
`5,485,027
`5,298,781
`
`5,237,481
`5,218,228
`
`5,164,325
`
`5,156,989
`5,132,235
`5,034,785
`4,983,535
`4,978,631
`
`07/15/1997
`
`01/07/1997
`
`01/13/1998
`12/23/1997
`
`11/25/1997
`
`Pad Protection Diode Structure
`Insulated Gate Semiconductor Device Typically Having
`Subsurface-Peaked Portion of Body Region for Improved
`Ruggedness
`Integrated Structure Current Sensing Resistor For Power
`Devices Particularly For Overload Self-Protected Power
`MOS Devices
`09/16/1997 Method of Making a FET with Dielectrically Isolated
`Sources and Drains
`09/02/1997 Method of Making Increased Density MOS-Gated
`Semiconductor Devices
`Trench MOS-Gated Device with a Minimum Number of
`Masks
`06/17/1997 Cell with Self-Aligned Contacts
`06/10/1997 Composite Power Transistor Structures Using
`Semiconductor Materials With Different Bandgaps
`Process for Manufacturing a Vertical Switched-Emitter
`Structure with Improved Lateral Isolation
`12/31/1996 Method for Forming a Semiconductor Structure with Self-
`Aligned Contacts
`11/19/1996 Method of Making Vertical Current Flow Field Effect
`Transistor
`11/12/1996 Vertical Switched-Emitter Structure with Improved Lateral
`Isolation
`06/18/1996 Conductive-Overlaid Self-Aligned MOS-Gated
`Semiconductor Devices
`Isolated DMOS IC Technology
`01/16/1996
`03/29/1994 Vertical Current Flow Field Effect Transistor with Thick
`Insulator Over Non-Channel Areas
`Temperature Sensing Device for Use in a Power Transistor
`08/17/1993
`06/08/1993 High Voltage MOS Transistors with Reduced Parasitic
`Current Gain
`11/17/1992 Method of Making a Vertical Current Flow Field Effect
`Transistor
`10/20/1992 Complementary, (sic) Isolated DMOS IC Technology
`07/21/1992 Method for Fabricating a High Voltage MOS Transistor
`07/23/1991
`Planar Vertical Channel DMOS Structure
`01/08/1991 Vertical DMOS Transistor Fabrication Process
`12/18/1990 Current Source with a Process Selectable Temperature
`Coefficient
`
`
`
`10
`
`XLNX-2007
`
`

`

`Blanchard Curriculum Vitae
`IPR2012-00023
`
`4,958,204
`4,956,700
`
`4,952,992
`
`4,929,991
`4,920,388
`4,916,509
`
`4,914,058
`
`4,896,196
`
`4,893,160
`
`4,868,537
`4,851,366
`4,845,051
`4,835,586
`4,827,324
`
`4,824,795
`
`4,816,882
`4,799,100
`
`4,798,810
`4,794,436
`4,791,462
`4,774,196
`4,767,722
`
`4,759,836
`4,707,909
`
`4,682,405
`
`4,402,003
`4,398,339
`4,393,391
`
`09/18/1990
`09/11/1990
`
`Junction Field-Effect Transistor with a Novel Gate
`Integrated Circuit with High Power, Vertical Output
`Transistor Capability
`08/28/1990 Method and Apparatus for Improving the On-Voltage
`Characteristics of a Semiconductor Device
`05/29/1990 Rugged Lateral DMOS Transistor Structure
`04/24/1990
`Power Transistor with Integrated Gate Resistor
`04/10/1990 Method for Obtaining Low Interconnect Resistance on a
`Grooved Surface and the Resulting Structure
`04/03/1990 Grooved DMOS Process with Varying Gate Dielectric
`Thickness
`01/23/1990 Vertical DMOS Power Transistor with an Integral Operating
`Condition Sensor
`the Performance of Trenched
`01/09/1990 Method for Increasing
`Devices and the Resulting Structure
`09/19/1989 Doped SiO2 Resistor and Method of Forming Same
`07/25/1989 Method for Providing Dielectrically Isolated Circuit
`07/04/1989 Buried Gate JFET
`05/30/1989 Dual-Gate High Density FET
`05/02/1989
`Implantation of Ions into an Insulating Layer to Increase
`Planar PN Junction Breakdown Voltage
`04/25/1989 Method for Obtaining Regions of Dielectrically Isolated
`Single Crystal Silicon
`Power MOS Transistor with Equipotential Ring
`03/28/1989
`01/17/1989 Method and Apparatus for Increasing Breakdown of a
`Planar Junction
`01/17/1989 Method for Manufacturing a Power MOS Transistor
`12/27/1988 High Voltage Drifted-Drain MOS Transistor
`12/13/1988 Dense Vertical J-MOS Transistor
`09/27/1988 Method of Bonding Semiconductor Wafers
`08/30/1988 Method for Making Planar Vertical Channel DMOS
`Structures
`Ion Implantation of Thin Film CrSi2 and SiC Resistors
`07/26/1988
`11/24/1987 Manufacture of Trimmable High Value Polycrystalline
`Silicon Resistors
`07/28/1987 Methods for Forming Lateral and Vertical DMOS
`Transistors
`08/30/1983 Composite MOS/Bipolar Power Device
`08/16/1983
`Fabrication Method for High Power MOS Device
`07/12/1983
`Power MOS Transistor With a Plurality of Longitudinal
`
`
`
`11
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`

`

`Blanchard Curriculum Vitae
`IPR2012-00023
`
`4,345,265
`
`4,344,081
`
`4,145,703
`
`Grooves to Increase Channel Conducting Area
`08/17/1982 MOS Power Transistor with Improved High-Voltage
`Capability
`08/10/1982 Combined DMOS and a Vertical Bipolar Transistor Device
`and Fabrication Method Therefor (sic)
`03/20/1979 High Power MOS Device and Fabrication Method Therefor
`(sic)
`
`
`Education
`
`University
`Year
`Stanford University
`1982
`1970 M.I.T.
`1968 M.I.T.
`
`Publications – Books
`
`Blanchard, R. A., Burgess, David, “Wafer Failure Analysis for Yield
`Enhancement,” Accelerated Analysis, 2000.
`
`Degree
`Ph.D., Electrical Engineering
`MSEE
`BSEE
`
`Blanchard, R.A., “Electronic Failure Analysis Handbook,” co-author of three
`chapters, P. L. Martin, ed., McGraw-Hill, 1999.
`
`Blanchard, R.A., Trapp, O., Lopp, L., “Semiconductor Technology Handbook,”
`Portola Valley, California, Technology Associates, 1993.
`
`Blanchard, R.A., “Discrete Semiconductor Switches: Still Improving,” Chapter
`3, Section 6, Modern Power Electronics, B. K. Bose, ed., Piscataway, N.J, IEEE
`Press, 1992.
`
`Blanchard, R.A., “Power Integrated Circuits: Physics, Design, and
`Application,” (Chapter 3 with J. Plummer) McGraw-Hill, 1986.
`
`Blanchard, R.A., Gise, P., “Modern Semiconductor Fabrication Technology,”
`Reston Publishing Company, 1986.
`
`Blanchard, R.A. and others, “MOSPOWER Applications Handbook,” Siliconix,
`Inc., 1984; Sections 1.3, 2.9, 2.9.1, 2.11, 4.2, 5.6, 5.6.2, 7.1.
`
`Blanchard, R.A., Gise, P., “Semiconductor and Integrated Circuit Fabrication
`Techniques,” Reston Publishing Company, 1979.
`
`
`
`12
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`

`Blanchard Curriculum Vitae
`IPR2012-00023
`
`
`Publications - Papers
`
`Blanchard, R.A., Wong, Chuck, “Off-Line Battery Charger Circuit with
`Secondary-Side PWM Control,” HFPC 2000 Proceedings, October 2000.
`
`Blanchard, R. A., Kusko, Alexander, “Electrical Arcing—Its Impact on Power
`Quality,” Power Quality Assurance, May/June 1996.
`
`Blanchard, R. A., Kusko, Alexander, “Standby vs. Online UPS,” Power Quality
`Assurance, March/April 1996.
`
`Blanchard, R. A., Kusko, Alexander, “Power Electronic Equipment Protection,”
`Power Quality Assurance, January/February 1996.
`
`Blanchard, R.A., Li, R., “Quantitative Analysis and Measurements of Computer
`Local Area Network (LAN) Failures,” PCIM/Power Quality/Mass Transit ‘95
`Conference, Long Beach, California, to be presented September 9-15, 1995.
`
`Blanchard, R.A., Medora, N., Kusko, A., “Power Factor Correction ICs - A
`Topological Overview,” Proceedings, High Frequency Power Conversion
`Conference, HFPC ‘95, San Jose, California, May 1995.
`
`Blanchard, R.A., Kusko, A., “Operation of Electrical Loads Supplied from
`Sine-Wave Current Source UPS,” Proceedings, High Frequency Power
`Conversion Conference, San Jose, California, April 1994.
`
`Cogan, A., Maluf, Blanchard, R.A., “A Very Large-Area, High-Power, High-
`Voltage DMOS Transistor,” Electronic Components Conference, May 1987.
`
`Blanchard, R.A., Dawes, W., et al., “Transient Hardened Power FETs,” IEEE
`Transactions on Nuclear Science, Vol. NS-33 (6), December 1986.
`
`Blanchard, R.A., Severns, R., Cogan, A., Fortier, T., “Special Features of
`Power MOSFETs in High-Frequency Switching Circuits,” Proceedings, High
`Frequency Power Conversion Conference, Virginia Beach, Virginia, May 1986.
`
`Blanchard, R.A., Fortier, T., Cogan, A., Harnden, J., “Low-On-Resistance, Low
`Voltage Power MOSFETs for Motor-drive Applications,” Proceedings, Electro
`86 Session 10, Boston, Massachusetts, May 1986.
`
`Blanchard, R.A., “The Use of MOSFETs in High-Dose-Rate Radiation
`Environments,” Proceedings, APEC 86, New Orleans, Louisiana (With R.
`Severns).
`
`
`
`13
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`

`

`Blanchard Curriculum Vitae
`IPR2012-00023
`
`Blanchard, R.A., Thibodeau, P., “Use of Depletion-Mode MOSFETs in
`Synchronous Rectification,” Proceedings of the 1986 Power Electronics
`Specialist Conference, Vancouver, B.C., Canada, 1986.
`
`Blanchard, R.A., Dawes, W., et al., “Power MOSFET Usage in Radiation
`Environments; Circuit Design Techniques and Improved Fabrication Methods,”
`Digest of Papers GOMAC 1986, San Diego, California. Received the
`Meritorious Paper of the Conference Award.
`
`Blanchard, R.A., Williams, “D/CMOS Technology: SMARTPOWER Processes
`that Solve Different Design Problems,” Proceedings of Electro ‘86, Session 13,
`March 15, 1986.
`
`Blanchard, R.A., Cogan, A., “Future Trends in Semiconductor Switching,”
`Proceedings, SATECH 85, Chicago, Illinois, October 1985.
`
`Blanchard, R.A., Thibodeau, P. “The Design of a High Efficiency, Low Voltage
`Power Supply Using MOSFET Synchronous Rectification and Current Mode
`Control,” PESC ‘85 Record, Toulouse, France, June 1985.
`
`Blanchard, R.A., Severns, R., “The Use of MOSFETs in High-Dose-Rate
`Radiation Environments,” Proceedings of APEC, 1986.
`
`Blanchard, R.A., Numann, “SMARTPOWER Technology: Empty Promises or
`Emerging Products?” Powertechniques, July 1985.
`
`Blanchard, R.A., “SMARTPOWER ICs: Process Innovation Produces
`Significant New Circuits,” Electronic Components News, May 1984.
`
`Blanchard, R.A., “The Application of High-Power MOS-Gated Structures,”
`Proceedings, Electro 85, New York, New York, May 1985.
`
`Blanchard, R.A., Buchanan, Tubis, “Power MOS Technology Invades
`Telecom,” Proceedings of Intelec ‘84, October 1984.
`
`Blanchard, R.A., Severns, R., “Practical Synchronous Rectification Using
`MOSFETs,” Proceedings of Powercon 11, 1984.
`
`Blanchard, R.A., “Process Improvements and Innovations Spur New Power
`ICs,” Electronic Engineering Times, September 24, 1984.
`
`Blanchard, R.A., “MOSPOWER Devices and Coming on Strong,” Electronic
`Products, pp 71-76, July 2, 1984.
`
`Alexander, M., Blanchard, R.A., Abramczyk, E., “Depletion-Mode MOSFETs
`Open a Channel into Power Switching,” Electronic Design, June 28, 1984.
`
`Blanchard, R.A., Severns, R., “MOSFETs Schottky Diodes Vie for Low-
`Voltage-Supply Designs,” EDN, June 28, 1984.
`
`
`
`14
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`

`Blanchard Curriculum Vitae
`IPR2012-00023
`
`Blanchard, R. A., “MOSPOWER Devices Boost Power-Supply Performance,”
`Electronic Engineering Times, June 4, 1984.
`
`Blanchard, R.A., Allan, G., “Understanding MOS Power Transistor
`Characteristics Minimizes Incoming Testing Requirements,” Test &
`Measurement World, pp. 78-87, January 1984.
`
`Blanchard, R.A., Severns, R., “Practical Synchronous Rectification Using
`MOSFETs,” Proceedings, Powercon 11, Dallas, Texas, 1984.
`
`Blanchard, R.A., Buchanan, W., Tubis, C., “Power MOS Technology Invades
`Telecom,” Proceedings, Intelec 84, New Orleans, Louisiana, October 1984.
`
`Blanchard, R.A., “Power Control with Integrated CMOS/DMOS Output,”
`Proceedings of Electro 1983, May 1983.
`
`Blanchard, R.A., Berger, P., “Discrete and Integrated MOSPOWER Transistors
`in Power Conversion and Power Control Applications,” Proceedings of PCI,
`Orlando, Florida, November 1983.
`
`Blanchard, R.A., “MOSFETs in Arrays and Integrated Circuits,” Proceedings of
`Electro ‘83, Session 7, April 1983.
`
`Blanchard, R.A., “Status and Emerging Direction of MOS Power Technology,”
`Proceedings of PCI/MOTOR CON ‘83, April 1983.
`
`Blanchard, R.A., Alexander, M., “Use MOSPOWER as Synchronous Rectifiers
`in Switched-Mode Power Supplies,” Powerconversion International, Vol. 9,
`No. 4, pp. 16-26, April 1983.
`
`Blanchard, R.A., “Power Control With Integrated CMOS/DMOS Output,”
`Proceedings, Electro 1983, New York, New York, May 1983.
`
`Blanchard, R.A., Alexander, M., “Use of MOSPOWER as Synchronous
`Rectifiers in Switched-Mode Power Supplies,” Powerconversion International,
`Vol. 9, No. 4, March 1983.
`
`Blanchard, R.A., Severns, R., “Designing Switched-Mode Power Converters for
`Very Low Temperature Operation,” Proceedings, Powercon 10, San Diego,
`California, March 1983.
`
`Blanchard, R.A., Harnden, J., “MOSFETs Control More Power in the Same-
`Sized Package,” Electronic Design, pp 107-114, December 9, 1982.
`
`Blanchard, R.A., Oxner, “Logic-Compatible MOSFETs Simplify High-Power
`Interfacing,” EDN, pp 105-109, November 24, 1982.
`
`Blanchard, R.A., “Bipolar and MOS Transistors: Emerging Partners for the
`1980’s,” Proceedings, Intelec 1982, Washington, D.C., October 1982.
`
`
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`

`Blanchard Curriculum Vitae
`IPR2012-00023
`
`Blanchard, R.A., “The Use of MOS Power Transistors in Hybrid Circuits,” The
`International Journal for Hybrid Microelectronics, Vol. 5(2), pp. 130-137,
`November, 1982.
`
`Blanchard, P.A., “A New High-Power MOS Transistor for Very High Current,
`High Voltage Switching Applications,” Proceedings of Powercon 8, 1981.
`
`Blanchard, R.A., “VMOS Power Transistors in Automotive Systems - An
`Update,” International Automotive Engineering Congress and Exposition,
`Detroit, Michigan, February 1981.
`
`Blanchard, R.A., Glogolja, M., Baker, R., White, K., “A New High-Power
`MOS Transistor for Very High Current, High Voltage Switching Applications,”
`Proceedings, Powercon 8, Dallas, Texas, 1981.
`
`Blanchard, R.A., “Power MOS transistors: Structure and Performance,”
`Powerconversion International, March/April 1980.
`
`Blanchard, R.A., “The VMOS Power Device - A Direct Interface between
`Microprocessors and Electromechanical Actuators,” International Automotive
`Engineering Congress and Exposition, Detroit, Michigan, March 1977.
`
`Horiuchi, S., Blanchard, R.A., “Boron Diffusion in Polycrystalline Silicon
`Layers,” Solid-State Electronics, Vol. 18, pp. 529-532, 1974.
`
`Blanchard, R.A., Lane, R., Gray, P., Stafford, K., “A Completely Monolithic
`Sample/Hold Amplifier Using Compatible Bipolar and Silicon-Gate FET
`Devices,” IEEE Journal of Solid-State Circuits, Vol. SC-9 (6), December 1974.
`
`Blanchard, R.A., “High Voltage Simultaneous Diffusion Silicon-Gate CMOS,”
`IEEE J.S.S.C., SC-9, No. 3, pp. 103-110, June 1974.
`
`Professional Associations and Achievements
`
` 
`
` Senior Member, Institute of Electrical and Electronics Engineers
` Member, Electronic Device Failure Analysis Society
` Member, International Microelectronics & Packaging Society
`