Filed on behalf of Intellectual Ventures Management, LLC
`By:
`Michael D. Specht
`Robert G. Sterne
`
`Sterne, Kessler, Goldstein & Fox PLLC
`1100 New York Avenue, NW
`
`Washington, DC. 20005
`Tel: (202) 371-2600
`Fax: (202) 371-2540
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL
`
`AND APPEAL BOARD
`
`
`PETITION FOR INTER PAR TES REVIEW
`
`OF US. PATENT NO. 7,566,960
`
`

`

`Inter partes review under 35 U.S.C. § 311 and 37 C.F.R. § 42.101 of United
`
`States Patent No. 7,566,960 to Conn, titled “Interposing Structure” (hereinafter
`
`“the ‘960 Patent)” is hereby requested. The ‘960 Patent is provided as IVM 1001.
`
`The petition for inter partes review is brought on behalf of Intellectual Ventures
`
`Management, LLC (also
`
`referred
`
`to
`
`herein
`
`as
`
`“Intellectual Ventures
`
`Management”).
`
`1.
`
`Grounds for Standéng (37 C.F.R. § 42.104(a))
`
`It is certified by the undersigned and the Petitioner, Intellectual Ventures
`
`Management, that the ‘960 Patent is available for review. The ‘960 Patent issued
`
`on July 28, 2009, more than nine months before the filing date of the present
`
`petition and is not currently involved in a post grant review proceeding.
`
`It is certified by the Petitioner, Intellectual Ventures Management, that the
`
`Petitioner is not estopped from requesting an inter partes review challenging
`
`claims 1—13 of the ‘960 Patent on the grounds identified in the petition.
`
`II.
`
`Identification of Challenge (37 C.F.R. § 42.104(b))
`
`A.
`
`Claim Construction
`
`The terms in claims
`
`1—8 are to be given their broadest
`
`reasonable
`
`interpretation, as understood by one of ordinary skill in the art and consistent with
`
`the disclosure.
`
`Independent claim 9 recites “means for electrically coupling a first micro-
`
`bump in a first position in the array of micro-bumps to a first landing pad disposed
`
`-2-
`
`

`

`opposite the first position and to a second landing pad located in a different
`
`position in the array of landing pads,” which is presumed to invoke interpretation
`
`of this limitation under 35 U.S.C. § 112(6). The function associated with the
`
`“means for” limitation of claim 9 is the “electrically coupling [of] a first micro-
`
`bump” to the recited “first landing pad” and “second landing pad.” As properly
`
`construed, the corresponding structure for this claim limitation (as described in the
`
`specification of the ‘960 Patent and equivalents thereof) refers to caposer 1082 in
`
`FIG. 24 of the ‘960 Patent.
`
`With respect to FIG. 24, the specification of the ‘960 Patent discloses:
`
`In addition to illustrating a via caposer having a bypass capacitor,
`FIG. 24 illustrates a via caposer that redistributes signals. FIG. 24
`shows a fifth landing pad 1103 on first surface 1086 of caposer 1082,
`a fifth micro-bump 1105 on a pad on second surface 1087 of caposer
`
`1082, and a third conductive layer 1106 within caposer 1082. Fifth
`landing pad 1103 is coupled to third conductive layer 1106 by a
`via 1107. Via 1107 is also coupled to a pad 1164 on second surface
`1037.
`13: Via 1108 couples third conductive layer 1106 to fifth
`micro-bump 1105 through the pad on second surface 1087. Third
`conductive layer 1106 comprises a conductive trace that provides
`a portion of a conductive path between fifth landing pad 1103 and
`fifth micro-bump 1105. the ‘960 Patent, 18:47-59, emphasis added.
`
`The micro-bump disposed on landing pad 1103 in caposer 1082 discloses the
`
`recited “first micro—bump” of claim 9. A first landing pad on package 1084 that
`
`corresponds to pad 1104 discloses the recited “first landing pad located opposite to
`
`the first position” of claim 9. Further, a second landing pad on package 1084 that
`
`corresponds to fifth micro—bump 1105 discloses the recited “second landing pad”
`
`-3-
`
`

`

`of claim 9. As clearly illustrated in FIG. 24 of the ‘960 Patent, the micro-bump
`
`disposed on landing pad 1103 electrically couples the first landing pad on package
`
`1084 to the second landing pad on package 1084 via conductive layer 1106. Thus,
`
`caposer 1082 in FIG. 24 of the ‘960 Patent is the corresponding structure for the
`
`“means for” limitation of claim 9. The remaining limitations of claim 9 are to be
`
`given their broadest reasonable interpretation, as understood by one of ordinary
`
`skill in the art and consistent with the disclosure.
`
`Claims 10-12 depend from claim 9. Claims 10-12 are to be given their
`
`broadest reasonable interpretation, as understood by one of ordinary skill in the art
`
`and consistent with the disclosure.
`
`B.
`
`Background
`
`The ‘960 Patent relates to an interposer disposed inside an integrated circuit
`
`(IC) package between a die and the IC package, where the interposer provides
`
`bypass capacitance and signal redistribution. See the ‘960 Patent, 125-9. The ‘960
`
`Patent was filed on October 31, 2003 as Appl. No. 10/698,704 (“the ‘704
`
`application”). The ‘704 application was filed with 16 total claims, in which claims
`
`1, 9, and 12 were independent claims.
`
`In response to Requirements for
`
`Restriction/Election of March 17, 2005 and June 16, 2005, Patent Owner elected
`
`claims 1-8 and 12-16.
`
`

`

`After Patent Owner’s election of claims 1-8 and 12-16, a summary of the
`
`prosecution history is as follows:
`
`Non-Final Office Action issued on September 29, 2005;
`Response to Non-Final Office Action filed on January 3, 2006;
`Final Office Action issued on April 21, 2006;
`Response to Final Office Action filed on June 19, 2006;
`Advisory Action issued on June 28, 2006;
`Request for Continued Examination filed on July 12, 2006;
`Non-Final Office Action issued on July 27, 2012;
`Response to Non-Final Office Action filed on October 10, 2006;
`Non-Final Office Action issued on January 8, 2007;
`Response to Non-Final Office Action filed on April 9, 2007;
`Non-Final Office Action issued on September 20, 2007;
`Response to Non-Final Office Action filed on December 12, 2007;
`Non—Final Office Action issued on March 13, 2008;
`
`Qflflflflflflflflifilfl
`
`Response to Non—Final Office Action filed on June 3, 2008;
`Non-Final Office Action issued on September 2, 2008;
`Response to Non-Final Office Action filed on November 25, 2008;
`and,
`
`Notice of Allowance issued on March 24, 2009.
`
`On page 2 of the Notice of Allowance of March 24, 2009, with respect to the
`
`reason for allowance, the Examiner stated:
`
`As to independent claims 1 and 12, the prior art of record fails to
`show the combination recited in any of the claims.
`In particular, the
`prior art of record fails to show or collectively teach the interposing
`structure electrically couples a first micro-bump in a first position of
`the array of micro-bumps to a first landing pad located opposite the
`first position and to a second landing pad in the array of landing pads.
`Applicant’s arguments provide reason for allowance.
`
`Claims 1-8 and 12—16 were renumbered as claims 1-8 and 9-13, respectively. As
`
`will be discussed in detail below,
`
`the above-noted features of renumbered
`
`

`

`independent claims 1 and 9 were well-known concepts in the prior art prior to the
`
`filing date of the ‘960 Patent.
`
`C.
`
`Ground 1: Claims 1, 2, 9 and 10 are anticipated under 35 U.S.C.
`§ 102(a) by Chakravorty ‘419
`
`US. Patent 6,611,419 to Chakravorty,
`
`titled “Electronic Assembly
`
`Comprising Substrate with Embedded Capacitors,” issued on August 26, 2003,
`
`prior to the effective filing date of the ‘960 Patent (hereinafter “Chakravorty
`
`‘419”). IVM 1003. Thus, Chakravorty ‘419 qualifies as prior art under at least 35
`
`U.S.C. § 102(a).
`
`Chakravorty ‘419 discloses each and every limitation of independent claims
`
`1 and 9 and dependent claims 2 and 10.
` —___.r_-=-:.—.
`
` Claim 1 Chakravorty ‘419
`
`[LP] An assembly,
`Chakravorty ‘419 is directed to “an electronic
`comprising:
`assembly that includes a substrate having one or
`more embedded capacitors to reduce switching noise
`in a high speed integrated circuit.” Chakravorty ‘419,
`
`1:14-16. See IVM 1002, 11 22.
`In reference to FIG. 3 (reproduced below with
`annotations), Chakravorty ‘419 discloses:
`
`[1.1] an integrated
`circuit die having an
`I array of micro-bumps
`disposed on a surface of
`the integrated circuit die
`in a first pattern;
`
`_..-=n_..
`
`
`
`
`coupled to signal lines of IC die 300, lead 302
`
`is coupled to Vcc, and lead 303 is coupled to
`.
`
`-6-
`
`
`
`
`The internal structure of substrate 310 can be
`similar
`to that described above
`regarding
`substrate 210 (FIG. 2). Thus, substrate 310 has
`a plurality of lands 311-313 on one surface
`thereof
`that can be
`coupled to leads or
`conductive areas 301-303, respectively, on IC
`die 300 via solder balls 308. Leads 301 are
`
`i
`3'
`
`
`
`

`

`
`
`
`
`Vss. Chakravorty ‘419, 523-16.—
`
`First Micro-Bump
`
`— 3i”
`’9
`I.
`J
`l)
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Second Landing Pad
`
`FIG. 3 of Chakravorty ‘419 (Annotated)
`
`IC die 300 has an array of solder balls 308 that are
`disposed on a surface of IC die 300 in the recited
`“first pattern.” For example, with respect to the
`portion of FIG. 3 within the dotted lines, solder balls
`308 are disposed in an array configuration (e.g., 1 X
`N array, where N is an integer greater than 1) on a
`
`surfa_ce of IC die 300. See IVM 1002, fl 23.
`
`
`
` _-_.
`
` Chakravorty ‘419 discloses claim portion [1.2a]. For
`
`
`[1.2a] an integrated
`circuit package having an
`array of landing pads
`disposed on an inside
`surface of the integrated
`circuit package in a
`second pattern and [1.2b]
`an array of solder balls
`disposed on an outside
`surface of the integrated
`circuit package, [1.2c]
`wherein the first pattern
`and the second pattern are
`substantially identical
`patterns; and
`
`
`
`example, in reference to FIG. 3 (reproduced above
`with annotations), Chakravorty ‘419 discloses that
`“[s]ubstrate 320 can be similar to substrate 310,
`optionally having an IC die (not shown) on the
`opposite surface thereof, or it can be a printed circuit
`board (PCB) or other type of substrate. Leads or
`conductive areas 334, 339, and 319 of substrate 320
`can be coupled to corresponding lands 331, 332, and
`317 of substrate 310 via solder balls 338.”
`
`Chakravorty “419, 4163—522. Leads or conductive
`areas 319, 334, and 339 in above-annotated FIG. 3 of
`Chakravorty ‘419 are disposed on an inside surface
`of substrate 320 (i.e., integrated circuit package) in
`the recited “second pattern.” For example, with
`respect to the portion of annotated FIG. 3 within the
`dotted lines, leads or conductive areas 319 and 339
`
`are disposed in an array configuration (3g: 1 x N
`
`

`

`
`
`
`array, where N is an integer greater than 1) on an
`inside surface of substrate 320. See IVM 1002, r| 24.
`
`
`
`
`
`
`
`Chakravorty ‘419 also discloses claim portion [12b].
`For example, in reference to FIG. 3, Chakravorty
`‘419 discloses that “|s|ubstrate 320 can be similar
`to substrate 310, optionally having an IC die (not
`shown) OE the opposite surface thereof, or it can be
`a printed circuit board (PCB) or other type of
`substrate.” Chakravorty ‘419, 4:63—66, emphasis
`added. IC die 300 is disposed on substrate 310 via
`solder balls 308 arranged in an array configuration
`(6g, 1 X N array, where N is an integer greater than
`1). Similarly, another IC die (not shown in FIG. 3)
`can be disposed on an outside surface of substrate
`320 Via solder balls in an array configuration (e.g., l
`x N array, where N is an integer greater than 1). For
`example, similar to solder balls 308 within the dotted
`lines (see annotated FIG. 3 of Chakravorty ‘419
`above), the solder balls on the outside surface of
`substrate 320 can be arranged in a l x N array, where
`N is an integer greater than 1. See IVM 1002, f 25.
`
`To the extent that the Office believes that
`
`Chakravorty ‘419 does not explicitly disclose the
`recited “array of solder balls on an outside surface of
`the integrated circuit package,” it would have been
`obvious to dispose solder balls on an outside surface
`of substrate 320 since substrate 320 can be of any
`type. See Chakravorty ‘419, 5:37. Other types of
`substrates that were well-known at the time of filing
`of Chakravorty ‘419 included, among others, Ball
`Grid Arrays (BGAs). See IVM 1002, 11 26.
`
`Chakravorty ‘419 discloses claim portion [1.2c]. In
`annotated FIG. 3 of Chakravorty ‘419 above, solder
`balls 308 are aligned with leads or conductive areas
`319 and 339. Thus, the pattern of solder balls 308
`and the pattern of leads or conductive areas 319 and
`
`“_3_39 are substantially identical patterns. See IVM
`
`-8-
`
`

`

`
`
`_
`
`Chakravorty ‘419 discloses claimportions [1.3a] and l
`
`“':—'
`
`1002, I127
`[1.3a] an interposing
`structure disposed inside
`the integrated circuit
`package between the
`integrated circuit die and
`the inside surface of the
`
`l
`
`[1 .3b]. For example, 1n reference to the above-
`annotated FIG. 3 of Chakravorty ‘419, substrate 310
`discloses the recited “interposing structure disposed
`inside the integrated circuit package between the
`integrated circuit die and the inside surface of the
`integrated circuit package.” In annotated FIG. 3 of
`integrated circuit
`Chakravorty ‘419 above, a solder ball 308 in a first
`package, [1.3b] the
`position in the array of solder balls (e.g., l x N array,
`interposer electrically
`where N is an integer greater than 1) is electrically
`coupling a first micro-
`coupled by a capacitive plate 329 (e.g., conductive
`bump in a first position in
`material) to a first lead or conductive area located
`the array of micro-bumps
`opposite to the first position and to a second lead or
`to a first landing pad
`conductive area 339 in the array of leads or
`located opposite to the
`conductive areas (e.g., l x N array, where N is an
`first position and to a
`integer greater than 1). See IVM 1002, 11"] 28-29.
`second landing pad in the
`
`—n_
` array of landing pads.
`,_ __
`Chakravorty ‘419
`The assembly of claim 1, Claim 1 is disclosed in Chakravorty ‘419. See
`[2.1] wherein a line
`Anticipation Rejection of Claim 1 Based on
`extending through the
`Chakravorty ‘419 above.
`first micro-bump in a
`direction orthogonal to
`the surface of the
`
` Chakravorty ‘419 discloses claim portion [2.1]. For
` Claim=2 a _
`l
`
`integrated circuit does not
`extend through the
`second landing pad of the
`integrated circuit
`package.
`
`example, FIG. 3 of Chakravorty (reproduced below
`with annotations) illustrates:
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
` Second Landing Pad
`
`First Landing Pad
`
`FIG. 3 of Chakravorty ‘419 (Annotated)
`
`As depicted above, a line extending th_r_ough solder
`
`-9-
`
`

`

`
`ballfi in a direction oflgonal to the surface of IC
`die 300 does not extend through the second lead or
`conductive area 339 of substrate 320. See IVM 1002,
`
`1.32;
`
`.
`Claim 9
`__
`Chakravorty ‘419
`[9.P] An assembly,
`Claim portion [9.P] is disclosed in Chakravorty ‘419.
`comprising:
`See Anticipation Rejection of Claim Portion [1.P]
`
`_ "_B_ased_orl C_hakravorty ‘419__abov_e.
`[9.1] an integrated
`Claim portion [9.1]13 disclosed1n Chakravorty ‘4l9.
`See Anticipation Rejection of Claim Portion [1.1]
`circuit die having an
`Based on Chakravorty ‘419 above.
`array of micro-bumps
`disposed on a surface of
`the integrated circuit die
`
`
`in a first pattern;
`[9.2a] an integrated
`circuit package having an
`array of landing pads
`disposed on an inside
`surface of the integrated
`circuit package in a
`second pattern and [9.2b]
`an array of solder balls
`disposed on an outside
`surface of the integrated
`circuit package, [9.2c]
`wherein the first pattern
`and the second pattern are
`substantially identical
`atterns; and
`[9.3a] means for
`l
`. electrically coupling a
`first micro-bump in a first
`position in the array of
`micro-bumps to a first
`landing pad disposed
`opposite the first position
`and to a second landing
`l pad located in a different
`position in the array_ofm
`
`
` .I—a__..._.
`
`Claim portions [9.2a], [9.2b], and [9.2c] are
`disclosed in Chakravorty ‘419. See Anticipation
`Rejection of Claim Portions [1.2a], [1.2b], and [1.2c]
`Based on Chakravorty ‘419 above.
`
`lI
`
`
`
`
`
`Chakravorty ‘419 discloses claim portion [9.3a]. For
`example, in annotated FIG. 3 of Chakravorty ‘419
`above (see claim 1), a solder ball 308 in a first
`position in the array of solder bumps (e.g., l X N
`array, where N is an integer greater than 1) is
`electrically coupled by capacitive plate 329 (e.g.,
`conductive material) to a first lead or conductive area
`disposed opposite the first position and to a second
`lead or conductive area 339 located in a different
`
`position i2 the array of leads or conductive areas
`
`-10-
`
`

`

`
`(e.g., l x N array, where N is an integer greater than-
`1).
`
`H
`
`the integrated circuit
` _}_3_ackage.
`-_
`C_h_§kravorty ‘4}9
`Claim 10
`The assembly of claim 9,
`[10.1] wherein the means
`is also for providing a
`bypass current to the
`integrated circuit die.
`
`Further, substrate 310 discloses claim portion [9.3b].
`See IVM 1002, ‘fi‘fi 28-29.
`
`Anticipation Rejection of Claim 9 Based on
`Chakravorty ‘419 above.
`
` Claim 9 is disclosed in Chakravorty ‘419. See
`
`l
`
`
`
`landing pads, [9.3b] the
`means being disposed
`inside the integrated
`circuit package between
`the integrated circuit die
`and the inside surface of
`
`
`
`Chakravorty ‘419 discloses claim portion [10.1]. For .
`example, Chakravorty ‘419 discloses that substrate
`310 includes embedded capacitors 330 coupled to
`Vcc and Vss terminals. See Chakravorty ‘419, 5:20—
`34. Embedded capacitors 330 serve as decoupling or
`bypass capacitors. See Chakravorty ‘419, 8:66-9:9.
`As would be understood by a person of ordinary skill
`in the relevant art, decoupling capacitors are used to
`decouple one portion of an electrical network from
`another portion. A decoupling capacitor acts as local
`energy storage (e.g., storage of charge or current) for
`the portion of the electrical network associated with
`the capacitor. In reference to FIG. 3 of Chakravorty
`‘419, embedded capacitors 330 provide bypass
`
`current to‘IC die 300. See IVM_1002,
`I 31.
`
` —- __
`
`3.
`
`Ground 2: Claim 13 is obvious under 35 U.S.C. § 103 based on
`
`Chakravorty ‘419
`
`As discussed above, Chakravorty ‘419 qualifies as prior art under at least 35
`
`U.S.C.
`
`§ 102(a).
`
`Chakravorty ‘419 discloses each and every limitation of
`
`dependent claim 13.
`
`-11-
`
`

`

` —1
`
`Claim 13
`Chakravor
`
`‘419
`
`
`
`
`
`The assembly of claim 9, Claim 9 is disclosed in Chakravorty ‘419. See
`[13.1] wherein the
`Anticipation Rejection of Claim 9 Based on
`integrated circuit die is an Chakravorty ‘419 above.
`application specific
`integrated circuit (ASIC). Chakravorty ‘419 discloses claim portion [13.1]. For
`example, Chakravorty ‘419 discloses, with respect to
`FIG. 3, that “Idlie 300 and substrates 310 and 320
`can be of any tyfle. In one embodiment, die 300 is a
`processor, substrate 310 is a multilayer ceramic
`substrate, and substrate 320 is a PCB.” Chakravorty
`‘419, 5:37—39, emphasis added. To a person of
`ordinary skill in the relevant art, the substitution of
`die 300 for an ASIC would have been nothing more
`than a “simple substitution of one known element for
`another to obtain predictable results.” MPEP §
`2141.III.(D). ASICs were well—known at the time of
`filing of Chakravorty ‘419, and it would have been
`obvious to implement an ASIC for die 300 of FIG. 3.
`
`S_‘_ee IVM 1002, 1H 33-34.___
`
`
`
`
`
`
`E.
`
`Ground 3: Claims 3-5, 7, 8, and 11 are obvious under 35 U.S.C. §
`103 based on Chakravorty ‘419 and Siniaguine
`
`U,S. Patent No. 6,730,540 to Siniaguine,
`
`titled “Clock Distribution
`
`Networks and Conductive Lines in Semiconductor Integrated Circuits,” was filed
`
`on April 18, 2002, prior to the effective filing date of the ‘960 Patent (hereinafter
`
`“Siniaguine”). IVM 1004. Thus, Siniaguine qualifies as prior art under at least 35
`
`U.S.C.§ 102(e).
`
`Chakravorty ‘419 and Siniaguine disclose each and every limitation of
`
`dependent claims 3—5, 7, 8, and 11.
`
`-12-
`
`

`

`
`
`
`Claim 3
`Chakravorty ‘419 in View of Siniaguine
`_
`j The assembly of claim 2, Claim 2 is disclosed in Chakravorty ‘419. See
`[3.1 (1] wherein the
`Anticipation Rejection of Claim 2 Based on
`surface of the integrated
`Chakravorty ‘4 1 9 above.
`circuit die is a major
`surface of the integrated
`circuit die, and [3.1 b]
`wherein the interposing
`structure has a major
`surface, and wherein the
`
`Claim portions [3.1a] and [3.1b] are disclosed in
`Chakravorty ‘419 and Siniaguine. With respect to
`” claim portion [3.1a], the recited “integrated circuit
`die” and “interposing structure,” IC die 300 and
`substrate 310 in FIG. 3 of Chakravorty ‘419,
`respectively, disclose these limitations. The
`specification, claims, or prosecution history of the
`‘960 patent do not define the recited “major surface”
`of the integrated circuit die or the interposing
`structure. However, IC die 300 has a “major”
`surface with solder balls 308 coupled thereto and
`substrate 310 also has a “major” surface that is
`coupled to solder balls 308.
`
`To a person of ordinary skill in the relevant art, the
`modifications to the major surfaces of IC die 300 and
`substrate 310 of Chakravorty ‘419 to have roughly
`identical surface areas as taught by Siniaguine would
`have been nothing more than “[a]pplying a known
`technique to a known device (method, or product)
`ready for improvement to yield predictable results.”
`MPEP § 2141.III.(D). Here, Siniaguine states that
`the packaging illustrated in FIG. 12 is an exemplary,
`conventional ball grid array (BGA) package. See
`Siniaguine, 7:61-67. Thus, a person of ordinary skill
`
`in the releygnt art would have been motivated to
`
`major surface of the
`integrated circuit die and
`the major surface of the
`interposing structure have
`roughly identical surface
`areas.
`
`
`
`
`
`With respect to claim portion [3. lb], in reference to
`FIG. 12, circuit 310 discloses the recited “integrated
`circuit die” and interposer 320 in FIG. 12 of
`Siniaguine disclose the recited “interposing
`structure.” In FIG. 12 of Siniaguine, the surface of
`circuit 310 and the surface of IC 320 have roughly
`identical surface areas.
`
`-13-
`
`
`
`

`

`
`
` combine the teachings of Siniaguine with
`
`Chakravorty ‘419. See IVM 1002, 1111 36-39.
`
`
`Chakravorty ‘41_9jn View of Siniaguine
`Claim 4
`
`
`
`The assembly of claim 3,
`[4.1] wherein the
`interposing structure
`includes no transistor and
`
`no PN junction.
`
`Siniaguine. See Obviousness Rejection of Claim 3
`Based on Chakravorty ‘419 and Siniaguine above.
`
`Chakravorty ‘419 discloses claim portion [4.1]. For
`example, in reference to FIG. 3, Chakravorty ‘419
`discloses that substrate 310 includes metallized
`
`The assembly of claim 4,
`[5.1 (1] wherein the
`interposing structure
`comprises an array of
`micro-bumps, [5.1 b]
`wherein the array of
`micro-bumps of the
`interposing structure has
`a pattern that is
`substantially identical to
`the second pattern of the
`landing pads on the inside
`surface of the integrated
`circuit package.
`
`Chakravorty ‘419 discloses claim portions [5.1a] and
`[5.1b]. For example, FIG. 3 of Chakravorty ‘419
`(reproduced below with annotations) illustrates:
`
`
`
`
`
`
`power vias and Vss/Vcc capacitive plates (e.g.,
`conductive material) within a ceramic substrate.
`Chakravorty ‘419, 5:3 7—61. As would be understood
`by a person of ordinary skill in the relevant art, these
`materials do not form transistors or PN junctions.
`
`See IVM 1002, T| 40.
`
`_ _Chakrav0r_ty ‘419 in View of Siniaguine
`Claim 5
`Claim 4 is disclosed in Chakravorty ‘419 and
`Siniaguine. See Obviousness Rejection of Claim 4
`Based on Chakravorty ‘419 and Siniaguine above.
`
` I Claim 3 is disclosed in Chakravorty ‘419 and
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`39'
`
`3m"-
`
`-
`
`.'
`
`551
`
`m.
`m
`
`k
`
`319
`
`FIG. 3 of Chakravorty ‘419 (Annotated)
`
`As depicted above, substrate 310 (e.g., interposing
`structure) has an array of solder balls 338 (e.g., 1 X N
`array, where N is an integer greater than 1). The
`array of solder balls 338 has a pattern that is
`
`substantially identical to the pattern of leads or
`
`-14-
`
`

`

`
`conductive areas 319 and 339 on the inside surface
`1
`
`of substrate 3_2_0. See IVM 1002, ‘H 41.
`l _
`. Chakravorty ‘419 in View of Siniaguine
`_
`Claim 7
`The assembly of claim 5, Claim 5 is disclosed in Chakravorty ‘419 and
`[7.1] wherein the
`Siniaguine. See Obviousness Rejection of Claim 5
`interposing structure
`Based on Chakravorty ‘419 and Siniaguine above.
`includes a bypass
`capacitor.
`
`
`
`
`
`
`Claim portion [7.1] is disclosed in Chakravorty ‘419.
`See Anticipation Rejection of Claim Portion [10.1]
`Based on Chakravorty ‘419 above. See IVM 1002, fl
`42.
`
`Chakravortx‘419 in View! of Siniaguine a
`Claim 8
`The assembly of claim 5, Claim 5 is disclosed in Chakravorty ‘419 and
`[8.1a] wherein the first
`Siniaguine. See Obviousness Rejection of Claim 5
`micro—bump is coupled to Based on Chakravorty ‘419 and Siniaguine above.
`the first landing pad at
`least in part by a
`conductor disposed in the
`interposing structure,
`[8.1b] wherein the
`conductor disposed in the
`interposing structure
`extends in a direction
`parallel to the surface of
`the integrated circuit.
`
`Chakravorty ‘419 discloses claim portions [8.1a] and
`[8.1b]. For example, in annotated FIG. 3 of
`Chakravorty ‘419 below, a solder ball 308 is coupled
`to a first lead or conductive area at least in part by a
`capacitive plate 329 (e.g., conductive material).
`Further, capacitive plate 329 is disposed in substrate
`310 and extends in a direction parallel to the surface
`of IC die 300. See IVM 1002, fi 43.
`
`.. First Micro-Bump
`
`
`":5"9
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`
`
`
`
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`
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`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`FIG. 3 of Chakravorty ‘419 (Annotated)_ _
`Chakravorty ‘419 in View of Siniaguine
`Claim 11
`I
`
`The assembly of claim 9,
`J Claim 9 is disclosed in Chakravorty ‘419. See
`
`
`
`-15-
`
`

`

`
`
`Anticipation Rejection-of Claim 9 B_ased on
`Chakravorty ‘419 above.
`
`[11.1a] wherein the
`surface of the integrated
`1 circuit die is a major
`surface of the integrated
`circuit die, and [11.1b]
`|' wherein the means has a
`
`major surface, and
`wherein the major surface
`of the integrated circuit
`die and the major surface
`of the means have
`
`roughly identical surface
`areas.
`
`
`-=-r_
`
`
`Claim portions [11.1a] and [11.1b] are disclosed in
`Chakravorty ‘419 and Siniaguine. See Obviousness
`Rejection of Claim Portions [3.1a] and [3.1b] Based
`on Chakravorty ‘419 and Siniaguine above. See IVM
`1002, W 36—39.
`
`Ground 4: Claims 6 and 12 are obvious under 35 U.S.C. § 103
`based on Chakravorty ‘419, Siniaguine, and Patel
`
`US. Patent No. 6,469,908 to Patel et a1., titled “Dual-Socket Interposer and
`
`Method of Fabrication Therefor,” issued on October 22, 2002, which is over one
`
`year prior to the effective filing date of the ‘960 Patent (hereinafter “Patel”). IVM
`
`1005. Thus, Patel qualifies as prior art under at least 35 U.S.C. § 102(b).
`
`Chakravorty ‘419, Siniaguine, and Patel disclose each and every limitation
`
`I
`
`1__.
`
`of dependent claims 6 and 12.
`
`__ Claim 6 __
`952115564: ”EL—9 in View ofSiniaguine a—nd Patel
`The assembly of claim 5, Claim 5 is disclosed in Chakravorty ‘419 and
`[6.1] wherein the
`Siniaguine. See Obviousness Rejection of Claim 5
`interposing structure
`includes a layer
`comprising epoxy and
`fiberglass.
`
`
`
` Based on Chakravorty ‘419 and Siniaguine above.
`
`-15-
`
`Patel discloses claim portion [6.1]. For example,
`Patel discloses that, with respect to interposer
`substrate 902, “[i]n one embodiment, the substrate is
`an organic substrate, such as an epoxy material. For
`example, standard PC board materials such as FE—4
`epoxy-glass, polymide-glass, benzocyclobutene,
`
`
`

`

`
`TeTlon, other epoxy resins, or the like could be used
`in various embodiments.” Patel, 7:5-9.
`
`
`
`Anticipation Rejection of Claim 9 Based on
`Chakravorty ‘419 above.
`
`thick.
`
`Patel discloses claim portion [12.1]. For example,
`Patel discloses that, with respect to interposer
`substrate 902, “[i]n various embodiments, the
`thickness of interposer substrate 902 is within a
`range of about 10-1000 microns.” Patel, 7:11-13.
`
` Claim 9 is disclosed in Chakravorty ‘419. See
`
`To a person of ordinary skill in the relevant art, the
`modifications to substrate 310 of Chakravorty ‘419
`to have a planar form less than 500 microns thick
`would have been nothing more than “[a]pplying a
`known technique to a known device (method, or
`product) ready for improvement to yield predictable
`results.” MPEP § 2141 .III.(D). Further, based on the
`interposer thickness range disclosed in Patel (e.g.,
`10-1000 microns) it would have been obvious to try
`each of the thicknesses between 10 and 500 microns
`
`To a person of ordinary skill in the relevant art, the
`modification to substrate 310 of Chakravorty ‘419
`(as modified by Siniaguine) to include a layer of
`epoxy and fiberglass would have been “‘obvious to
`tey’ — choosing from a finite number of identified,
`predictable solutions, with a reasonable expectation
`of success.” MPEP § 2141.III.(D). Thus, a person of
`ordinary skill in the relevant art would have been
`motivated to combine the teachings of Patel with
`Chakravorty ‘419 and Siniaguine. See IVM 1002, ‘l|
`44.
`h Chakravorty ‘419 in View of Patel
`Claim 12
`Tie assembly of claim?
`[12.1] wherein the means
`has a planar form and is
`less than 500 microns
`
`
`
`i
`'
`
`{
`
`
`
`to yield a desirable and predictable interposer
`I thickness with a reasonable expectation of success.
`See MPEP § 2141.III.(D). Thus, a person of
`
`ordinary skill inthe relevant art would have been
`
`-17-
`
`

`

`
`
`
`
`
`motivated to combine the teachings of Patel with
`Chakravorty ‘41_9._ See IVM 1002, 11 45.
`
`G.
`
`Ground 5: Claims 1-13 are obvious under 35 U.S.C. § 103 based
`on Chung and Chakravorty ‘362
`
`US. Patent No. 6,680,218 to Chung et a1., titled “Fabrication Method for
`
`Vertical Electronic Circuit Package and System,” was filed on February 21, 2003,
`
`prior to the effective filing date of the ‘960 Patent (hereinafter “Chung”). IVM
`
`1006. US. Patent No. 6,970,362,
`
`titled “Electronic Assemblies and Systems
`
`Comprising Interposer with Embedded Capacitors,” was filed on July 31, 2000,
`
`prior to the effective filing date of the ‘960 Patent (hereinafter “Chakravorty
`
`‘362”). IVM 1007. Thus, both Chung and Chakravorty ‘362 qualify as prior art
`
`under at least 35 U.S.C. § 102(6).
`
`Chung and Chakravorty ‘362 disclose each and every limitation of
`
`independent claims 1 and 9 and dependent claims 2—8, and 10-13.
`
`
` Claim 1 l Chung and Chakravorty ‘362L_ .,
`
`[1.P] An assembly,
`Chung is directed to “[a]n electronic circuit
`comprising:
`package [that] includes a vertical package section
`
`
`
`
`
`package section (306, FIG. 3).” Chung, Abstract.
`
`See IYM 100_2, ‘3 46.
`Chung discloses claim portion [1.1]. For example,
`[1.1] an integrated
`in reference to FIG. 5 (reproduced below), Chung
`circuit die having an array
`discloses that “In a more typical package designed
`of micro-bumps disposed
`for an IC with 40x40 bond pads, 40 conductive
`on a surface of the
`layers would exist in the vertical section 304, and
`integrated circuit die in a
`perhaps 10 outer layers would be dedicated to
`first pattern;
`
`apower and 10 outer layers would be dedicated to
`
`l
`
`
`1
`
`
`
`
`(304,FIG.3)electricallyconnectedtoahorizontal
`
`-18-
`
`

`

`
`
`ground, leaving 20 inner layers that can be
`dedicated to I/O signals.” Chung, 7:43—48.
`
`
`
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`IC 302 has an array of solder bumps or balls that
`are disposed on a surface of IC 302 in the recited
`“first pattern.” For example, with respect to FIG. 5
`above, IC 302 can have a 40x40 array of bond pads
`with a complementary set of bond pads on the top
`surface of vertical section 304 via the array of
`solder bumps or balls. In another example, with
`respect to FIG. 5 above, the array of solder bumps
`or balls are disposed in a l x N array, Where N is an
`
`integer ggater than 1. S_ee IVM 1002, ‘1 47.
`Chung discloses claim portion [1.2a]. For
`example, in reference to FIG. 5:3, Chung discloses
`“[a] set of bond pads on the bottom surface of
`
` ' vertical section 304 are electrically connected to a
`
`
`
`complimentary set of bond pads on the top surface
`of horiézontal section 306 via solder bumps or balls,
`in one embodiment. .
`.
`. The top surface bond pads
`of horizontal section 306 are electrically connected
`to vias 538 and conductive layers 540, 542, 544
`Within horizontal section 306.” Chung, 826-25.
`Horizontal package section 306 (e.g., part of an IC
`package) includes an array of bond pads disposed
`on an inside surface of horizontal package section
`306 in the recited “second pattern.” For example,
`with respect to FIG. 5 of Chung, the array of bond
`pads is disposed in a l x N array, where N is an
`
`integer greater: than_l.
`
`-19-
`
`
`
` [1.2a] an integrated
`
`
`
`
`
`
`integrated circuit package,
`[1.2c] wherein the first
`pattern and the second
`pattern are substantially
`identical patterns; and
`
`
`
`
`
`
`circuit package havin