(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2002/0053728 A1
`
`Isaak et al.
`(43) Pub. Date:
`May 9, 2002
`
`US 20020053728A1
`
`(54) PANEL STACKING 0F BGA DEVICES TO
`FORM THREE-DIMENSIONAL MODULES
`
`(52) us. Cl.
`
`............................................ 257/686; 438/109
`
`(76)
`
`Inventors: Harlan R. Isaak, Costa Mesa, CA
`(US); Andrew C. Ross, Ramona, CA
`(US); Glen E. Roeters, Huntington
`Beach, CA (US)
`
`Correspondence Address:
`STETINA BRUNDA GARRED & BRUCKER
`75 ENTERPRISE, SUITE 250
`ALISO VIEJO, CA 92656 (US)
`
`(21)
`
`Appl. No.:
`
`10/017,553
`
`(22)
`
`Filed:
`
`Dec. 14, 2001
`
`Related US. Application Data
`
`(63) Continuation-in-part of application No. 09/598,343,
`filed on Jun. 21, 2000.
`
`Publication Classification
`
`(51)
`
`Int. C1.7 ............................ H01L 23/02; HOSK 1/00;
`H01R 12/00; H01L 21/50;
`H01L 21/48; H01L 21/44
`
`(57)
`
`ABSTRACT
`
`A chip stack comprising at least one base layer including a
`base substrate having a first conductive pattern disposed
`thereon. The chip stack further comprises at
`least one
`interconnect frame having a second conductive pattern dis-
`posed thereon Which is electrically connected to the first
`conductive pattern of the base layer. Also included in the
`chip stack are at least two integrated circuit chip packages.
`The integrated circuit chip packages may each be electri-
`cally connected to the first conductive pattern of the base
`layer such that one of the integrated circuit chip packages is
`at least partially circumvented by the interconnect frame.
`Alternatively, one of the integrated circuit chip packages
`may be electrically connected to the first conductive pattern,
`with the remaining integrated circuit chip package being
`attached to the base substrate and at least partially circum-
`vented by the interconnect frame such that the circumvented
`integrated circuit chip package and the second conductive
`pattern of the interconnect frame collectively define a com-
`posite footprint for the chip stack. A transposer layer may be
`included as a portion of each chip stack, with the transposer
`layer including a third conductive pattern specifically con-
`figured to provide a CSP-TSOP interface.
`
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`IVM 1009
`IPR of U.S. Pat. No. 7,566, 960
`
`

`

`Patent Application Publication May 9, 2002 Sheet 1 0f 4
`
`US 2002/0053728 A1
`
`
`
`

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`Patent Application Publication May 9, 2002 Sheet 2 0f 4
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`US 2002/0053728 A1
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`Patent Application Publication May 9, 2002 Sheet 3 0f 4
`
`US 2002/0053728 A1
`
`
`
`

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`Patent Application Publication May 9, 2002 Sheet 4 0f 4
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`US 2002/0053728 A1
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`/300
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`316
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`
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`438
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`

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`US 2002/0053728 A1
`
`May 9, 2002
`
`PANEL STACKING OF BGA DEVICES TO FORM
`THREE-DIMENSIONAL MODULES
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`[0001] The present application is a continuation-in-part of
`US. application Ser. No. 09/598,343 entitled PANEL
`STACKING OF BGA DEVICES TO FORM THREE-DI-
`MENSIONAL MODULES filed Jun. 21, 2000.
`
`STATEMENT RE: FEDERALLY SPONSORED
`RESEARCH/DEVELOPMENT
`
`[0002]
`
`(Not Applicable)
`
`BACKGROUND OF THE INVENTION
`
`invention relates generally to chip
`[0003] The present
`stacks, and more particularly to a chip stack having connec-
`tions routed from the bottom to the perimeter thereof to
`allow multiple integrated circuit chips such as BGA devices
`to be quickly, easily and inexpensively vertically intercon-
`nected in a volumetrically efficient manner.
`
`[0004] Multiple techniques are currently employed in the
`prior art to increase memory capacity on a printed circuit
`board. Such techniques include the use of larger memory
`chips, if available, and increasing the size of the circuit
`board for purposes of allowing the same to accommodate
`more memory devices or chips. In another technique, ver-
`tical plug-in boards are used to increase the height of the
`circuit board to allow the same to accommodate additional
`
`memory devices or chips.
`
`[0005] Perhaps one of the most commonly used tech-
`niques to increase memory capacity is the stacking of
`memory devices into a vertical chip stack, sometimes
`referred to as 3D packaging or Z-Stacking. In the Z-Stacking
`process, from two (2) to as many as eight (8) memory
`devices or other integrated circuit (IC) chips are intercon-
`nected in a single component (i.e., chip stack) which is
`mountable to the “footprint” typically used for a single
`package device such as a packaged chip. The Z-Stacking
`process has been found to be volumetrically efficient, with
`packaged chips in TSOP (thin small outline package) or
`LCC (leadless chip carrier) form generally being considered
`to be the easiest to use in relation thereto. Though bare dies
`or chips may also be used in the Z-Stacking process, such
`use tends to make the stacking process more complex and
`not well suited to automation.
`
`In the Z—Stacking process, the IC chips or packaged
`[0006]
`chips must, in addition to being formed into a stack, be
`electrically interconnected to each other in a desired manner.
`There is known in the prior art various different arrange-
`ments and techniques for electrically interconnecting the IC
`chips or packaged chips within a stack. Examples of such
`arrangements and techniques are disclosed in Applicant’s
`US. Pat. No. 4,956,694 entitled INTEGRATED CIRCUIT
`CHIP STACKING issued Sep. 11, 1990, US. Pat. No.
`5,612,570 entitled CHIP STACK AND METHOD OF
`MAKING SAME issued Mar. 18, 1997, and US. Pat. No.
`5,869,353 entitled MODULAR PANEL STACKING PRO-
`CESS issued Feb. 9, 1999.
`
`techniques
`and
`arrangements
`various
`[0007] The
`described in these issued patents and other currently pending
`
`patent applications of Applicant have been found to provide
`chip stacks which are relatively easy and inexpensive to
`manufacture, and are well suited for use in a multitude of
`differing applications. The present invention provides yet a
`further alternative arrangement and technique for forming a
`volumetrically efficient chip stack. In the chip stack of the
`present invention, connections are routed from the bottom of
`the chip stack to the perimeter thereof so that interconnec-
`tions can be made vertically which allows multiple inte-
`grated circuit chips such as BGA, CSP, fine pitch BGA, or
`flip chip devices to be stacked in a manner providing the
`potential for significant increases in the production rate of
`the chip stack and resultant reductions in the cost thereof.
`
`BRIEF SUMMARY OF THE INVENTION
`
`In accordance with the present invention, there is
`[0008]
`provided a chip stack comprising a base layer which
`includes a base substrate having a first conductive pattern
`disposed thereon. The chip stack further comprises at least
`one interconnect frame having a second conductive pattern
`disposed thereon which is electrically connected to the first
`conductive pattern of the base layer. Also included in the
`chip stack is a transposer layer which itself comprises a
`transposer substrate having a third conductive pattern dis-
`posed thereon. The third conductive pattern of the transposer
`substrate is electrically connected to the second conductive
`pattern of the interconnect frame. In addition to the base and
`transposer layers and interconnect frame,
`the chip stack
`comprises at
`least
`two integrated circuit chip packages
`which are electrically connected to respective ones of the
`first and third conductive patterns. The interconnect frame is
`disposed between the base and transposer layers, with one of
`the integrated circuit chip packages being at least partially
`circumvented by the interconnect frame. The integrated
`circuit chip packages may each comprise a CSP device, with
`the third conductive pattern of the transposer layer being
`uniquely sized and configured to provide a TSOP interface
`for the chip stack.
`
`[0009] Further in accordance with the present invention,
`there is provided a chip stack comprising a base layer which
`includes a base substrate having a first conductive pattern
`disposed thereon. In addition to the base layer, the chip stack
`comprises at least one interconnect frame having a second
`conductive pattern disposed thereon which is electrically
`connected to the first conductive pattern of the base layer
`and electrically connectable to another component. In addi-
`tion to the base layer and interconnect frame, the chip stack
`comprises at least two integrated circuit chip packages. One
`of the integrated circuit chip packages is electrically con-
`nected to the first conductive pattern of the base layer, with
`the remaining one of the integrated circuit chip packages
`being attached (as opposed to electrically connected) to an
`opposed side of the base substrate and at least partially
`circumvented by the interconnect frame. Each of the inte-
`grated circuit chip packages includes a plurality of conduc-
`tive contacts, with the second conductive pattern of the
`interconnect frame and the conductive contacts of the inte-
`
`grated circuit chip package circumvented thereby collec-
`tively defining a composite footprint of the chip stack which
`is electrically connectable to another component.
`
`[0010] Still further in accordance with the present inven-
`tion, there is provided a chip stack comprising a base layer
`including a base substrate having a first conductive pattern
`
`

`

`US 2002/0053728 A1
`
`May 9, 2002
`
`disposed thereon. The chip stack further comprises at least
`one interconnect frame having a second conductive pattern
`disposed thereon which is electrically connected to the first
`conductive pattern of the base layer and electrically con-
`nectable to another component. Also included in the chip
`stack are at least two integrated circuit chip packages which
`are each electrically connected to the first conductive pattern
`and disposed on opposed sides of the base substrate. One of
`the integrated circuit chip packages is at
`least partially
`circumvented by the interconnect frame.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`[0011] These, as well as other features of the present
`invention, will become more apparent upon reference to the
`drawings wherein:
`
`[0012] FIG. 1 is a top perspective view of a chip stack
`constructed in accordance with the present invention;
`
`[0013] FIG. 2 is an exploded view of the chip stack shown
`in FIG. 1;
`
`[0014] FIG. 3 is an exploded view of the various compo-
`nents which are stacked upon each other in accordance with
`a preferred method of assembling the chip stack of the
`present invention;
`
`[0015] FIG. 4 is a partial cross-sectional view of the
`components shown in FIG. 3 as stacked upon each other
`prior to a solder refiow step of the present assembly method;
`
`[0016] FIG. 4a is an enlargement of the encircled region
`4a shown in FIG. 4;
`
`[0017] FIG. 5 is partial cross-sectional view similar to
`FIG. 4 illustrating the components shown in FIG. 3 as
`stacked upon each other subsequent to the completion of the
`solder refiow step of the present assembly method;
`
`[0018] FIG. 5a is an enlargement of the encircled region
`5a shown in FIG. 5;
`
`[0019] FIG. 6 is a top perspective view of a chip stack
`constructed in accordance with a second embodiment of the
`
`present invention;
`
`[0020] FIG. 7 is an exploded view of the chip stack shown
`in FIG. 6;
`
`[0021] FIG. 8 is a partial perspective view of the trans-
`poser layer of the chip stack shown in FIG. 7 taken along
`line A-A thereof;
`
`[0022] FIG. 9 is a side-elevational view of a chip stack
`constructed in accordance with a third embodiment of the
`
`present invention; and
`
`[0023] FIG. 10 is a side-elevational view of a chip stack
`constructed in accordance with a fourth embodiment of the
`
`present invention.
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`[0024] Referring now to the drawings wherein the show-
`ings are for purposes of illustrating preferred embodiments
`of the present
`invention only, and not for purposes of
`limiting the same, FIG. 1 perspectively illustrates a chip
`stack 10 assembled in accordance with a first embodiment of
`
`the present invention. The chip stack 10 comprises at least
`
`two identically configured base layers 12. Each of the base
`layers 12 itself comprises a rectangularly configured base
`substrate 14 which defines a generally planar top surface 16,
`a generally planar bottom surface 18, an opposed pair of
`longitudinal peripheral edge segments 20, and an opposed
`pair of lateral peripheral edge segments 22.
`
`[0025] Disposed on the base substrate 14 of each base
`layer 12 is a first conductive pattern which itself preferably
`comprises a first set of base pads 24 and a second set of base
`pads 26 which are each disposed on the top surface 16 of the
`base substrate 14. The base pads 24 of the first set are
`preferably arranged in a generally rectangular pattern or
`array in the central portion of the base substrate 14, with the
`base pads 26 of the second set extending linearly along the
`longitudinal and lateral peripheral edge segments 20, 22 of
`the base substrate 14. The base pads 24 of the first set are
`electrically connected to respective ones of the base pads 26
`of the second set via conductive traces 28. In addition to the
`
`the first
`base pads 24, 26 of the first and second sets,
`conductive pattern of each base layer 12 comprises a third
`set of base pads 30 which is disposed on the bottom surface
`18 of the base substrate 14. The base pads 30 of the third set
`are preferably arranged in an identical pattern to the base
`pads 26 of the second set, and extend linearly along the
`longitudinal and lateral peripheral edge segments 20, 22 of
`the base substrate 14 such that each of the base pads 30 of
`the third set is aligned with and electrically connected to a
`respective one of the base pads 26 of the second set.
`
`[0026] As is best seen in FIGS. 3-5, each of the base pads
`26 of the second set is electrically connected to a respective
`one of the base pads 30 of the third set via a base feed-
`through hole 32. Each base feed-through hole 32 is prefer-
`ably plugged with a conductive material. The conductive
`material is preferably selected from the group consisting of
`nickel, gold, tin, silver epoxy, and combinations thereof. The
`base pads 26, 30 of the second and third sets, as well as the
`base pads 24 of the first set, each preferably have a generally
`circular configuration.
`In this respect, each base feed-
`through hole 32 preferably extends axially between each
`corresponding, coaxially aligned pair of the base pads 26, 30
`of the second and third sets. The base pads 26, 30 of the
`second and third sets are preferably formed upon (i.e.,
`surface plated to) the base substrate 14 subsequent to the
`plugging of the base feed-through holes 32 and are used to
`cover the opposed, open ends thereof. If the base feed-
`through holes 32 were left unplugged, solder coming into
`contact with the base pads 26, 30 of the second and third sets
`would tend to wick into the base feed-through holes 32 upon
`the refiow of the solder (which will be discussed below),
`thus robbing the base pads 26, 30 of solder needed to
`facilitate various electrical connections in the chip stack 10.
`
`In addition to the base layers 12, the chip stack 10
`[0027]
`of the present invention comprises at least one rectangularly
`configured interconnect frame 34. The interconnect frame
`34 defines a generally planar top surface 36, a generally
`planar bottom surface 38, an opposed pair of longitudinal
`side sections 40, and an opposed pair of lateral side sections
`42. Disposed on the interconnect frame 34 is a second
`conductive pattern which itself preferably comprises a first
`set of frame pads 44 disposed on the top surface 36, and a
`second set of frame pads 46 disposed on the bottom surface
`38. The frame pads 44, 46 of the first and second sets are
`preferably arranged in patterns which are identical to each
`
`

`

`US 2002/0053728 A1
`
`May 9, 2002
`
`other, and to the patterns of the second and third sets of base
`pads 26, 30 of each of the base layers 12. In this respect, the
`frame pads 44, 46 of the first and second sets each extend
`linearly along the longitudinal and lateral side sections 40,
`42 of the interconnect frame 34, with each of the frame pads
`44 of the first set being aligned with and electrically con-
`nected to a respective one of the frame pads 46 of the second
`set. As best seen in FIGS. 4(a) and 5(a), similar to the
`electrical connection of the base pads 26, 30 of the second
`and third sets to each other, the electrical connection of each
`of the frame pads 44 of the first set to a respective one of the
`frame pads 46 of the second set is preferably accomplished
`via a frame feed-through hole 48 which is also preferably
`plugged with a conductive material. The conductive material
`is preferably selected from the same group used as the
`conductive material to plug the base feed-through holes 32,
`i.e., nickel, gold, tin, silver epoxy, and combinations thereof.
`Each of the frame feed-through holes 48 preferably extends
`axially between a corresponding, coaxially aligned pair of
`the frame pads 44, 46 of the first and second sets, with the
`plugging of the frame feed-through holes 48 preferably
`occurring prior to the surface plating of the frame pads 44,
`46 of the first and second sets to respective ones of the top
`and bottom surfaces 36, 38 of the interconnect frame 34.
`
`the interconnect
`In the preferred embodiment,
`[0028]
`frame 34 is preferably prepared for use in the chip stack 10
`by forming generally semi-spherically shaped solder bumps
`50 on each of the frame pads 44, 46 of the first and second
`sets. These solder bumps 50 are preferably formed by first
`stenciling solder paste onto the frame pads 44, 46 of the first
`and second sets, and thereafter refiowing the solder paste to
`form the solder bumps 50. The use of a six mil thick stencil
`with an aperture approximately the same size as each of the
`frame pads 44, 46 will facilitate the formation of a solder
`bump 50 approximately six mils high. As indicated above,
`the frame pads 44, 46 of the first and second sets are formed
`(i.e., surface plated) subsequent to the frame feed-through
`holes 48 being plugged with the conductive material. If the
`frame feed-through holes 48 were left unplugged, each
`frame feed-through hole 48 could trap flux or air which
`would blow out the solder during the refiow cycle used to
`form the solder bumps 50 on each corresponding, coaxially
`aligned pair of frame pads 44, 46 of the first and second sets.
`[0029]
`In the chip stack 10, the interconnect frame 34 is
`disposed between the base layers 12, with the second
`conductive pattern of the interconnect frame 34 being elec-
`trically connected to the first conductive pattern of each of
`the base layers 12. More particularly, the frame pads 46 of
`the second set are electrically connected to respective ones
`of the base pads 26 of the second set of one of the base layers
`12 (i.e., the base layer 12 immediately below the intercon-
`nect frame 34 in the chip stack 10), with the frame pads 44
`of the first set being electrically connected to respective ones
`of the base pads 30 of the third set of one of the base layers
`12 (i.e., the base layer 12 immediately above the intercon-
`nect frame 34 in the chip stack 10). Due to the base pads 26,
`30 of the second and third sets and the frame pads 44, 46 of
`the first and second sets all being arranged in identical
`patterns, each coaxially aligned pair of frame pads 44, 46 of
`the first and second sets is itself coaxially aligned with a
`coaxially aligned set of base pads 26, 30 of the second and
`third sets of each of the adjacent base layers 12. The
`electrical connection of the second conductive pattern of the
`interconnect frame 34 to the first conductive pattern of each
`
`of the adjacent base layers 12 is preferably facilitated via a
`soldering process which will be described in more detail
`below.
`
`[0030] The chip stack 10 of the present invention further
`preferably comprises a transposer layer 52. The transposer
`layer 52 itself comprises a rectangularly configured trans-
`poser substrate 54 which defines a generally planar top
`surface 56, a generally planar bottom surface 58, an opposed
`pair of longitudinal peripheral edge segments 60, and an
`opposed pair of lateral peripheral edge segments 62. Dis-
`posed on the transposer substrate 54 is a third conductive
`pattern. The third conductive pattern comprises a first set of
`transposer pads 64 which are disposed on the top surface 56
`of the transposer substrate 54, and a second set of transposer
`pads 66 which are disposed on the bottom surface 58
`thereof. The transposer pads 64 of the first set are electrically
`connected to respective ones of the transposer pads 66 of the
`second set via conductive traces. The transposer pads 64 of
`the first set are preferably arranged in a pattern which is
`identical to the patterns of the second and third sets of base
`pads 26, 30 and the first and second sets of frame pads 44,
`46. In this respect, the transposer pads 64 of the first set
`extend linearly along the longitudinal and lateral peripheral
`edge segments 60, 62 of the transposer substrate 54. The
`transposer pads 66 of the second set are themselves prefer-
`ably arranged in a generally rectangular pattern or array in
`the central portion of the bottom surface 58 of the transposer
`substrate 54, with the pattern of the transposer pads 66 of the
`second set preferably being identical to the pattern of the
`base pads 24 of the first set of each of the base layers 12.
`
`In the preferred embodiment, the transposer layer
`[0031]
`52 is prepared for use in the chip stack 10 by forming
`generally spherically shaped solder balls 68 on each of the
`transposer pads 66 of the second set. These solder balls 68
`are preferably formed by stencil printing solder paste onto
`each of the transposer pads 66 of the second set, and
`thereafter refiowing the solder paste to form the solder balls
`68. The aperture in the stencil used to form the solder balls
`68 is typically larger than each of the transposer pads 66 and
`thick enough to deposit sufficient solder to form the solder
`balls 68. As seen in FIG. 3, the transposer layer 52 is also
`prepared for use in the chip stack 10 by forming generally
`semi-spherically shaped solder bumps 67 on each of the
`transposer pads 64 of the first set. These solder bumps 67 are
`preferably formed in the same manner previously described
`in relation to the formation of the solder bumps 50 on the
`frame pads 44, 46 of the first and second sets.
`
`In the chip stack 10, the first conductive pattern of
`[0032]
`one of the base layers 12 (i.e., the lowermost base layer 12
`in the chip stack 10) is electrically connected to the third
`conductive pattern of the transposer layer 52. More particu-
`larly, each of the base pads 30 of the third set of the
`lowermost base layer 12 is electrically connected to a
`respective one of the transposer pads 64 of the first set. Due
`to the base pads 30 of the third set and the transposer pads
`64 of the first set being arranged in identical patterns, each
`of the base pads 30 of third set is coaxially alignable with a
`respective one of the transposer pads 64 of the first set, with
`the electrical connection therebetween preferably being
`facilitated via soldering as will be discussed in more detail
`below.
`
`In the present chip stack 10, the base pads 24, 26,
`[0033]
`30 of the first, second and third sets, the conductive traces
`
`

`

`US 2002/0053728 A1
`
`May 9, 2002
`
`28, the frame pads 44, 46 of the first and second sets, and the
`transposer pads 64, 66 of the first and second sets are each
`preferably fabricated from very thin copper having a thick-
`ness in the range of from about five microns to about
`twenty-five microns through the use of conventional etching
`techniques. Advantageously, the use of thin copper for the
`various pads and traces 28 allows for etching line widths and
`spacings down to a pitch of about 4 mils which substantially
`increases the routing density on each of the base layers 12,
`as well as the transposer layer 52. Additionally, the base
`substrate 14, the interconnect frame 34, and the transposer
`substrate 54 are each preferably fabricated from either FR-4,
`polyamide, or some other suitable material which can easily
`be routed. As indicated above, all of the base feed-through
`holes 32 and frame feed-through holes 48 are plugged with
`a conductive material prior to the surface plating procedure
`used to form the base pads 24, 26, 30 of the first, second and
`third sets, and the frame pads 44, 46 of the first and second
`sets. The material used to form each base substrate 14 and/or
`the transposer substrate 54 may be as thin as about 0.010
`inches or may be a thicker multilayer structure.
`
`[0034] The chip stack 10 of the present invention further
`comprises at
`least
`two identically configured integrated
`circuit chips 70 which are electrically connected to respec-
`tive ones of the first conductive patterns of the base layers
`12. Each of the integrated circuit chips 70 preferably com-
`prises a rectangularly configured body 72 defining a gener-
`ally planar top surface 74, a generally planar bottom surface
`76, an opposed pair of longitudinal sides 78, and an opposed
`pair of lateral sides 80. Disposed on the bottom surface 76
`of the body 72 are a plurality of generally spherically shaped
`conductive contacts 82 which are preferably arranged in a
`pattern identical to the patterns of the base pads 24 of the
`first set and the transposer pads 66 of the second set. The
`conductive contacts 82 of each of the integrated circuit chips
`70 are electrically connected to respective ones of the base
`pads 24 of the first set of a respective one of the first
`conductive patterns of the base layers 12. Due to the
`conductive contacts 82 and base pads 24 of each of the first
`sets being arranged in identical patterns,
`the conductive
`contacts 82 of each of the integrated circuit chips 70 are
`coaxially alignable with respective ones of the base pads 24
`of the corresponding first set. In each of the integrated circuit
`chips 70, solder is preferably pre-applied to each of the
`conductive contacts 82 thereof. The electrical connection of
`
`the conductive contacts 82 of each integrated circuit chip 70
`to respective ones of the base pads 24 of the first set of a
`respective one of the first conductive patterns is preferably
`accomplished via soldering in a manner which will be
`discussed in more detail below. Additionally, each of the
`integrated circuit chips 70 is preferably a BGA (ball grid
`array) device, though the same may alternatively comprise
`either a CSP device or a flip chip device.
`
`In the present chip stack 10, a layer 84 of flux/
`[0035]
`underfill is preferably disposed between the bottom surface
`76 of the body 72 of each of the integrated circuit chips 70
`and respective ones of the top surfaces 16 of the base
`substrates 14. Each layer 84 of the flux/underfill is prefer-
`ably spread over the base pads 24 of the first set of a
`respective one of the first conductive patterns of the base
`layers 12. Each layer 84 substantially encapsulates the
`conductive contacts 82 of the corresponding integrated
`
`circuit chip 70 when the same is electrically connected to the
`first conductive pattern of a respective one of the base layers
`12.
`
`[0036] Prior to the attachment of the integrated circuit chip
`70 to a respective base layer 12, a bakeout cycle is required
`to drive out
`the moisture in the base layer 12 and the
`corresponding integrated circuit chip 70. Acycle of approxi-
`mately eight hours at about 125° Celsius is desirable, which
`is followed by storage in a dry nitrogen atmosphere until
`use. The first step in the attachment of the integrated circuit
`chip 70 to the corresponding base layer 12 is the precise
`deposition of the layer 84 of an appropriate flux/underfill
`material over the base pads 24 of the corresponding first set.
`The integrated circuit chip 70 is then placed over the pad
`area, squeezing out the flux/underfill material of the layer 84
`to the longitudinal and lateral sides 78, 80 of the body 72 and
`seating the conductive contacts 82 onto respective ones of
`the base pads 24 of the corresponding first set. If done
`properly, the layer 84 of the flux/underfill material, when
`cured, will have no voids or minimum voids. The base layer
`12 having the integrated circuit chip 70 positioned thereupon
`in the above-described manner is then run through a solder
`refiow cycle with no dwelling time at an intermediate
`temperature of approximately 150° Celsius. A post cure
`cycle to complete the polymerization of the layer 84 of the
`flux/underfill material may be required depending on the
`particular fiux/underfill material used in the layer 84. At this
`juncture, the base layer 12 having the integrated circuit chip
`70 electrically connected thereto may be electrically tested.
`
`the standard approach for the
`In the prior art,
`[0037]
`attachment or electrical connection of the conductive con-
`
`tacts of a BGA device to an attachment or pad site is to first
`flux the pad site or conductive contacts of the BGA device,
`place the BGA device on the pad site in the proper orien-
`tation, refiow the solder pre-applied to the conductive con-
`tacts of the BGA device to facilitate the electrical connection
`
`to the pad site, clean, then underfill and cure. The cleaning
`step typically requires considerable time since the gap under
`the bottom surface of the body of the BGA device is very
`small and very difficult to penetrate with standard cleaning
`methods. Also, the removal of the cleaning fluid (which is
`generally water) requires long bakeout times.
`
`[0038] The underfill of an epoxy between the bottom
`surface of the body of the BGA device and the top surface
`of the substrate having the pad site thereon is a relatively
`easy procedure, but is very slow. If a no-clean flux is used
`for attachment, the residue from the flux typically becomes
`entrapped within the epoxy underfill and may cause corro-
`sion problems. A subsequent solder refiow process to facili-
`tate the attachment of the chip stack to a main printed circuit
`board (PCB) often causes the residue flux to vaporize which
`exerts pressure on the solder joints and could delaminate the
`structure. Most underfill materials become very hard (i.e.,
`greater than ninety shore D) and are cured at a temperature
`of less than about 180° Celsius. The solder is solid at this
`
`temperature and the underfill encases the solder with no
`room for expansion. The solder from the conductive contacts
`of the BGA device expands when molten again, thus exert-
`ing pressure which can delaminate the structure. If the chip
`stack is not subjected to subsequent refiow temperatures
`when completed, there is no problem. However, the chip
`stack must be able to withstand the subsequent refiow
`temperature.
`
`

`

`US 2002/0053728 A1
`
`May 9, 2002
`
`[0039] The fiux/underfill material used for the layer 84
`provides both flux and underfill properties with one formu-
`lation. As the temperature rises during the solder refiow
`process which will be discussed below, the flux character-
`istics of the material aid in the solder process, with extended
`exposure to the peak solder refiow temperature beginning
`the polymerization process of the underfill portion of the
`material. The flux is incorporated into the underfill, thus
`becoming one compatible material which is cured above the
`melting point of solder. Thus,
`there is room within the
`encased solder for expansion at the refiow temperature. No
`cleaning steps are required, though careful dispensing of the
`correct volume and accurate placement of the integrated
`circuit chip 70 upon its corresponding base layer 12 is
`critical.
`
`[0040] The complete chip stack 10 shown in FIG. 1
`includes a transposer layer 52, four base layers 12, three
`interconnect frames 34, and four integrated circuit chips 70.
`The first conductive pattern of the lowermost base layer 12
`is electrically connected to the third conductive pattern of
`the transposer layer 52 in the above-described manner.
`Additionally, each of the interconnect frames 34 is disposed
`or positioned between an adjacent pair of base layers 12,
`with the second conductive pattern of each of the intercon-
`nect frames 34 being electrically connected to the first
`conductive pattern of such adjacent pair of base layers 12 in
`the above-described manner. Since the conductive contacts
`
`82 of each of the integrated circuit chips 70 are electrically
`connected to respective ones of the base pads 24 of the first
`set of respective ones of the first conductive patterns, the
`integrated circuit chips 70 other than for the uppermost
`integrated circuit chip