(12) Umted States Patent
`(10) Patent N0.:
`US 6,469,908 132
`
`Patel et al.
`(45) Date of Patent:
`Oct. 22, 2002
`
`U8006469908B2
`
`(54) DUAL-SOCKET INTERPOSER AND
`METHOD OF FABRICATION THEREFOR
`
`(75)
`
`Inventors: P. R. Patel; Yuan-Liang Li, both of
`Chandler; David G. Figueroa, Mesa;
`Shamala Chickamenahalli, Chandler;
`Huong T. D0, Scottsdale, all OfAZ
`(US)
`
`.
`(73) Assrgnee:
`
`( * ) Notice:
`
`.
`Intel Corporatlon, Santa Clara, CA
`(US)
`Subject to any disclaimer, the term of this
`ginseng 1:5643:11516% (dra agijusted under 35
`'
`'
`'
`y
`y '
`
`.
`(21) Appl. No” 10/076’893
`(22)
`F1led:
`Feb. 14, 2002
`(65)
`Prior Publication Data
`
`4,860,165 A *
`5,627,413 A
`5,669,783 A
`5,712,768 A
`5,847,951 A
`5,864,478 A
`5,919,259 A *
`5,973,928 A
`6,351,392 B1 *
`
`.................. 165/80.4
`8/1989 Cassinelli
`5/1997 Mughir et a1.
`................ 307/86
`9/1997 Inoue et a1. .......... 439/331
`
`
`1/1998 Werther ............... 361/767
`............... 363/147
`12/1998 Brown et a1.
`1/1999 McCutchan et a1.
`........ 363/147
`7/1999 Dahl
`.......................... 307/130
`10/1999 Blasi et a1.
`................. 361/760
`2/2002 Palaniappa ................... 257/48
`
`* cited by examiner
`
`Primary Examiner—David Martin
`Assistant Examiner—Hung Bui
`(74) Attorney, Agent, or Firm—Schwegman, Lundberg,
`Woesnner & Kluth, PA.
`(57)
`ABSTRACT
`.
`.
`.
`.
`An 1nterposer 1ncludes two separate sets of p1ns, and mserts
`into two sockets on a printed circuit board. One set of pins
`supplies power to a step down converter (SDC) mounted on
`the interposer. The second set of pins provide inputs and
`outputs to an 1ntegrated c1rcu1t mounted on the 1nterposer.
`One or more conductrve traces 1n or on the 1nterposer
`electrically connect an output of the SDC to an input of the
`integrated circuit,
`thus supplying regulated power to the
`.
`.
`.
`.
`1ntegrated c1rcu1t
`through the 1nterposer. The SDC and
`integrated circuit can be directly mounted on the interposer,
`or either or both can be mounted on packages that connect
`to the interposer. The SDC and integrated circuit can be flip
`chips or can be connected to the interposer or package using
`wirebonds. The packages can be pinned or connectable by
`solder bumps.
`
`US 2002/0089833 A1 JUL 11: 2002
`.
`.
`Related U'S' Appllcatlon Data
`(62) Division of application No. 09/540,046, filed on Mar. 31,
`2000, now Pat. No. 6,366,467.
`7
`
`Int. Cl.
`(51)
`(52) U.S. Cl.
`
`.................................................. H05K 7/10
`....................... 361/760; 361/803; 361/718;
`361/748' 257/691' 257/718
`’
`361 ’760 736
`h
`eagem/794803728718748 /792’ 799?
`’ 257/691, 728? 363/35 5’9 64
`’
`’
`’
`’
`References Cited
`U.S. PATENT DOCUMENTS
`
`ld f S
`0
`
`58
`
`(
`
`)
`
`F'
`1e
`
`(56)
`
`4,231,154 A
`
`11/1980 Gazdik et a1.
`
`................ 29/840
`
`7 Claims, 7 Drawing Sheets
`
`
`
`IVM 1005
`IPR of U.S. Pat. No. 7, 566, 960
`
`

`

`US. Patent
`
`Oct. 22, 2002
`
`Sheet 1 0f 7
`
`US 6,469,908 B2
`
`
`VOLTAGE
`REGULATOR
`
`MODULE
`
`
`
`FIG.
`
`1
`
`

`

`US. Patent
`
`Oct. 22, 2002
`
`Sheet 2 0f 7
`
`US 6,469,908 B2
`
`
`
`
`alnIZIVAIZIVAIZIa
`VAIZIVA-2_lllll-flIZIVA-z
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`
`
`314 I
`
`\
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`l
`
`313
`
`\ 316
`
`308
`
`310
`
`FIG. 3
`
`306
`
`VIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
`
`VII/IIIIIIIIIIIIIIIIIIIIIIIIIIJ
`VIIIII/IllIIIIIIIIIIIIIIIIIIIIA
`III/IIII/IIIII/IIIIIIIIIIIIIIIIJ
`VIII/[III],III/IIIIIIIIIIIIIIIIA
`
`FIG. 4
`
`

`

`U.S. Patent
`
`Oct. 22, 2002
`
`Sheet 3 0f 7
`
`US 6,469,908 B2
`
`
`
`612
`
`' .
`
`
`
`flIZ-VA-ZIVA-ZIVA-VA-ZIZIVA-M-VA
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`
`614
`
`

`

`US. Patent
`
`Oct. 22, 2002
`
`Sheet 4 0f 7
`
`US 6,469,908 B2
`
` —
`
`- 0-”.fi-0-Q-71-71 708
`
`
`
`
`
`FABRICATE
`INTERPOSER
`
`
`
`SUBSTRATE
`
`804
`
`
`
`ATTACH TWO SETS 0F
`PINS TO INTERPOSER
`
`
`
`PC BOARD
`
`806
`
`ATTACH VRM AND
`INTEGRATED CIRCUIT
`
`808
`
`INSERT DUAL-SOCKET
`INTERPOSER INTO
`
`FIG. 8
`
`

`

`US. Patent
`
`Oct. 22, 2002
`
`Sheet 5 0f 7
`
`US 6,469,908 B2
`
`902
`908
`906
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`
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`1002
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`FIG. 10
`
`

`

`US. Patent
`
`Oct. 22, 2002
`
`Sheet 6 0f 7
`
`US 6,469,908 B2
`
`
`\
`
`
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`FIG. 12
`
`

`

`US. Patent
`
`Oct. 22, 2002
`
`Sheet 7 0f 7
`
`US 6,469,908 B2
`
`1 300
`
`1 304
`
`MICROPROCESSOR
`
`MEMORY
`
`INTERPOSER
`
`POWER
`
`suggfiRfT'gg“
`
`FIG. 13
`
`

`

`US 6,469,908 B2
`
`1
`DUAL-SOCKET INTERPOSER AND
`METHOD OF FABRICATION THEREFOR
`
`This application is a divisional of application U.S. Ser.
`No. 09/540,046, filed on Mar. 31, 2000 now US. Pat. No.
`6,366,467.
`
`5
`
`TECHNICAL FIELD OF THE INVENTION
`
`The present invention relates generally to power delivery
`systems and fabrication methods, and more particularly to
`power delivery systems between a step down converter and
`an integrated circuit, and methods of fabricating the same.
`BACKGROUND OF THE INVENTION
`
`A requirement of most electronic systems is a regulated
`source of direct current (DC) voltage. Whether the DC
`power originates with a battery or has been converted from
`alternating current (AC) power, a voltage regulator circuit is
`usually required to provide a steady DC voltage having the
`correct amplitude. In some cases, however, AC power is
`supplied to the electronic system,
`in which case an AC
`distributor is employed to downconvert and frequency
`enhance the AC power.
`Used in conjunction with an integrated circuit, a regulated
`source of power is typically provided using a step down
`converter (SDC), which can be, for example, a voltage
`regulator module (VRM) or an AC distributor. FIG. 1
`illustrates a circuit 100 for supplying power to an integrated
`circuit load 108 in accordance with the prior art. Circuit 100
`includes AC voltage source 102, SDC 104, and power
`delivery system 106.
`Initially, voltage is supplied by AC voltage source 102. If
`SDC 104 is a VRM, the amplitude is then modified, and the
`resulting AC voltage is rectified, filtered, and regulated by
`SDC 104. In many cases, a separate analog-to-digital con-
`verter (not shown) is used to convert the AC power to DC
`before it is supplied to the VRM, whereupon the VRM steps
`the voltage down to a voltage required by the load 108. If
`SDC 104 is an AC distributor, the amplitude is modified and
`the frequency is enhanced before supplying the power to
`load 108. SDC 104 may be incorporated into a single
`discrete component, or may include multiple discrete com-
`ponents (e.g., voltage regulator,
`inductors, decoupling
`capacitors, rectifiers, etc.). The converted voltage is then
`supplied to load 108 through power delivery system 106.
`Load 108 could be, for example, one or more circuits within
`a microprocessor or some other type of integrated or discrete
`circuit.
`
`Power delivery system 106 generally includes a series of
`conductive elements through which the power flows from
`SDC 104 to load 108. Avoltage drop occurs between SDC
`104 and integrated circuit load 108 due to losses along the
`path between SDC 104 and load 108. The voltage drop
`caused by power delivery system 106 can be roughly
`modeled by an inductor 110 in series with a resistor 112,
`which represent the inductance and resistance, respectively,
`of the conductive path between SDC 104 and load 108. In
`many cases, it is desirable to minimize these values in order
`to minimize the voltage drop that occurs through the power
`delivery system 106.
`the farther the distance
`All other things being equal,
`between SDC 104 and integrated circuit load 108, the larger
`the voltage drop. At relatively low voltages, this voltage
`drop is a tolerable effect that is compensated for by provid-
`ing an SDC that supplies a higher voltage than is actually
`needed by the integrated circuit. Anegative side effect of this
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`2
`strategy, however, is that the SDC may need to be larger than
`necessary, and power is inefficiently consumed.
`In some prior art configurations, to reduce the distance
`between the SDC 104 and the load 108, SDC 104 is mounted
`on a printed circuit (PC) board as close as practical to the
`integrated circuit package socket.
`In this configuration,
`current
`travels through traces in the PC board, and up
`through the socket and the package pins. The current con-
`tinues along traces in the package to connections that make
`electrical contact with pads on the integrated circuit.
`the
`In some high performance applications, however,
`electrical distance between a PC board mounted SDC and
`the integrated circuit is unacceptably far. One solution for
`reducing the electrical distance between the SDC and the
`integrated circuit is to mount the SDC on a power pod, and
`to connect the power pod to an interposer upon which the
`integrated circuit package is mounted.
`FIG. 2 illustrates a schematic cross-section of an SDC 202
`mounted on a power pod 204, and coupled to an interposer
`206 via a connector 208 in accordance with the prior art. An
`interposer 206 essentially is a small PC board that enables
`other components to be mounted in close proximity to the
`integrated circuit, and/or that provides a dimensional inter-
`face between the connectors 210 to an integrated circuit
`package 212 and the pin holes of a PC board socket 214.
`Interposers are often used when the scale and/or location of
`connectors 210 are different from the scale and/or location
`of pin holes on the socket 214. In addition, in some cases,
`interposers may be used to house decoupling capacitors (not
`shown) or other small discrete components in close prox-
`imity to the integrated circuit package 212.
`SDC 202 receives AC power and ground through pins 216
`inserted into PC board 218. SDC 202 then regulates the
`power, as described above. The resulting voltage may then
`be filtered by an inductive filter and decoupling capacitors
`(not shown). That power is then supplied to integrated
`circuit 220. To supply power to the integrated circuit 220,
`electrical current travels from SDC 202 through traces (not
`shown) in power pod 204. The current then travels through
`connector 208 and additional
`traces (not shown) within
`interposer; 206, through connectors 210, and through still
`other traces (not shown) in integrated circuit package 212.
`Finally, the current reaches ball joints (or some other type of
`connector, such as bond wires), which electrically and
`physically connect integrated circuit 220 to package 212.
`Various loads (not shown) on the integrated circuit 220 may
`then consume the supplied power.
`Unfortunately, connector 208 is a relatively high-
`inductance component, thus the performance of the power
`delivery system is reduced by its presence. In addition,
`connector 208 is a separate component, resulting in addi-
`tional cost, reliability issues, and board, assembly proce-
`dures.
`
`As frequencies, edge rates, and current demands of high
`performance integrated circuit products continue to increase,
`the inductance and resistance of the power delivery system
`become critical parameters. For the reasons stated above and
`for other reasons stated below, which will become apparent
`to those skilled in the art upon reading and understanding the
`present specification, there is a need in the art for a lower-
`inductance power delivery system than has been achieved
`using prior art configurations. In addition, there is a need in
`the art for a power delivery system that is low-cost, reliable,
`and does not require significant changes in board assembly
`procedures.
`BRIEF DESCRIPTION OF THE DRAWING
`
`FIG. 1 illustrates a power supply circuit in accordance
`with the prior art;
`
`

`

`US 6,469,908 B2
`
`3
`FIG. 2 illustrates a schematic cross-section of an SDC
`
`mounted on a power pod and coupled to an interposer via a
`connector in accordance with the prior art;
`FIG. 3 illustrates a schematic cross-section of an SDC and
`
`integrated circuit mounted on a dual-socket interposer in
`accordance with one embodiment of the present invention;
`FIG. 4 illustrates a top view of the interposer configura-
`tion shown in FIG. 3 in accordance with one embodiment of
`
`the present invention;
`FIG. 5 illustrates a schematic cross-section of an SDC
`
`10
`
`package and integrated circuit package mounted on a dual-
`socket interposer in accordance with another embodiment of
`the present invention;
`FIG. 6 illustrates a schematic cross-section of an SDC
`
`package and integrated circuit package mounted on a dual-
`socket interposer in accordance with another embodiment of
`the present invention;
`FIG. 7 illustrates a schematic cross-section of an SDC
`
`mounted on a PC board and an integrated circuit package
`mounted on a dual-socket interposer in accordance with
`another embodiment of the present invention;
`FIG. 8 illustrates a flowchart of a method for fabricating
`a dual-socket interposer in accordance with one embodiment
`of the present invention;
`FIGS. 9—12 are schematic cross sections illustrating vari-
`ous stages of fabricating a dual-socket interposer in accor-
`dance with one embodiment of the present invention; and
`FIG. 13 illustrates a general purpose computer system in
`accordance with one embodiment of the present invention.
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`The apparatus of the present invention includes an inter-
`poser having two sets of pins that connect to two sockets on
`a PC board. Some pins in the first set of pins are designated
`to supply power to a step down converter (SDC), such as a
`voltage regulator module (VRM) or an AC distributor. Some
`pins in the second set of pins are designated to provide
`inputs and outputs to an integrated circuit mounted on the
`interposer. Conductive traces in or on the interposer elec-
`trically connect the SDC output to one or more inputs to the
`integrated circuit. In various embodiments, the SDC and
`integrated circuit (or their packages) are mounted on the
`interposer using pin grid, ball grid, and land grid arrays. In
`another embodiment, the SDC is mounted on the PC board,
`and the first set of pins carries the SDC output
`to the
`conductive traces in or on the interposer.
`FIG. 3 illustrates a schematic cross-section of an SDC 302
`
`and integrated circuit package 304 mounted on a dual-socket
`interposer 306 in accordance with one embodiment of the
`present invention. Interposer 306 includes two sets of pins
`308, 310 on the bottom surface of the interposer 306. The
`first set 308 inserts into a first socket 312 on PC board 314,
`while the second set 310 inserts into a second socket 316 on
`PC board 314.
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`least some pins in the first set of pins 308 are
`At
`designated to supply power to SDC 302, where that power
`can take the form of AC or DC current. SDC 302 can be
`
`60
`
`mounted directly on interposer 306 using flip-chip
`technology, or in alternate embodiments, it can be mounted
`on a pinned, land grid, or ball grid package that connects to
`interposer 306. Some of these alternate embodiments are
`more fully described, below.
`In one embodiment input capacitor 318 and input inductor
`320 filter the input power, and output capacitor 322 and
`
`4
`output inductor 324 filter the output power. The output of
`SDC 302 is supplied to integrated circuit 304 via conductive
`traces (not shown) within or on interposer 306.
`At least some pins in the second set of pins 310 are
`designated to provide inputs and outputs to integrated circuit
`304. Integrated circuit 304 can be, for example, a micro-
`processor or some other type of integrated circuit
`that
`requires a regulated source of power. Integrated circuit 304
`can be mounted directly on interposer 306 using flip-chip
`technology, or in alternate embodiments, it can be mounted
`using flip-chip or wirebond technologies on a pinned, land
`grid, or ball grid package that connects to interposer 306.
`Some of these alternate embodiments are more fully
`described, below.
`Various capacitors, such as die side capacitors 326 (i.e.,
`capacitors on the top surface of interposer 306) and land side
`capacitors 328 (i.e., capacitors on the bottom surface of
`interposer 306), can be electrically connected to integrated
`circuit 304 in order to provide decoupling and/or excess
`capacitance. In one embodiment, the second set of pins 310
`can be arranged so that the land side capacitors 328 do not
`interfere with socket 316. In other words, the array may
`exclude pins in its center, and the land side capacitors 328
`can be mounted in the center space instead.
`In other
`embodiments, the second set of pins 310 can be a continuous
`array of pins, without space for land side capacitors 328. In
`still other embodiments,
`the first set of pins 308 can be
`arranged in a manner similar to the arrangement shown for
`the second set of pins 310, and some or all of the input
`and/or output capacitors 318, 322 and/or inductors 320, 324
`can be mounted on the bottom side of interposer 306.
`FIG. 3 illustrates that two separate sockets are used to
`supply power to SDC 302 and to provide inputs and outputs
`to integrated circuit 304. Unlike prior art systems, the SDC
`output
`is not supplied to integrated circuit 304 through
`socket 316. Instead, the SDC output is supplied to integrated
`circuit 304 through conductive traces (not shown) within
`interposer 306.
`This is depicted in more detail in FIG. 4, which illustrates
`a top view of the interposer configuration shown in FIG. 3
`in accordance with one embodiment of the present inven-
`tion. One or more conductive traces 402 electrically connect
`an output of SDC 302 with an input of integrated circuit 304.
`Conductive traces 402 may be deposited on the top or
`bottom surface of interposer 306, or they may be disposed
`in between one or more layers of interposer 306.
`Referring also to FIG. 3, because the SDC output need not
`travel through socket 316, the SDC output has a very low
`inductance to the integrated circuit 304. Thus, the voltage
`drop between SDC 302 and integrated circuit 304 may be
`significantly less than can be achieved using prior art
`methods, making the dual-socket interposer design of the
`present invention better suited to high-performance appli-
`cations.
`
`Although a certain number of conductive traces 402, pins
`308, 310, capacitors 318, 322, 326, 328, and inductors 320,
`324 are shown in FIGS. 3 and 4, more or fewer of any of
`these elements could be included in any of numerous
`designs without departing from the scope of the present
`invention.
`FIG. 5 illustrates a schematic cross-section of an SDC
`
`65
`
`package 502 and integrated circuit package 504 mounted on
`a dual-socket interposer 506 in accordance with another
`embodiment of the present
`invention. Conceptually,
`the
`embodiment shown in FIG. 5 is similar to that shown in FIG.
`
`3, in that interposer 506 includes two sets of pins 508, 510
`
`

`

`US 6,469,908 B2
`
`5
`that insert into two separate sockets 512, 514 on a PC board
`516. The first set of pins 508 supplies power to an SDC 518,
`and the second set of pins 510 provide inputs and outputs to
`integrated circuit 520. In addition, conductive traces (not
`shown) within interposer 506 electrically connect the output
`of SDC 518 to one or more inputs of integrated circuit 520.
`In the embodiment shown in FIG. 5, however, SDC 518
`is mounted on an SDC package 502, rather than being
`mounted directly on interposer 506. In the embodiment
`shown, SDC 518 is a flip-chip, and package 502 is a ball grid
`or land grid array package. In an alternate embodiment, SDC
`518 could be wirebonded to package 502.
`Input capacitor 522 and input inductor 524 are mounted
`on SDC package 502, while output capacitor 526 and output
`inductor 528 are mounted on interposer 506. In various
`alternate embodiments, SDC 518 could be connected to
`SDC package 502 using bond wires, or some other connec-
`tion technology. In addition, input capacitor 522 and/or input
`inductor 524 could be mounted on interposer 506, and/or
`output capacitor 526 and/or output inductor 528 could be
`mounted on SDC package 502.
`Also in contrast to the embodiment shown in FIG. 3,
`integrated circuit 520 is mounted on integrated circuit pack-
`age 504, rather than being mounted directly on interposer
`506. In the embodiment shown, integrated circuit 520 is a
`flip-chip, and package 504 is a ball grid or land grid array
`package. In an alternate embodiment, integrated circuit 520
`could be wirebonded to package 504.
`Land side capacitors 530 are mounted on the bottom
`surface of package 504, and interposer 506 includes an
`opening that accommodates capacitors 530. Decoupling
`capacitors 532 are mounted on interposer 506. In an alter-
`nate embodiment, decoupling capacitors 532 could be
`mounted on the top surface of package 504.
`FIG. 6 illustrates a schematic cross-section of an SDC
`
`package 602 and integrated circuit package 604 mounted on
`a dual-socket interposer 606 in accordance with another
`embodiment of the present
`invention. Conceptually,
`the
`embodiment shown in FIG. 6 is similar to that shown in FIG.
`
`5, in that interposer 606 includes two sets of pins 608, 610
`that insert into two separate sockets 612, 614 on a PC board
`616. The first set of pins 608 supplies power to an SDC 618,
`and the second set of pins 610 provide inputs and outputs to
`integrated circuit 620. In addition, conductive traces (not
`shown) within interposer 606 electrically connect the output
`of SDC 618 to one or more inputs of integrated circuit 620.
`In the embodiment shown in FIG. 6, however, SDC
`package 602 is a pinned package, where pins 622 on a
`bottom surface of package 602 insert into a socket 624 on
`the top surface of interposer 606. Some of pins 622 are
`dedicated to supplying input power to SDC 618, and some
`of pins 622 are dedicated to connecting the SDC output to
`the conductive traces (not shown) within interposer 606.
`Although the embodiment shown in FIG. 6 is a higher-
`inductance configuration, it enables a non-functional SDC to
`be easily replaced. This ability to swap out SDC packages
`increases board yields during production, since it eliminates
`the need to scrap an entire printed wiring board due to a
`faulty SDC.
`In some cases, it may be desirable to mount the SDC on
`the PC board, rather than mounting it on the interposer. This
`may be the case,
`for example, when it
`is desirable to
`optimize the number of pins to meet the needed inductance,
`resistance, and current requirements of the integrated circuit,
`without requiring socket pin counts to exceed a reasonable
`number of pins. In addition, it may be desirable to use a
`
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`commercially-available socket, rather than designing and
`manufacturing a specialized socket.
`Both of these performance and cost optimizations can be
`achieved by mounting the SDC on the PC board, and still
`using a dual-socket interposer to separate the SDC output
`pins from the integrated circuit input and output pins. FIG.
`7 illustrates a schematic cross-section of an SDC package
`702 mounted on a PC board 704 and an integrated circuit
`package 706 mounted on a dual-socket interposer 708 in
`accordance with another embodiment of the present inven-
`tion.
`
`Interposer 708 includes two sets of pins 710, 712 on its
`bottom surface. Pins 710, 712 insert
`into two separate
`sockets 714, 716 on PC board 704. The first set of pins 710
`connect to conductive traces (not shown) disposed in or on
`interposer 708, and that electrically connect to one or more
`inputs of integrated circuit 718.
`SDC package 702 is a pinned package, where pins 720 on
`a bottom surface of package 702 insert into a socket 724 on
`the top surface of PC board 704. In an alternate embodiment,
`SDC package 702 can mount to a bottom surface of PC
`board 704. In such an embodiment, it may be desirable from
`a performance perspective to mount SDC package 702
`directly underneath socket 714, thus reducing the inductance
`between SDC package 702 and integrated circuit 718.
`SDC 722 is shown as a flip-chip, although it also could be
`attached to package 702 using wirebond or some other
`packaging technology. At least some of pins 720 are dedi-
`cated to supplying input power to SDC 722, and some of
`pins 720 are dedicated to connecting the SDC output to
`conductive traces (not shown) within PC board 704. These
`conductive traces connect to socket 714, and thus to pins 710
`and the conductive traces (not shown) within interposer 708.
`The conductive traces, thus, electrically connect pins 710 to
`one or more inputs of integrated circuit 718. In this manner,
`SDC output travels from SDC package 702 through pins
`720, socket 724, conductive traces in PC board 704, pins
`710, conductive traces (not shown) in interposer 708, and
`package 706 before reaching integrated circuit 718.
`FIG. 8 illustrates a flowchart of a method for fabricating
`a dual-socket interposer in accordance with one embodiment
`of the present invention. FIG. 8 should be viewed in con-
`junction with FIGS. 9—12, which are schematic cross sec-
`tions illustrating various stages of fabricating a dual-socket
`interposer in accordance with one embodiment of the
`present invention. The method begins,
`in block 802, by
`fabricating an interposer substrate 902 (FIG. 9). Substrate
`902 includes one or more levels 904 of patterned conductive
`material disposed in between or on a surface of layers of
`non-conducting material. In addition, conductive intercon-
`nects 906 electrically connect the multiple levels 904 of
`conductive material, and also provide connections to one or
`more sockets 908 and/or pads 910 on the top surface of
`interposer substrate 902. Although, as will be described
`below, socket 908 and pads 910 are used to connect an
`integrated circuit package an SDC or SDC package to
`substrate 904, it should be understood that the use of a socket
`908 and pads 910 for these respective components is for
`example purposes only. In various embodiments, either or
`both an integrated circuit (or an integrated circuit package)
`and an SDC (or an SDC package) could be connected to
`substrate 904 using a socket or pads.
`Interposer substrate 902 also includes two sets 912, 914 of
`pin holes, located on the bottom surface of substrate 902. Pin
`holes 912, 914 form openings into which pins (not shown)
`can be inserted, making electrical contact with interconnects
`906 and/or conductive material levels 904.
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`US 6,469,908 B2
`
`7
`The process of fabricating interposer substrate 902 uses a
`combination of PC board fabrication techniques that are well
`known to those of skill in the art. Generally, these techniques
`involve a build-up process that begins by providing a first
`layer of the substrate. In one embodiment, the substrate is an
`organic substrate, such as an epoxy material. For example,
`standard PC board materials such as FR-4 epoxy-glass,
`polymide-glass, benzocyclobutene, Teflon, other epoxy
`resins, or the like could be used in various embodiments. In
`alternate embodiments,
`the substrate could consist of an
`inorganic substance, such as ceramic, for example. In vari-
`ous embodiments, the thickness of interposer substrate 902
`is within a range of about 10—1000 microns. Interposer
`substrate 902 could consist of one or multiple layers of
`substrate material, where each layer is within a range of
`about 10—40 microns in one embodiment. Substrate 902 and
`
`its associated layers could be thicker or thinner than these
`ranges in other embodiments.
`Generally, substrate 902 includes layers of patterned
`conductive material 904 separated by non-conducting
`dielectric layers. The patterned conductive layers 904
`include conductive traces, that enable the outputs of an SDC
`to be electrically connected to the inputs to an integrated
`circuit. Thus, the patterned conductive traces interconnect
`some of pads 910 with some of the socket holes in socket
`908.
`
`In one embodiment, the patterned conductive layers 904
`are copper layers, although other conductive metals such as
`tin, lead, nickel, gold, and palladium, or other materials
`could be used in other embodiments.
`In various
`
`the thickness of each conductive layer is
`embodiments,
`within a range of about 5—15 microns. The conductive layers
`904 could be thicker or thinner than that range in other
`embodiments.
`
`The patterned conductive layers 904 can be formed, for
`example, by depositing a seed layer, such as sputter-
`deposited or electroless-deposited copper, on a substrate
`layer, followed by electrolytic plating a layer of copper on
`the seed layer. In another embodiment, a conductive layer
`904 is formed using standard photolithographic techniques.
`Other methods of depositing a conductive layer 904 will be
`apparent to those skilled in the art, such as screen printing
`or other printing of conductive inks.
`In still another
`embodiment,
`a clad laminate, such as a copper-clad
`laminate, could be used.
`Dielectric layers are formed over some of the conductive
`material layers 904 in order to electrically isolate the con-
`ductive layers from each other. In one embodiment, each
`dielectric layer contains a metal oxide, such as tantalum
`oxide (Ta205). The metal oxide may be formed using a
`physical vapor deposition technique of the metal, and anod-
`izing the layer of the metal in a weak acid electrolyte to form
`the metal oxide. For example, the metal may be sputter
`deposited from a metal target to form a layer of the metal.
`In one embodiment, a shadow mask can be placed on or in
`close proximity to the substrate to block or mask areas where
`deposition is not desired. Physical vapor deposition tech-
`niques also can be carried out from one or both surfaces of
`the substrate.
`
`Alternatively, a metal layer may be deposited by electro-
`lytic plating or photolithographic techniques, and converted
`to the metal oxide by anodization in a weak acid electrolyte.
`In another embodiment, dielectric layers can be formed by
`RF sputtering from a composite target of a dielectric
`material, or
`through reactive sputtering from multiple
`elemental targets, without the need for anodization or other
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`8
`oxidation techniques. Metal organic chemical vapor depo-
`sition (MOCVD) and sol-gel techniques have further been
`utilized to directly form metal oxide dielectrics. Other
`techniques of forming layers of dielectric material are
`known in the art and can include chemical vapor deposition
`(CVD) and plasma-enhanced CVD. Furthermore, other
`dielectric materials can be utilized with the various embodi-
`
`ments. Examples of other dielectric materials include stron-
`tium titanate (SrTiO3), barium titanate (BaTiOS), barium
`strontium titanate (BaSrTiOS; BST), lead zirconium titanate
`(PbZrTiOS; PZT), aluminum oxide (A1203), or zirconium
`oxide (Zr203), often formed by sputtering from a composite
`target or by MOCVD. Further examples include more con-
`ventional dielectric materials, such as silicon dioxide
`(SiOZ), silicon nitride (SiN), and silicon oxynitride
`(SiOxNy).
`During the build-up process, portions of the conductive
`904 and dielectric layers can be selectively removed, expos-
`ing portions of other conductive layers 904 underneath the
`removed portions. Removal of the portions of conductive
`material could be performed, for, example, using a common
`subtractive technology, such as chemical mechanical pla-
`narization to physically abrade away the material.
`Alternatively, a photo or laser imaging and etching process
`could be used. Other subtractive technologies could be used
`in other embodiments. In still other embodiments, additive
`technology could be used to deposit the desired portions of
`conductive layers. For example, rather than plating and
`subtracting portions of the conductive layers 904, portions
`of the conductive layers could be selectively screened or
`stenciled using a conductive paste.
`