(12) United States Patent
`(10) Patent N0.:
`US 6,730,540 B2
`
`Siniaguine
`(45) Date of Patent:
`May 4, 2004
`
`USOO6730540B2
`
`(54) CLOCK DISTRIBUTION NETWORKS AND
`CONDUCTIVE LINES IN SEMICONDUCTOR
`INTEGRATED CIRCUITS
`
`(75)
`
`Inventor: Oleg Siniaguine, San Carlos, CA (US)
`
`(73)
`
`Assignee: Tru-Si Technologies, Inc., Sunnyvale,
`CA (US)
`
`( * )
`
`Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21)
`
`(22)
`
`(65)
`
`(51)
`(52)
`
`(58)
`
`(56)
`
`Appl. No.: 10/127,144
`
`Filed:
`
`Apr. 18, 2002
`Prior Publication Data
`
`US 2003/0199123 A1 Oct. 23, 2003
`
`Int. Cl.7 ................................................ H01L 21/44
`US. Cl.
`....................... 438/107; 438/108; 438/110;
`257/723; 257/777
`Field of Search ................................. 327/295, 296,
`327/297, 298, 299; 257/690, 698, 723,
`777; 438/107, 108, 110
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`
`
`.............. 257/678
`1/1993 Chance et al.
`5,177,594 A
`10/1993 Simmons et al.
`.
`361/687
`5,251,097 A
`
`.................... 385/14
`5/1995 Koh et al.
`5,416,861 A *
`3/1996 Gehman et al.
`.............. 29/840
`5,501,006 A *
`9/1997 Dangelo .......
`.. 257/210
`5,665,989 A *
`6/1998 Koh .................. 385/14
`5,761,350 A *
`9/1998 Bertin et al.
`.. 257/516
`5,811,868 A
`3/2000 Rao et al.
`................... 327/298
`6,037,822 A *
`3/2000 Bozso et al.
`................ 438/106
`6,040,203 A
`1/2001 Paniccia et al.
`..
`257/778
`6,175,160 B1
`
`........
`4/2001 Mak et al.
`257/532
`6,222,246 B1
`....... 438/725
`7/2001 Chooi et al.
`6,265,321 B1
`
`343/700 MS
`8/2001 Lesea et al.
`6,271,795 B1 *
`.................. 438/108
`8/2001 Ahn et al.
`6,281,042 B1 *
`6,311,313 B1 * 10/2001 Camporese et al.
`.
`...... 716/6
`
`6,322,903 B1
`11/2001 Siniaguine et al.
`..
`428/617
`
`6,424,034 B1 *
`7/2002 Ahn et al.
`........
`257/723
`................ 438/107
`6,461,895 B1 * 10/2002 Liang et al.
`
`.................... 438/618
`6,495,442 B1 * 12/2002 Lin et al.
`.................. 257/717
`6,586,835 B1 *
`7/2003 Ahn et al.
`2002/0068441 A1 *
`6/2002 Lin ............................ 438/637
`OTHER PUBLICATIONS
`
`L. Cao and J .P Krusius, A Novel “Double—Decker” Flip—
`Chip BGA Package for Low Power Giga—Hertz Clock
`Distribution, 1997 47th Electronic Components And Tech-
`nology Conference, San Jose, CA, 1152—1157 (May 16—21,
`1997).*
`E. A. M. Klumpernik et al., “Transmission Lines in CMOS:
`An Explorative Study”, 12th Annual Workshop on Circuits,
`Systems and Signal Processing, Veldhove/Netherlands, Nov.
`29—30, 2001, pp. 440—445.
`Jim Lipman, Technical Editor, “Growing your own IC clock
`tree”, EDN Access—03.14.97 Growing your own IC clock
`tree, http://archives.e—insite.net/archives/ednmag/reg/l997/
`031497/06CS.htm, Feb. 27, 2002, pp. 1—7.
`
`* cited by examiner
`
`Primary Examiner—Long Pham
`Assistant Examiner—Thao X. Le
`
`Firm—Michael
`or
`(74) Attorney, Agent,
`MacPherson Kwok Chen & Heid LLP
`
`Shenker;
`
`(57)
`
`ABSTRACT
`
`A clock distribution network (110) is formed on a semicon-
`ductor interposer (320) which is a semiconductor integrated
`circuit. An input terminal (120) of the clock distribution
`network is formed on one side of the interposer, and output
`terminals (130) of the clock distribution network are formed
`on the opposite side of the interposer. The interposer has a
`through hole (360), and the clock distribution network
`includes a conductive feature going through the through
`hole. The side of the interposer which has the output
`terminals (130) is bonded to a second integrated circuit
`(310) containing circuitry clocked by the clock distribution
`network. The other side of the interposer is bonded to a third
`integrated circuit or a wiring substrate (330). The interposer
`contains a ground structure, or ground structures (390, 510),
`that shield circuitry from the clock distribution network.
`Conductive lines (150) in an integrated circuit are formed in
`trenches (610) in a semiconductor substrate.
`
`21 Claims, 15 Drawing Sheets
`
`
`
`'
`
`I
`\\
`l
`" "'I
`vow0"“
`”vac.
`t \ \\\\
`A\\\\\.\\\‘
`poo...
`0609»
`O
`. v M
`o o o.
`Q?” ‘84
`.Q:¢’Q:4‘o’<
`'o‘o’v’o‘o‘o‘
`.‘o’o’oo‘o’o
`’A’.‘A‘A‘“‘
`flfifi‘fifld
`
`i’$‘3‘$’3’5
`wooow
`”cwow
`goo...
`fo‘¢%‘o’o’4
`l’.‘.’§.’o’d
`
`
`
`
`
`I
`\
`.
`
`
`
` _—vv ’
`
`V‘V
`'V'O'!
`
`.
`
`p.0¢..,—>uV". 9"V"':‘:‘l""";‘:.1"""
`’O’Q‘V‘VV‘Q‘
`
`fio‘o’o‘o’o’o’o’o’ofl‘o’o’o’.‘‘ ’ 0 o o
`oooocooooooooooooooooooooo
`...................
`...........
`"W"°"”""’””""333:5:35:3:1:3:::3:3:3:o:
` o‘o‘o‘6‘9‘o‘o‘9V9‘o‘
`
`'O'O’o‘o‘o’o‘o’o’0’0’9’0’6’9’0’0'9"
`
`_
`
`I
`
`IVM 1004
`IPR of U.S. Pat. No. 7,566, 960
`
`

`

`US. Patent
`
`May 4, 2004
`
`Sheet 1 0f 15
`
`US 6,730,540 B2
`
`130 H
`
`ad
`<
`
`3
`
`o
`S
`
`l
`
`I
`
`ad
`'
`. O
`a
`
`.
`
`0-4
`
`.
`
`E
`LL
`
`"
`,8:
`
`

`

`US. Patent
`
`May 4, 2004
`
`Sheet 2 0f 15
`
`US 6,730,540 B2
`
`160.2
`
`
`
`
`
`
`IIIIIIIIIIIIII‘
`IIIIIII
`IIIII4
`
`
`.IIIIIIISII-II
`“III-IIIH II-II{
`“:IIIIIIMIIIIIM
`IIIIIIIIIII'
`HI ~ III§ IIIII.
`
`
`3 III
`II-II‘
`
`III-IIIIIII-II
`
`
`
`
`
`
`
`
`FIG.2PRIORART
`
`
`
`milli-
`
`>
`
`
`
`
`IIIII{
`III
`I
`IIIIIIIIIIIIII
`
`
`
`
`
`

`

`US. Patent
`
`May 4, 2004
`
`Sheet 3 0f 15
`
`US 6,730,540 132
`
`omm
`
`ExamMODEm.05
`
`

`

`US. Patent
`
`May 4, 2004
`
`Sheet 4 0f 15
`
`US 6,730,540 132
`
`o<
`
`-
`
`Pd“
`ov—‘
`m
`
`PM
`
`3 1! 6"“.
`
`"
`
`
`
`«
`M O
`N N
`0') —-¢
`
`I
`
`*:~:~:v:::‘:«-
`,
`wu-o‘;
`0°
`*
`-
`«v 4» h
`wmpfiqra K 00
`hfl‘i 4‘
`m
`«My "" —
`tvfivfi-
`._.,.—,-,-.——-
`w¢¢¢¢ _ rv'" 4
`"‘¢’.§I
`I
`p.
`*1
`7
`¢ *"'{
`—/ 4.
`1
`”H4 0;».
`/ r.
`4
`NH?” 4’“
`f“ V
`‘4
`Oflfir"! — I, Q
`§
`b’t‘t’v’fi
`/ it
`4
`'%*‘.‘*V
`{4
`\A.‘4.§4.,4
`
`
`
`
`
`‘
`
`'
`
`‘
`
`.
`
`§$“‘*’*§!I f—
`’3
`i’fi- I —§ fififi‘fi
`/ 941" ”’4
`fr"
`~
`9
`,+,~
`f a»
`o
`a
`a:
`*1“
`«4
`m
`.,§ . 4‘ — -
`%*<’~%$*:*1”-Il K o
`35% "0‘3
`afiflzaotql
`Q
`o ¢“'.*‘*«Vr:"‘-l (I m“ o
`5v:
`:.I—
`a 2*
`30
`9‘3
`g.
`2:.—
`ifi’fifl— ll
`BW 9&4‘
`w «ms.
`main”
`Wfl’flfi":
`Wvflfi'fil- "
`§'¢%‘§’*fi .
`¢*¢%¢’¢’+4
`°°
`Wk 1’4 _
`°°
`I
`fitfi’fi‘hl'
`Vfl’vaJ K. m
`fiféfi'fil—
`4M3: A
`n‘wfi'll
`._-.—.-———-
`«W’é- ‘vfi
`'
`*Wék'"
`”$04,336.!:1."
`
`FIG.4
`
`_
`
`-
`
`___
`
`§ 3
`
`23.1
`
`1
`
`

`

`US. Patent
`
`May 4, 2004
`
`Sheet 5 0f 15
`
`US 6,730,540 B2
`
`
`
`» 000+
`
`
`#50000
`~qp¢+¢
`
`hfii’fifif‘
`
`9‘05ng —mm!
`
`waxy _
`:30... I4
`(r .
`
`
`
`’Y’T’f’
`
`
`§%,§¥g.""
`
`.
`rmMb-Il
`
`
`
`
`ggzzggl— _.§.
`
`
`
`azmw-IIER
`as
`§
`fil...
`v
`\
`«V .
`W
`§
`fifi‘fififlv
`mm.— I —%
`~+q¢4+
`\
`*¢
`M 0
`.
`%
`*2:
`4M0 “'3
`D Q Q
`§
`93" :‘I
`I
`1“"-
`:
`
`fiflflfi40¢¢++¢Am»..-J_
`wwwv
`f'fi'fi'qnfip4M5?jfli+£fi’ *1!
`(’7,:1}new$33.fifip*1
`
`to
`.
`CD
`E
`
`b Y
`
`
`
`l
`
`-
`
`
`
`
`
`r
`
`
`,A y
`
`
`

`

`US. Patent
`
`May 4, 2004
`
`Sheet 6 0f 15
`
`US 6,730,540 132
`
`
`
`h-----------------nn-
`
`

`

`US. Patent
`
`May 4, 2004
`
`Sheet 7 0f 15
`
`US 6,730,540 B2
`
`o
`V
`
`1-:
`O
`v—n
`
`O
`!-4
`P-4
`
`O
`N
`m
`
`m
`
`5Ta?”351$“«09:
`
`3;};
`
`$0.02I
`fi.
`7
`
`Q.A
`
`'0
`Q0*
`
`
`
`‘O0‘:4i
`9"
`PA
`
`4'
`
`\II
` .v.‘rO40*1.».3}.‘9Q4““
`
`
`.§
`
`
`
` ’3 ‘0
`4?
`
`’70
`A9'9'9'?‘”,9uMn4%:wt
`0.‘J‘A
`
`
`ii40:»
`
`’T.Y.‘P«wm9‘0’9“1*?i».
`
`
`
`1;"oG‘1"M» Q’0
`
`179.0»«0:5‘8‘toL"
`
`
`17,7.V#00QQ*6? ¢.'§‘§9.?
`
`
`079’?OO0'OQ9%‘3’:h.
`
`
`’5‘3‘5“?
`
`#‘f’§’§' Q9§‘0‘»‘0‘0
`
`
`
`
`*1{0:4b1:»0’0
`
`
`
`
`
`FIG.7
`
`33
`
`
`
`»Q:
`OQ
`
`

`

`US. Patent
`
`Dday4,2004
`
`Sheet 8 0f 15
`
`US 6,730,540 132
`
`390
`
`
`
`
`Q¢
`
`Q
`
`¢ ¢
`
`+o
`
`
`
`
`
`
`320
`UUUU7ZIIIZlflflllflZlllflflflHUUV?UU?T????TTITZIZIIZIIZZEH£H&
`
`630
`
`
`
`
`._.
`vvvyI-Y
`.. , .
`w . V???“a» . ,
`
`
`I
`afifififififififififlfifi
`¢
`§
`
`4@%‘
`¢+$51fifi¢
`¢+o*$ufi$$,
`
`vvvvv
`##flfsfiflfifififl
`d5”
`¢¢¢¢¥§og¢
`.
`
`#¥1§¥%
`fi
`.
`5gp“ **
`‘ 4»
`QM
`
`3gfi§$¢5£§$§fi§§§fifi$$wvvav
`v‘r
`évvvv
`
`fiéééfiggfifi§§fifis§§§§§§§§§
`
`
`r-r
`¢¢§O¢§§$§O gaggp¢¢¢oqfi
`‘-
`¢¢fih
`§¢
`
`fifififl$¢
`¢¢o¢ t4§$~$fifl~§-fififlflflflfi
`
`r
`d
`'0
`4) or o a, ’9‘”;ugsgqggo t «Hr
`o
`o.
`gag“;
`Q}
`»¢¢o o
`¢§¢¢¢yfigp *¢
`ififl‘fio‘dWtfi’fiifi'fi:$+«b4!
`+¢¢‘¢
`é???
`awvvu»
`‘1fiflfivz dfi¢flfihfififififlfifl¥¥¥kfi
`Q
`fig? 99*
`
`uuu.iwwuuu
`g»
`‘flmg
`’0
`§¢§?Q‘} *¢
`‘00
`O’.
`.9.“. * *§*§*§‘
`Q}.
`
`* 0 . ‘§**§**Qf§§§§¢§§§
`...........
`¢¢+¢¢a
`h駧fl§§§§§t§fifi '”
`
`
`fififififi
`
`
`
`
`- & #45
`w§
`
`
`
`m:
`+¢
`
`
`‘1”
`fiflflfifl
`¢
`to
`¢¢§+¢
`
`-;¢§+o¢+++§¢a
`
`fifififitfifiéfifi‘t‘fi
`
`fifimpfifi
`awgavvs
`¢
`t¢ts¢t4t¢t€¢t¢t¢t€d
`
`ifi
`h¢4§¥¥¥¥V¥5
`
`%&&fifl&fififlfi?
`
`
`9”
`fiflfiflflhfififlflhi
`
`
`Eh
`Wfiflflflfifififififi’
`O‘
`
`’9‘ ’*"‘"§"9’V'9'.'9":*:**‘:.:‘:*’*.t":*§‘é
`
`.‘
`fifi$§$§%fi&g&¢§¢8§¢+++¢¢¢
`¢++o¢¢++¢+*
`
`
`qflz
`.évavvvuvvvv
`¢
`”*avwmz
`;‘§&*¢o‘¢¢o¢.
`'3
`fififfitfi
`Vfiflflfiwfi
`#V%w.
`?v
`
`
`fiffififiyt
`*¢¢¢¢¢+¢.
`qg$$5,
`gyggggx
`¢o+¢+{
`vo
`.fgflfifih
`+¢¢~§
`‘q9¢q&&p¢
`affigagfi»
`
`
`péfioo¢¢o¢¢o
`o¢q¢¢¢¢¢¢afi§
`d
`v +9¢+§9¢o
`¢§¢
`
`
`afifip
`
`
`vamvvvvv
`##Qfifi?
`gggay
`*oflfifié§$§$¢$¢$fi
`fiwfifififiwfififlfl
`
`
`fiavyugpvagfly ¢
`fifififihfifi
`
`
`aggvs
`amamaaaavavwvz¢wwww--~
`
`
`o¢
`an;
`fifififlfififi"*¢*3fi%fififi$$fi
`
`
`¢q¢+qp
`g9 ¢¢qp+¢o
`qp¢q¢¢¢¢¢¢a¢gg
`9. $9439" ’3‘“
`d¥5
`as:g;:::§;:::;:;:;.:¢.:¢::fissfifixfir
`
`9d
`Qof¢¢$*¢‘*$¢¢*§¢*¢*fl’tfiflfifl’fifiw
`00
`+§§§
`p qp¢qw¢gfifip
`¢
`v d$w¥n.§va#$$§$$§w
`
`fiv.’.
`gagng
`O
`O
`g,
`fiatotvt3:2:2223:?:+t¢:¢1¢:¢31919t929:9.21
`Q» A»
`
`
`
`FIG.8
`
`
`
`
`
`
`
`
`
`
`6f
`
`
`
`
`
`
`
`
`
` 1
`
`
`
`

`

`US. Patent
`
`May 4, 2004
`
`Sheet 9 0f 15
`
`US 6,730,540 B2
`
`
`
`
`
`
`,-
`mewwwfi
`
`y¢¢+¢¢¢‘
`##fiflfififi
`
`4.
`
`
`
`
`
`
`
`
`
`
`
`— V
`
`‘W’O‘Q
`
`I.”
`
`0+00i?
`
`0tdb¢
`
`«9+ o «
`00¢4§¢¢
`
`Qfififlfifih
`900! +0*
`£€¢$3¢é
`
`hfififlfifiw
`flflflflfififl
`fiflfiflflflfl
`hflfiflfififl
`fififififififi
`&
`'34-? 10$.A‘E
`
`
`
`630
`
`(I? 0
`
`620
`
`3% gat0.
`
`
`.9t
`
`
`vv
`
`'Qa:f03a;3*:45n
`z: :2§
`
`9
`
`0D I
`fit00toat
`$>#_
`
`~
`
`é!
`
`p90. 00
`
`
`
`sfifis‘w
`
`gggffiga
`
`figagfiafi
`fifififiafififi
`~¢¢¢¢50+
`0+0¢¢¢¢¢
`flfifififififi
`.§¢¢¢%¢+
`¢¢§o§+¢<
`9
`'fififiéfififi00+
`
`O”O9«3‘‘0
`4¢+qg
`
`
`Willi/III!III!III/III!IIIIIIIIIIIIII/Illlllllllllllllllfl
`
`Nov ‘
`
`4 §
`
`
`
`§\x
`
`x S
`
`§\
`
`

`

`US. Patent
`
`May 4, 2004
`
`Sheet 10 0f 15
`
`US 6,730,540 132
`
`
`
`510
`
`
`«f'f'f wry .
`..~.¢ ¢¢€%+vv.
`fififlfifigfiQfififififlfifli
`
`#wwvwvvfl
`
`
`vfifififififi
`odk¢¢+¢¢¢d§+¢+
`
`
`r9+++¢¢§
`awwwswwwumu
`fiflfififi.
`¢¢¢¢¢¢
`4% ¢¢t+¢+¢¢¢+¢¢¢¢4
`’v¢¢¢+
`
`
`++¢++4+¢+¢+¢§++¢
`o*.¢¢,
`#97
`¢‘¢+qp¢ 0
`éfl¥¥%§*+¢
`fifififififit
`oéfi?‘9‘G
`
`
`710
`fififififififififififififih
`4+
`¢¢+¢u€
`u¢¢¢+
`¢¢¢‘¢¢¢#
`flfih?‘
`+‘+¢++ ¢¢¢++4+¢+
`*ofii‘i».
`Jofifiéfifigwwm
`p¢+¢¢6¢§¢¢ 4f¢f+
`afifipfipfififi$§$m¢¢
`
`
`¢++¢4
`.
`.
`§¢+q
`
`
`ggwagfiwvvavwvfiaggggy
`gay¢
`fifififigfihfifikfifififif
`dwvfi
`“to
`gfivvfififigfififififi§g§$ffifl
`¢
`fifl#“¢
`‘oq, ‘Q i? *1 *9
`dwww4
`4 G<5 0 {r
`4}
`f.§***¢’§.4‘9‘§*§*
`§?*#¢¢¢¢Q¢¢¢
`,
`fififififififififigfififififififififififififi
`‘%#t4
`wwwfi
`fimfigghammflb¢¢+
`4‘Ab
`+4wwwu~wu~s-ms
`
`
`¢¢o¢¢+¢¢
`1'
`$¥$¥¥kfi¥b¢
`¢~p qgfigfififififiy
`
`
`‘4‘ O
`o ¢ v o c, v ¢ 4:» g,
`fifl$flfi¢fi$§flfi
`
`
`fififififififlflfifip*++++
`
`
`
`fiflfifififi?
`
`¢¢++++¢+1
`
`¢¢¢¢¢‘¢¢¢¢
`#W3
`a:*.*¢*1*3*$*1*i*3*31fi
`
`
`‘¥
`
`
`irl-
`
`
`fipitt¢§§¢¢§¢¢
`£3
`¢¢
`¢¢¢q
`ti‘fi
`
`ggmaggggggggy;
`
`¢¢W¥¢flfifififlfiflfi
`
`9*
`
`¢+¢¢
`. ‘++
`figfifig£§¢
`¢
`+*¢¢++++¢«
`
`Qwflgfi
`t¢¢¢¢t¢§¢
`r &¢ ¢¢+‘+¢+¢§
`fififfifififlfihfihfifi?
`
`££fi$fi$fifi$fifififi
`
`
`Vflflfiflflflflfififlflflfifi
`
`sauna
`r¢¢ ‘
`O
`?
`p.
`Q
`5+4¥Q
`»;¢ Q
`O)-
`4}
`5;d¥b+¢£fl+4¥%¢¢dfi+++o+i
`
`
`
`
`
`
`
`
`
`
`
`FIG.11
`
`3#
`
`F I f
`
`pf
`
`714
`
`720
`
`
`
`
`
`dfiflflW
`iflflflfifi?
`¢¢¢¢«
`¢¢¢v¢¢
`a
`>
`Q
`+¢++i
`+¢¢h++
`¢‘§¢‘¢+‘oo¢+¢¢«
`4
`
`
`
`§
`
`
`4 ¢h¢4
`¢+¢¢¢¢¢¢o¢o¢+i
`¢++
`e
`9
`Vfiflfifihfihfiflfiflfihfififl
`Q4}flya;upQ3
`p+¢q¢¢¢‘¢+¢++¢++¢
`fifl?’¢¥¥¥%¥flflflfiflflflflflfihfififl
`
`
`oF
`4
`
`
`¢
`I‘
`,
`a
`
`
`¢
`¢
`
`
`I'
`_
`'
`4
`o
`
`
`ifl?’J¥Wflkfifififi#§¥¥¥WNflhfififi
`
`
`o #5¢+¢+¢¢¢¢§+¢¢ a;
`Q*+$%4%£55
`¢¢ ¢¢¢¢¢3
`
`
`
`v
`z.
`A
`ALA]
`.fiwfimfifldfifififififig%flfigfivvz
`
`
`A
`
`A
`
`
`
`¢ 0
`
`

`

`US. Patent
`
`May 4, 2004
`
`Sheet 11 0f 15
`
`US 6,730,540 132
`
`omw
`
`Efifiiljfll
`
`
`
`
`NH.05
`
`
`
`

`

`US. Patent
`
`May 4, 2004
`
`Sheet 12 0f 15
`
`US 6,730,540 B2
`
`V"_ y }
`
`—}'¢'4 3:At.
`03:04..0.0
`,'‘3:03 0*0’0‘01’0’01D
`
`0
`
`5VV*3.v-*4!3+:
`9"0’0".0.00.030.0
`.0’0’.0.00.0‘20:
`-.y;00'0000000.0.0.0
`0.0.0.0
`0000*0’00‘0020..0.
`',
`-00
`.00:0:00.0.00.0.0
`20‘0
`Q
`'0:00.0101’
`0 § .. ¢
`
`a'
`
`0'0‘
`r
`4.
`1.:0
`00'2
`v:0.00f
`1’
`‘,Q’0i
`‘‘20
`00*i‘0f0
`000:3:010
`
`4' §
`4.
`4
`0.0
`«9'
`4’0
`3*.
`r0:*0
`v’3':00*0*0
`0§0.0
`0‘50'1':0.000
`V‘0.
`
`.‘
`O
`O00*0
`1.,0
`V:0Q’0’0
`‘0¢0*0
`
`*
`
`

`

`US. Patent
`
`May 4, 2004
`
`Sheet 13 0f 15
`
`US 6,730,540 132
`
`
`
`

`

`US. Patent
`
`May 4, 2004
`
`Sheet 14 0f 15
`
`US 6,730,540 132
`
`3mcan
`
`
`
`
`
`.3w...%a.»_fl.“.»_§as7575.gzflfifi...$33“,0%.“.300...w......,_».u.....”.§_§.,
`§§aiuu33u5§n§§u§3r53u§5nElvfi§a§5§535§§9§3r39wf.r.9r.§135;vby§3ru3rgbfpkypfh
`
`
`§§§¢¢§¢Q¢¢OQOQO¢§OQ§¢O#00G06$4§§§fi§¢¢§¢¢¢¢¢¢§¢§+¢«;
`
`
`
`4w«wuwumumuwflwumuwuwumumuwuwuwuwumu..Mmuwnwnwnwumnwodd.0.0.o.ow“«HwnwnwHwflmowflwnwnwumuwuwu«new»?Hwflvuwuwuwuwuwwwnqu........._
`
`
`
`
`
`
`
`
`
`«35.x;xaby}.
`v¢§v¢§v*+
`
`vinPL
`
` ..
`
`
`
`+‘*‘*‘6J¢‘.‘f‘*‘‘.“.‘.“"G‘.‘fi1.,.“.".‘.‘*".1¢‘§‘¢“.‘.."‘
`
`
`+053#0594050030099300000000v21:$$_a_n¢§¢+OOO¢OOO’OQ‘OQ.G¢¢§¢¢¢¢9¢¢¢¢OO¢¢0v433%0+?+¢¢+¢J
`
`
`
`
`“.33.?.33:ta...3.”.wvvvvvvvvx
`
`3...?£15....
`,0..0..3“wagwgfivg
`
`
`
`
`
`...EEEE‘Hd-‘lullnfl‘fllfli...
`
`
`
`
`

`

`US. Patent
`
`May 4, 2004
`
`SheetlS 0f15
`
`US 6,730,540 132
`
`.uwufitw‘.............fivfiuwuwuuwuvwoi«Fran..fivLfioLQLan...WfiLaT—fiod—fiowowghm
`
`
`
`
` VommQhfi
`.
`
`
`
`
`
`
`
`rtwmfiflfifififififififiwv.§R&&?¢¢wfififififlfiWWQwawflfifiwwafiafixfifififimfififinv¢¢++o+§+¢¢+¢¢¢¢s+¢¢¢¢¢+4+¢+++¢¢+¢+oo¢+o¢+oooov900+9909.r9$¢¢¢90¢9¢+00¢9‘o0¢o¢¢¢¢¢o000009.09.00¢¢0¢oo¢¢¢¢¢¢¢¢oo¢33.
`
`aéflfldadaG€€€€€€G€€€€€€€€€€££€Qfifii43Eflfiaédaedddd€d€€€€€€€€€€€€€€€€€€€q
`
`
`
`
`
`a3tflaaaraaitllxdafieiaidddfififififififlfi3E333aaKaa§a333#233323§a333333&§&§€€v¢¢+¢0¢¢+¢o¢oo¢¢+¢oo0¢.¢0¢o¢¢4oooo09000000...goo¢¢¢o¢¢oo¢§+¢+¢¢¢¢oooo¢Aoooo¢4flo+¢+000.¢¢¢¢¢¢+¢¢ogfiooocoo¢oo3%.fio000ooooooo00woooo00009000
`
`
`0009000000009009¢¢¢¢¢¢¢¢¢0990000000900900909900000009004.
`
`:flavwéafifixpzxpfiéahéuuxwacfiepdaJfivo--omlnzfiafigufififizmaapszanuXhfinfir1€£d€€§+x€
`.rfrup...».pb.0p_p.mWHm—rwuwacw—no.9...9.9_w_K—of_.?£é¢a.»$3.374?hhfififigigs—.9400..000anE92:5.V»pom“
`
`
`
`
`
`
`ufififinflfiufifififififi¢¢o¢tgfinhfihfiv$§nhhabflnhfifl0>¢¢333§31£333???
`
`gfififiagflgfigfififlafifikfiflfifigfikK§3K$§3§§3§§K§§§§£hflfi§f§gxfi
`'1onU:.UE«’02
`.UHmWomm
`
`“gang—m.av»
`
`gluifiii‘llafiiflillin
`
`
`
`.Haflqq‘uaaflfiflalhii‘.il
`
`
`
`
`
`
`
`—v4rW¢N¢J
`
`
`
`
`
`
`
`
`
`
`

`

`US 6,730,540 B2
`
`1
`CLOCK DISTRIBUTION NETWORKS AND
`CONDUCTIVE LINES IN SEMICONDUCTOR
`INTEGRATED CIRCUITS
`
`BACKGROUND OF THE INVENTION
`
`The present invention relates to placement of clock dis-
`tribution networks and fabrication of conductive lines in
`
`semiconductor integrated circuit structures.
`FIG. 1 shows a tree-like clock distribution network 110
`
`10
`
`designed to distribute a clock signal with a minimum clock
`skew in an integrated circuit. The clock signal is received at
`a terminal 120 and distributed to terminals 130 at the leaves
`
`of tree 110. Terminals 130 are connected to inputs of circuit
`blocks 140 such as registers, flip flops, latches, logic gates,
`etc. The network tree is provided by conductive lines 150.
`The wires 150 that connect the tree nodes of each given tree
`level to the tree nodes of any given adjacent level have the
`same dimensions. Buffers (amplifiers) 160 are located at
`selected points in the tree to amplify the clock signal. In
`order to minimize the clock skew, each clock path from
`terminal 120 to a terminal 130 has the same dimensions, and
`the respective buffers 160 in each path are identical to each
`other. These rules are sometimes violated to compensate for
`different loading at different terminals 130. For example, the
`lengths or widths of individual wires 150 can be adjusted.
`FIG. 2 is a plan view of a grid type clock distribution
`network. Lines 150 form a grid, with the horizontal and
`vertical
`lines being connected together at
`the points of
`intersection. The clock signal is delivered to terminal 120 at
`the grid center, amplified by buffer 160.1, and distributed to
`buffers 160.2 at the grid edges. Each buffer 160.2 drives a
`horizontal or vertical line 150. Clock terminals 130 are
`
`positioned on lines 150 and connected to circuit blocks such
`as blocks 140 of FIG. 1.
`Other clock distribution networks are also known. For
`
`example, the tree and grid networks can be combined. A
`circuit block 140 of FIG. 1 can be replaced with a grid
`network or a local clock generation circuit. See US. Pat. No.
`6,311,313 entitled “X-Y GRID TREE CLOCK DISTRIBU-
`TION NETWORK WITH TUNABLE TREE AND GRID
`
`NETWORK ” issued Oct. 30, 2001 to Camporese et al.,
`incorporated herein by reference.
`A perfect placement of a clock distribution network on a
`semiconductor die can be difficult due to the presence of
`other circuitry. A modern integrated circuit may include up
`to eight metal layers. The clock distribution network uses
`one of these layers for lines 150. Another metal
`layer,
`underlying the lines 150, is used for a ground plane or a
`ground grid to shield the underlying circuitry from the
`electromagnetic field generated by high frequency clock
`signals on lines 150. These two layers are separated by a
`dielectric. The speed of signal propagation along the clock
`distribution network is affected by the capacitance between
`the lines 150 and the ground plane or grid. The capacitance
`is not uniform across the integrated circuit due to local
`variations of the dielectric thickness and the capacitive
`coupling between the lines 150 and other nearby switching
`lines. As a result, it is difficult to control the impedance of
`lines 150 and therefore the clock propagation speed.
`Further, the ground plane or grid consumes valuable area,
`increases the cost and complexity of the integrated circuit,
`and sometimes does not completely eliminate the electro-
`magnetic interference problem because the position of the
`ground plane or grid can be restricted to allow the same
`metal layer to be used for other circuit elements.
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`2
`In FIG. 3, the clock distribution network is removed from
`die 310 containing the clocked circuitry, and placed on a
`separate (“secondary”) die 320. The dies 310 and 320 are
`bonded together in a flip chip manner with solder balls 321.
`The two dies are offset from each other so that each die has
`
`contact pads not covered by the other die. These contact pads
`are shown as pads 322 on die 310 and pads 323 on die 320.
`Pads 322, 323 are connected to external circuitry (not
`shown) with solder balls 313. Alternatively, die 320 can be
`made larger than die 310 to make room for contact pads 323.
`See US. Pat. No. 6,040,203 entitled “CLOCK SKEW
`MINIMIZATION AND METHOD FOR INTEGRATED
`
`CIRCUITS”, issued Mar. 21, 2000 to Bozso et al., incorpo-
`rated herein by reference.
`SUMMARY
`
`The invention is defined by the appended claims which
`are incorporated into this section by reference. Some fea-
`tures of the invention are summarized immediately below.
`The inventor has observed that in the structure of FIG. 3
`
`significant electromagnetic interference, as well as parasitic
`capacitance, can be associated with the transfer of signals
`and power and ground voltages between contact pads 322,
`323 and circuit blocks in dies 310 and 320. The signal,
`power, and ground paths between contact pads 322 and
`blocks 140 go through conductive lines 324. The signal,
`power and ground paths between contact pads 323 and
`circuit 310, and the paths between contact pads 323 and
`circuitry 325 in die 320, go through conductive lines 326.
`Depending on the layout, the lines 324, 326 can be parallel
`to lines 150, or make small angles with lines 150. The small
`angles when combined with small spacing between a line
`324 or 326 and a line 150 may lead to significant electro-
`magnetic interference and parasitic capacitance.
`In some embodiments of the invention, some or all of the
`contact pads 323, and at least a contact pad that serves as the
`input terminal of the clock distribution network, are moved
`to the bottom of die 320. The bottom contact pads 323 are
`connected to circuitry at the top of the die by means of
`conductive features forming large angles (e.g. 90°) with the
`top and bottom surfaces of die 310. Since large portions of
`lines 150 extend along the top surface of die 310,
`the
`electromagnetic interference and the parasitic capacitance
`can be reduced.
`
`In some embodiments, contact pads 322 are omitted. The
`conductive paths to and from die 310 are through die 320.
`Further reduction of the electromagnetic interference and the
`parasitic capacitance can be achieved as a result. Also, the
`structure occupies less area.
`The bottom contact pads on die 320 can be bonded to
`contact pads on another integrated circuit or a wiring sub-
`strate. In this case, the die 320 serves as a semiconductor
`“interposer” positioned between die 310 and other integrated
`circuits or between die 310 and a wiring substrate.
`Die 320 may include ground planes or grids or other
`grounded lines to shield the circuitry above and below the
`interposer from the clock distribution network.
`In another embodiment, several interposers are provided,
`with different parts of a clock distribution network on
`different interposers.
`In some embodiments, the clock distribution lines 150
`(FIGS. 1, 2) are formed in trenches etched in a semicon-
`ductor substrate. The RC value of lines 150 can be lowered
`
`by making the trenches deeper, without increasing the lateral
`area occupied by the RC lines. Also, the RC value, and hence
`the clock skew, become more controllable.
`
`

`

`US 6,730,540 B2
`
`3
`Other conductive lines, not belonging to the clock distri-
`bution network, can be formed in such trenches.
`Other embodiments and variations are described below.
`
`The invention is defined by the appended claims.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIGS. 1 and 2 are plan views that illustrate prior art clock
`distribution networks.
`
`FIG. 3 is a side view illustrating a prior art structure.
`FIGS. 4 and 5 are cross sectional views of embodiments
`
`of the present invention.
`FIG. 6 is a schematic diagram illustrating an embodiment
`of the present invention.
`FIGS. 7 and 8 are cross sectional views of some embodi-
`
`ments of the present invention.
`FIG. 9 is a top view of an embodiment of the present
`invention.
`FIGS. 10—11 are cross sectional views of some embodi-
`
`ments of the present invention.
`FIG. 12 is a side view of one embodiment of the present
`invention.
`FIG. 13 is a cross sectional view of one embodiment of
`
`the present invention.
`FIG. 14A is a side view of one embodiment of the present
`invention.
`FIG. 14B is a bottom view of the structure of FIG. 14A.
`
`FIGS. 15A—15D, 16, 17A—17D are cross sectional view
`of embodiments of the present invention in the process of
`fabrication.
`
`DESCRIPTION OF SOME EMBODIMENTS
`
`The examples in this section are provided for illustration
`and not to limit the invention. The invention is not limited
`
`to particular circuits, materials, processes, process
`parameters, equipment, or dimensions.
`FIG. 4 illustrates an integrated circuit 310 mounted on
`another integrated circuit 320 which in turn is mounted on
`a wiring substrate 330. Each of circuits 310, 320 is a
`semiconductor die or wafer, or some portion of a semicon-
`ductor wafer. Circuit 310 includes clocked circuitry 140 and
`may also include non-clocked circuitry. For example, circuit
`310 may include a microprocessor, a memory, a digital
`controller, and so on. Circuit 320 is an interposer that
`contains clock distribution networks 110. The clock distri-
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`bution networks can be of any type, including the types
`shown in FIGS. 1, 2, or other types, known or to be invented.
`Circuit 310 includes a semiconductor substrate 340.
`
`50
`
`Active areas 340A may have been formed in substrate 340
`for transistors, resistors, capacitors, interconnect lines, or
`other circuit elements. Interposer 320 includes a semicon-
`ductor substrate 350. Conductive lines 150 have been
`
`layers deposited over
`formed from one or more metal
`substrate 350 and insulated from the substrate by insulating
`layers. An insulating layer may include one or more dielec-
`tric layers, a stack of dielectric and semiconductor layers,
`and other insulating structures, known or to be invented.
`Alternatively, lines 150 can be formed from diffused (doped)
`areas of substrate 350, or a combination of metal layers and
`diffused areas, or from other conductive materials, using any
`suitable techniques, known or to be invented. Some tech-
`niques for forming the lines 150 are described below with
`respect to FIGS. 8—11. Clock terminals 130 (the outputs of
`the clock distribution networks) are contact pads formed at
`the top surface of interposer 320. Clock input terminals 120
`
`55
`
`60
`
`65
`
`4
`are provided by contact pads 323 located at the bottom
`surface of interposer 320. The clock terminals are inputs to
`clock distribution networks. Holes 360 pass through sub-
`strate 350 between its top and bottom surfaces. Conductive
`features are formed in through holes 360 to connect the
`clock input terminals 120, and possibly other terminals 323
`at
`the bottom of interposer 320,
`to contact pads and/or
`circuitry at the top of the interposer. The conductive features
`are insulated from substrate 350 by dielectric 370. Suitable
`techniques for forming such conductive features are
`described in US. Pat. No. 6,322,903 issued Nov. 27, 2001
`to O. Siniaguine et al. and incorporated herein by reference.
`Other techniques, known or to be invented, can be also used.
`The conductive features can be metal plugs or thin films
`deposited over sidewalls of holes 360 over dielectric 370.
`The conductive features can be perpendicular to the top and
`bottom surfaces of circuit 320 or substrate 340, or the
`conductive features can form large angles with these sur-
`faces. These angles are at least 80° in some embodiments, or
`at least 45°, or at least 30°. Other angles are possible.
`Circuit 310 is bonded to interposer 320 in a flip chip
`manner, with the active areas 340A at the bottom of substrate
`340. Contact pads 374 on the bottom of circuit 310 are
`bonded to contact pads on the top of circuit 320. Some of
`contact pads 374 are inputs of circuit blocks 140 (FIG. 1).
`These contact pads 374 are bonded to pads 130. Other
`contact pads 374 are bonded to other contact pads 380 at the
`top of interposer 320. Contact pads 380 can be connected, by
`conductive features in holes 360, to contact pads 323 (i.e.
`contact pads 323.1, 323.2, 323.3 etc.) on the bottom of
`interposer 320. In one example, contact pad 323.1 is a power
`supply input. Contact pad 323.3 is a ground input. Contact
`pad 323.2 an input, output, or input/output terminal for a
`signal. The invention is not limited to any particular signals
`that can be routed through interposer 320.
`Contact pads 323 are bonded to pads 388 on wiring
`substrate 330.
`
`The bonding of circuit 310 to interposer 320 can be
`accomplished with solder, thermocompression, conductive
`or anisotropic adhesive, or any other technique, known or to
`be invented. The same techniques, or other techniques, can
`be used to bond the contact pads 323 to pads 388.
`Active areas 340A may be positioned at the top of circuit
`310. Circuit 310 may include contact pads both at the top
`and at the bottom, with through holes going through sub-
`strate 340 to provide suitable interconnections. Other inte-
`grated circuits (not shown), including other interposers, can
`be bonded to contact pads on top of circuit 310. See the
`aforementioned US. Pat. No. 6,322,903. These other inte-
`grated circuits may contain parts of clock distribution net-
`works. The integrated circuits may be bonded to each other
`in any configurations, not necessarily in a stack one above
`the other. For example, multiple circuits 310 can be bonded
`side by side to the top surface of interposer 320. Multiple
`interposers may be present, and they may contain different
`parts of clock distribution networks, or different clock
`distribution networks.
`
`FIG. 5 shows a similar structure but with interposer 320
`containing a ground structure 390. Structure 390 can be a
`ground plane, i.e. a conductive feature that is wider than a
`line 150. Structure 390 can be a ground grid (a grid of
`grounded conductive lines) or may consist of just a few
`(possibly one) grounded lines. Structure 390 may include
`multiple ground planes or grids. Structure 390 shields the
`circuit 310 from noise generated by the clock distribution
`networks. Structure 390 can be formed from a metal layer or
`
`

`

`US 6,730,540 B2
`
`5
`layers overlying the lines 150. Structure 390 is connected to
`contact pad 323.3 and is insulated from lines 150 by
`dielectric. Structure 390 is interrupted to make room for
`contacts 394 that connect contact pads 130, 380 at the top of
`interposer 320 to lines 150 and other features in the inter-
`poser. Ground structure 390 may extend over almost all of
`substrate 350, or at least almost all of the clock distribution
`networks.
`
`In some embodiments, structure 390 is held at a constant
`non-ground voltage.
`Due to the presence of shielding structure 390, it is less
`important to have a ground plane in circuit 310. The number
`of metal layers in circuit 310 can therefore be reduced. The
`incremental cost of each additional metal layer increases
`with the total number of metal layers in an integrated circuit,
`so moving a ground plane from circuit 310 to circuit 320
`may reduce the total manufacturing cost.
`As shown in FIG. 5, active areas 350A may be formed in
`substrate 350 for transistors or other elements of “clock
`
`headers” 160 (such as shown in FIGS. 1, 2). Clock headers
`160 can be amplifiers, clock dividers or multipliers, phase
`shifters, or other clock circuitry. In the example of FIG. 5,
`active areas 350A are located at the top surface of substrate
`350, but this is not necessary. Similar active areas and clock
`headers can be formed in the structure of FIG. 4.
`
`Placing the ground structure 390 on the interposer rather
`than on circuit 310 reduces the capacitive coupling between
`the ground structure and circuit elements of circuit 310
`because the ground structure becomes father from the circuit
`elements of circuit 310. The capacitive coupling and elec-
`tromagnetic interference between the ground structure and
`the conductive features in holes 360 is small because the
`
`ground structure and the conductive features in holes 360 are
`at an angle (near 90°) to each other.
`the
`If a ground structure is provided in circuit 310,
`capacitive coupling and the electromagnetic interference
`between this ground structure and the conductive features in
`holes 360 are reduced for the same reason.
`
`In some embodiments, at least some contact pads 380 are
`positioned above the respective holes 360 and are connected
`to respective contact pads 323 without use of horizontal
`conductive lines. Acontact pad 380 can however be laterally
`spaced from the respective hole 360, and connected to the
`respective contact pad 323 by a combination of a conductive
`feature in the hole 360 and horizontal lines.
`
`Substrate 350 is grounded, or held at some other constant
`voltage, to shield the clock distribution networks from the
`circuitry in wiring substrate 330 and vice versa. Of course,
`the active areas 350A do not have to be grounded, but the
`grounded portion of substrate 350 extends laterally through-
`out the substrate in some embodiments.
`
`Interposer 320 may contain only a part of a clock distri-
`bution network. For example, interposer 320 may contain
`only a sub-tree 1108 (FIG. 6) of a tree network 110. Sub-tree
`1108 consists of a number of tree levels including the root
`120. The rest of network 110 may be in circuit 310.
`In FIG. 7, interposer 320 contains an additional ground
`structure 510. This may be a ground plane or grid or any
`other type similar to structure 390. Ground structure 510 is
`located between clock distribution lines 150 and substrate
`350.
`In some embodiments, structure 510 is held at a
`constant non-ground voltage. Substrate 350 is not necessar-
`ily held at a constant voltage.
`In some embodiments, interposer 320 contains only the
`clock distribution network or networks, so its fabrication is
`
`5
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`6
`interposer
`relatively inexpensive. In other embodiments,
`320 also contains decoupling capacitors, diodes, resistors,
`transistors, and other elements. In some embodiments, the
`fabrication yield of the entire structure is increased because
`the fabrication of the clock distribution network does not
`
`have to be integrated with the fabrication of circuit 310
`except at the packaging stage.
`FIG. 8 is a cross sectional view illustrating fabrication of
`lines 150 in one embodiment. Trenches 610 are etched in
`substrate 350. Dielectric film 620 is formed on the substrate.
`
`Dielectric 620 covers the trench surfaces. Then a metal layer
`624, e.g. tungsten, aluminum or copper, is deposited to fill
`the trenches and possibly cover the substrate. If metal 624
`covers the substrate, the metal is removed from above the
`substrate by chemical mechanical polishing (CMP), electro-
`chemical polishing, etching, or some other method. The
`trenches remain filled with metal 624, which provides the
`lines 150. The trenches may form a tree or grid network as
`in FIG. 1 or 2, or some other network. Metal 624 provides
`a corresponding conductive network.
`In so