Ulllted States Patent [19]
`Bellaar et al.
`
`US006002168A
`[11] Patent Number:
`[45] Date of Patent:
`
`6 002 168
`9
`9
`Dec. 14, 1999
`
`[54] MICROELECTRONIC COMPONENT WITH
`RIGID INTERPOSER
`
`[75] Inventors: Pieter H_ Bellaar, Baambruggc,
`
`5,152,695 10/1992 Grabbe et al. .......................... .. 439/71
`5,173,055 12/1992 Grabbe ......... ..
`439/66
`5,433,822
`7/1995 Mimura et al. .
`257/737
`5,518,964
`5/1996 D1Stefan0 et al
`438/113
`
`
`
`
`
`Netherlands, Thomas HI Distefano Monte Serene, Calif‘; Joseph Fjelstad, Sunnyvale, Calif‘; Christopher M-
`
`,
`
`,
`
`/
`
`
`
`......................... .. Kovac 8.1. garlnztisilnta ............................. .. ]e s a ................................. ..
`
`
`
`
`
`/
`
`Pickett, Dublin, Calif; John W. Smith,
`
`OTHER PUBLICATIONS
`
`Palo Alto, Calif.
`
`[73] Assignee; Tessera, Inc” San Jose, Calif
`
`_
`[21] Appl' NO" 08/978’082
`[22] Filed;
`Nov_ 25, 1997
`[51]
`Int. Cl.6 ......................... .. H01L 23/48; H01L 23/06;
`H01L 23/52
`
`U-S. Cl. ........................ ..
`257/705
`_
`[58] Fleld 0f Search ................................... .. 257/669, 737,
`257/738> 693> 696> 783> 48> 668> 778> 688>
`705> 700> 695
`
`[56]
`
`_
`References Clted
`U_S_ PATENT DOCUMENTS
`
`3,303,393
`3,952,404
`
`5,148,265
`5,148,266
`
`_
`2/1967 Hymes -
`....................... .. 59/589
`4/1976 Matunami .....
`1124;212:1305) et a '
`257/668
`9/1992 Khandros et a1.
`9/1992 Khandros et al. .................... .. 257/668
`
`_
`
`_
`
`_
`
`_
`
`IMB Technical Dlsclosure Bulletin, “Ch1p Column Package
`Structure”, vol. 40 No. 08 Aug. 1997. p 117 (257/696).
`
`Primar Examiner—Mahshid Saadat
`y
`Assistant Examiner—Jhihan B. Clark
`lgtrtsrnheyi ggi‘jl’ll, H01: I17Ii';l')m—Lerner, David, Littenberg,
`
`H1 0 Z
`
`ent ,
`
`[57]
`
`ABSTRACT
`
`Substrate,
`Amicroelectronic Component for mounting a
`such as a hybrid circuit to a rigid support substrate, such as
`a printed circuit board The microelectronic component
`includes a rigid interposer Which may have a chip mounted
`on its ?rst surface; a pattern of contacts on the rigid
`interposer; a ?exible interposer overlying the second surface
`of the rigid interposer; a pattern of terminals on the ?exible
`interposer; ?exible leads; and solder coated copper balls
`mounted on the ?exible interposer. The microelectronic
`component may have a socket assembly mounted on the ?rst
`Surface of the rigid interposer‘ The microelectronic compo_
`nent may be mounted on a rigid support substrate.
`
`48 Claims, 1 Drawing Sheet
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`U.S. Patent
`
`Dec. 14,1999
`
`6,002,168
`
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`
`1
`MICROELECTRONIC COMPONENT WITH
`RIGID INTERPOSER
`
`6,002,168
`
`2
`balls. One solid core solder ball is provided betWeen each
`contact on the chip and each contact pad on the substrate.
`Although these connections Work Well for small devices,
`With larger devices, the rigid connections provided by the
`solid core solder balls tend to crack at the soldered junctions
`betWeen the balls and the opposing surfaces. Warpage or
`distortion of the chip or substrate, furthermore, make it
`dif?cult to engage all of the solid core solder balls betWeen
`the chip and substrate simultaneously, or to engage all of the
`solid core solder balls betWeen the chip and a test ?xture.
`Although it is desirable to use solid core solder balls to
`interconnect a hybrid circuit to a printed circuit board, such
`an interconnection Would be subject to similar problems.
`The electrical poWer that is dissipated When a microelec
`tronic device is in operation tends to heat up that device.
`When the device is no longer in operation, it tends to cool
`doWn. Over a period of time, the device tends to undergo a
`number of heating up and cooling doWn cycles as the device
`is repeatedly turned on and off. These cycles, Which cause an
`associated expansion and contraction of the device, are
`commonly referred to as “thermal cycling”.
`A device in Which a hybrid circuit is bonded to a printed
`circuit board using solid core solder balls Would be subject
`to substantial strain, caused by thermal cycling, during
`operation of the device. Electrical poWer dissipated Within
`the hybrid circuit during operation Would tend to heat up the
`hybrid circuit and, to a lesser extent, the printed circuit
`board. The temperature of the hybrid circuit, therefore, and,
`to a lesser extent, the printed circuit board Would rise each
`time the device is turned on and fall each time the device is
`turned off. Since the hybrid circuit and the printed circuit
`board are normally constructed from different materials
`having different coef?cients of thermal expansion, the
`hybrid circuit and printed circuit board Would normally
`expand and contract by different amounts. This is commonly
`referred to as a “thermal mismatch”. The thermal mismatch
`causes the electrical contacts on the hybrid circuit to move
`relative to the electrical contact pads on the printed circuit
`board as the temperature of the hybrid circuit and printed
`circuit board change. The relative movement Would deform
`the electrical interconnections betWeen the hybrid circuit
`and the printed circuit board and place them under mechani
`cal stress. Since these stresses Would be applied repeatedly
`With repeated operation of the device, they Would cause
`breakage of the electrical interconnections. Thermal cycling
`stresses may occur even Where the hybrid circuit and printed
`circuit board are formed from like materials having similar
`coef?cients of thermal expansion. This is because the tem
`perature of the hybrid circuit may increase more rapidly than
`the temperature of the printed circuit board When poWer is
`?rst applied to the hybrid circuit. Unfortunately, solid core
`solder balls are neither ?exible nor strong enough to With
`stand the strain generated by differential rates of thermal
`expansion.
`Commonly assigned US. Pat. Nos. 5,148,265; 5,148,266;
`5,518,964; and 5,659,952; and patent application Ser. No.
`08/365,747, ?led on Dec. 29,1994, the speci?cations of
`Which are incorporated by reference herein, provide sub
`stantial solutions to the problems of thermal stresses and
`component testing. Nonetheless, still further improvement is
`desirable.
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`The present invention relates to the art of electronic
`packaging, and more speci?cally to components useful for
`mounting and/or testing semiconductor chips and related
`electronic components. The present invention also relates to
`semiconductor chip assemblies and electronic devices incor
`porating such components.
`2. Description of the Related Art
`Modern electronic devices utiliZe semiconductor
`components, commonly referred to as “integrated circuits”
`Which incorporate numerous electronic elements. These
`chips are mounted on substrates that physically support the
`chips and electrically interconnect each chip With other
`elements of the circuit. The substrate may be part of a
`discrete chip package, such as a single chip module or a
`multi-chip module, or may be a circuit board. The chip
`module or circuit board is typically incorporated into a large
`circuit. An interconnection betWeen the chip and the chip
`module is commonly referred to as a “?rst level” assembly
`or chip interconnection. An interconnection betWeen the
`chip module and a printed circuit board or card is commonly
`referred to as a “second level” interconnection. In “chip on
`board” packaging, the chip is mounted directly on the
`printed circuit board. This type is interconnection has been
`referred to as a “11/2 level” interconnection.
`One relatively common packaging scheme is called a
`“hybrid circuit”. A hybrid circuit typically contains a semi
`conductor chip that has been mounted and electrically
`interconnected to a circuit that has been formed on a thin
`layer of a rigid ceramic material. The method used to
`electrically interconnected the chip to the circuit is generally
`any of the methods that are knoWn for use in ?rst level
`bonding, such as Wire bonding, tab bonding and ?ip chip
`bonding. In some cases it is desirable to mount and electri
`cally interconnect the hybrid circuit to a printed circuit
`board. Solder is typically used to form the interconnection.
`It is dif?cult, hoWever, to reWork a hybrid circuit that has
`been soldered to a printed circuit board. In order to reWork
`the assembly, the hybrid circuit must be removed from the
`printed circuit board. When the hybrid circuit is separated
`from the printed circuit board, part of the solder mass is
`removed from the contacts on the hybrid circuit. Non
`uniform partial solder masses remain on the hybrid circuit
`contacts, the printed circuit board or both. When the hybrid
`circuit is resoldered to the printed circuit board, the non
`uniform partial solder masses can cause short circuits and
`alignment problems.
`Another problem associated With the assembly process is
`testing. In a typical assembly process, each hybrid circuit is
`tested before it is soldered to a printed circuit board. Testing
`involves clamping the hybrid circuit to a socket to engage
`the solder balls of the hybrid circuit With the test contacts of
`the test assembly. When the solder balls are engaged With the
`test contacts, the solder tends to creep and to deform,
`especially if the hybrid circuit is equipped With high-lead
`solder. The testing process, like the reWork process, can lead
`to short circuit and alignment problems. To overcome these
`problems, it is desirable to use solid core solder balls to
`interconnect the ceramic substrate to a printed circuit board.
`In US. Pat. No. 3,303,393, Which issued on Feb. 7, 1967,
`Hymes et al. disclose a semiconductor chip assembly With
`?ip-chip connections Which incorporates copper core solder
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`SUMMARY OF THE INVENTION
`
`65
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`One aspect of the present invention provides a ?exible
`chip carrier. The ?exible chip carrier of this aspect of the
`present invention includes a rigid interposer having ?rst and
`
`

`
`3
`second surfaces. The rigid interposer is preferably adapted to
`mount and electrically connect a semiconductor chip onto
`the ?rst surface of the rigid interposer. An interconnection
`betWeen the rigid interposer and a semiconductor chip is a
`“?rst level” interconnection. The rigid interposer may be
`adapted to interconnect a semiconductor chip using any of
`the knoWn methods of creating “?rst level” interconnec
`tions. Some conventional “?rst level” interconnection meth
`ods include Wire bonding, tape-automated bonding and
`?ip-chip bonding. The second surface contains a plurality of
`contacts disposed in a pattern. The area encompassed by the
`contacts is de?ned as a “contact pattern area”. The rigid
`interposer is preferably a thin, sheet-like layer material. The
`rigid interposer may be composed of any rigid dielectric
`material. Preferred rigid dielectric materials include ceramic
`materials, such as alumina, beryllia, silicon carbide, alumi
`num nitride, forsterite, mullite, and glass-ceramics; compos
`ite materials, such as polyester/?berglass, polyimide/
`?berglass, and epoxy/?berglass; and silicon. More preferred
`rigid dielectric materials are the ceramic materials listed
`above. The preferred ceramic material is alumina. On pre
`ferred embodiments, the rigid interposer contains an elec
`trical circuit. Although the coef?cient of thermal expansion,
`hereinafter “CTE”, of the rigid interposer is generally
`greater than the CTE of a semiconductor chip and generally
`less than the CTE of an epoxy-polyimide printed circuit
`board, the CTE of the rigid interposer may be roughly equal
`to the CTE of the semiconductor chip. This is because other
`sub-components of the present invention, speci?cally the
`?exible interposer and/or the optional compliant layer can
`compensation for the CTE mismatch betWeen chip and the
`rigid interposer and the CTE mismatch betWeen the rigid
`interposer and the ?exible interposer.
`The ?exible chip carrier also includes a ?exible interposer
`that overlies the second surface of the rigid interposer. The
`?exible interposer has a top surface that faces toWard the
`second surface of the rigid interposer, and a bottom surface
`that does not. The ?exible interposer preferably is a thin,
`?exible sheet of a polymeric material such as polyimide, a
`?uoropolymer, a thermoplastic polymer or an elastomer. In
`preferred embodiments, the ?exible interposer contains an
`electrical circuit. The ?exible interposer may have one or
`more apertures, extending from the top surface of the
`?exible interposer to the bottom surface.
`Aplurality of electrically conductive terminals is disposed
`on the ?exible interposer in a pattern on at least one surface
`selected from the group consisting of the top surface and the
`bottom surface. In preferred embodiments, either all of the
`terminals disposed on the top surface or all of the terminals
`are disposed on the bottom surface of the ?exible interposer.
`At least some of the terminals, and preferably most or all of
`the terminals, are disposed Within the area of the ?exible
`interposer overlying the contact pattern area on the rigid
`interposer. Generally, each terminal is associated With one
`contact on the rigid interposer.
`The ?exible chip carrier also includes a plurality of
`electrically conductive leads connecting at least some of the
`contacts on the rigid interposer With at least some of the
`terminals on the ?exible interposer. Each lead has a contact
`end connected to the associated contact on the rigid inter
`poser and a terminal end connected to the associated termi
`nal on the ?exible interposer. The leads and the ?exible
`interposer are constructed and arranged so that the contacts
`ends of the leads are moveable relative to the terminals at
`least to the extent required to compensate for differential
`thermal expansion betWeen the components. The intercon
`nection betWeen the contacts on the rigid interposer and the
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`6,002,168
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`4
`terminals on the ?exible interposer is a second “?rst level”
`interconnection. The leads are preferably ?exible so that the
`terminals are moveable With respect to the contacts to
`accommodate movement caused by differential thermal
`expansion.
`The ?exible interposer is ?exible to facilitate movement
`of the contact ends of the leads relative to the terminals and
`thus to contribute to the ability of the chip carrier to
`Withstand thermal cycling. Each ?exible lead may extend
`through an aperture in the ?exible interposer. The ?exible
`leads may be formed integrally With the terminals on the
`?exible interposer, or else may be separately formed ?ne
`Wires. Preferably, the leads are curved to provide increased
`?exibility. The leads may be generally S-shaped. Each lead
`may be formed from a ribbon of conductive materials having
`oppositely-directed major surfaces, the ribbon being curved
`in directions normal to its major surfaces to form a curved
`con?guration of the lead In a preferred embodiment, the lead
`is S-shaped.
`Some preferred arrangements of leads connecting the
`contacts to the terminals include a “fan-in”, “fan-out”,
`“fan-in/fan-out”, and area array. In a “fan-in” arrangement,
`the contacts on the rigid interposer are typically disposed on
`the periphery of the rigid interposer. The terminals are
`generally disposed inside the region that overlies the region
`bounded by the contacts on the rigid interposer. The leads
`connecting the terminals to the associated contacts fan
`inWardly. In a “fan-out” arrangement, the contacts on the
`rigid interposer are again generally disposed on the periph
`ery of the rigid interposer, and the terminals on the ?exible
`interposer are generally disposed in a region that is outside
`the region that overlies the region bounded by the contacts.
`The leads connecting the terminals to the associated contacts
`fan outWardly. In a “fan-in/fan-out” arrangement, some
`terminals on the ?exible interposer are disposed inside the
`region bounded by the contacts and some are disposed
`outside the region. Some leads, therefore, fan-in and some
`fan-out. The rigid interposer contacts typically are disposed
`in single roWs and columns on the second surface and the
`leads are interdigitated. By the term “interdigitated”, it is
`meant that fan-in and fan-out leads are interspersed With one
`another. The preferred interdigitated fan-in/fan-out arrange
`ment is Where each lead that is adjacent to a fan-in lead is
`a fan-out lead and each lead that is adjacent to a fan-out lead
`is a fan-in lead. In an “area array” arrangement, the contacts
`on the rigid interposer may be disposed on the periphery of
`the rigid interposer or may be disposed in a so called area
`array, i.e., a grid like pattern covering all or a substantial
`portion of the bottom surface of the rigid interposer. For the
`leads to be in an area array arrangement, hoWever, the
`terminals on the ?exible interposer must be disposed in area
`array.
`The ?exible chip carrier further includes a plurality of
`joining units, each-including a solid core Which is preferably
`spherical. Each joining unit is disposed on the bottom
`surface of the ?exible interposer, is electrically intercon
`nected to one terminal, and extends doWnWardly from such
`terminal. If any terminals are disposed on the bottom surface
`of the ?exible interposer, one of said joining units is pref
`erably disposed directly on each of such terminals. The solid
`cores are preferably electrically conductive. Preferably, the
`solid cores are made from copper or nickel.
`The ?exible chip carrier also includes a unit bonding
`material. The unit bonding material extends betWeen the
`terminal and the solid core. Preferably, the unit bonding
`material is standard lead/tin solder and is provided as a part
`of the joining unit, as a coating extending over the solid core.
`
`

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`6,002,168
`
`5
`The unit bonding material may be used to bond the ?exible
`chip carrier to a printed circuit board or another support
`substrate.
`The ?exible chip carrier may also include a compliant
`layer covering the ?exible leads in Whole or in part. The
`compliant layer comprises a dielectric material having a loW
`modulus of elasticity, such as an elastomeric material.
`Preferred elastomeric materials include silicones, ?exibliZed
`epoxies, and thermoplastics. Silicone elastomers are particu
`larly preferred. The dielectric material may be provided in
`the form of a layer, With holes in the layer aligned With the
`terminals on the ?exible interposer. In preferred
`embodiments, the compliant layer is formed in at least a tWo
`step process. The ?rst step involves dispensing a controlled
`amount of a thixotropic or non-slumping silicone elastomer
`on a portion, but not all, of the bottom surface of the rigid
`interposer and/or a portion, but not all, of the ?rst surface of
`the ?exible interposer, to create a compliant spacer. The
`compliant spacer controls the separation betWeen the rigid
`interposer and the ?exible interposer. The second step
`involves dispensing a second silicone elastomer over the
`thixotropic or non-slumping silicone elastomer. Compliant
`spacers and their use in microelectronic assemblies is more
`fully described in commonly assigned, US. Pat. No. 5,659,
`952, the speci?cation of Which is hereby incorporated by
`reference.
`One aspect of the present invention provides a semicon
`ductor chip assembly. The semiconductor chip assembly of
`the present invention includes the ?exible chip carrier
`described above and at least one semiconductor chip that has
`been connected to the ?rst surface of the rigid interposer of
`the ?exible chip carrier. The semiconductor chip assembly
`of the present invention may contain a plurality of semicon
`ductor chips.
`If the semiconductor chip assembly contains a plurality of
`chips, each chip is mounted on and electrically intercon
`nected to the rigid interposer of the ?exible chip carrier.
`Such assemblies may be referred to as multichip modules.
`Such a multichip module may, for example, comprise a
`monolithic microWave integrated circuit and a high fre
`quency digital integrated circuit on one rigid interposer that
`is part of a ?exible chip carrier. If both of these high
`frequency elements are on one rigid interposer, the high
`frequency elements of the circuit can be isolated from the
`loWer frequency elements. In another embodiment, an inte
`grated circuit in the form of a central processing unit,
`sometimes referred to as a “cpu”, and one or more memory
`chips may be mounted on a rigid interposer of the present
`?exible chip carrier to form a semiconductor chip assembly
`of the present invention. Such an assembly Would also be a
`multichip module.
`Preferred methods of connecting the one or more semi
`conductor chips to the ?exible chip carrier include
`Wirebonding, ?ip chip bonding and tab bonding, With Wire
`bonding and ?ip chip bonding being more preferred. If the
`semiconductor chip is to be Wire bonded, the rigid interposer
`should have as plurality of electrically conductive pads
`disposed in a ring-like pattern. The chip is secured to the ?rst
`surface of the rigid interposer at the center of the ring-like
`pattern, so that the contact pads on the rigid interposer
`surround the chip. The chip is mounted on the ?rst surface
`of the rigid interposer. The chip is mounted on the rigid
`interposer in a face-up disposition, With the back surface of
`the chip confronting the ?rst surface of the rigid interposer,
`and With the front surface of the chip facing upWardly, aWay
`from the rigid interposer so that the electrical contacts on the
`front surface of the chip are exposed. Fine Wires are con
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`6
`nected betWeen the electrical contacts on the front surface of
`the chip and the contact pads on the ?rst surface of the rigid
`interposer. These Wires extend outWardly from the chip to
`the surrounding contact pads on the ?rst surface of the rigid
`interposer.
`If the semiconductor chip is to be connected to the rigid
`interposer using ?ip chip technology, the electrical contacts
`on the front surface of the chip are provided With bumps of
`solder. The ?rst surface of the rigid interposer should include
`a plurality of contact pads arranged in an array correspond
`ing to the array of electrical contacts on the chip. The chip,
`With the solder bumps, is inverted so that its front surface
`faces toWards the ?rst surface of the rigid interposer, With
`each electrical contact and solder bump on the chip being
`positioned on the appropriate contact pad on the ?rst surface
`of the rigid interposer. The assembly is then heated so as to
`liquefy the solder and, upon resolidi?cation of the solder,
`bond each contact on the chip to the confronting contact pad
`on the ?rst surface of the rigid interposer.
`The semiconductor chip assembly of the present invention
`has at least tWo “?rst level” interconnections in the ?exible
`chip carrier. The ?rst “?rst level” interconnection is the
`interconnection betWeen the semiconductor chip and the
`rigid interposer and second “?rst level” interconnection is
`the interconnection betWeen the rigid interposer and the
`?exible interposer.
`Another aspect of the present invention provides a test
`assembly for semiconductor chips. Current semiconductor
`chip manufacturing techniques do not result in 100% yields,
`some chips, therefore, Will be defective. Often, the defect
`can not be detected until the chip is operated under poWer in
`a test ?xture or in an actual assembly. A single bad chip can
`make a larger assembly, Which may include other chips or
`other valuable components, Worthless, or can require pains
`taking procedures to extricate the bad chip from the assem
`bly. The chips and the mounting components used in a
`semiconductor chip assembly should, therefor, permit test
`ing of the chips and replacement of the chips before the
`chips are fused to a substrate.
`Semiconductor chips can be tested in the test assembly of
`the present invention. The test assembly of this aspect of the
`present invention includes the ?exible chip carrier as
`described above. The test assembly further includes a sheet
`socket assembly or connector. Preferred sheet socket assem
`blies and connectors are those described in commonly
`assigned US. Pat. No. 5,615,824; US. Pat. No. 5,632,631;
`US. patent application Ser. No. 08/254,991, ?led on Jun. 7,
`1994; and US. patent application Ser. No. 08/862,151, ?led
`on May 22, 1997, the speci?cations of Which are incorpo
`rated by reference herein.
`In preferred embodiments, the sheet socket component or
`connector includes a planar or sheet like dielectric body
`having ?rst and second major surfaces and also having a
`plurality of holes open to the ?rst major surface. The second
`major surface faces toWard the ?rst surface of the rigid
`interposer of the ?exible chip carrier. The holes are disposed
`in an array corresponding to an array of bumped leads on a
`semiconductor chip or microelectronic device Which is to be
`tested. The sheet socket assembly further includes an array
`of resilient contacts secured to the ?rst major surface of the
`dielectric body in registration With the holes so that each
`such resilient contact extends over one hole. Each resilient
`contact is adapted such that it can resiliently engage a
`bumped lead that has been inserted into the associated hole.
`The sheet socket assembly also includes a plurality of socket
`terminals electrically connected to these resilient contacts.
`
`

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`6,002,168
`
`7
`Typically, the socket terminals are disposed on the second
`major surface of the dielectric body in an array correspond
`ing to the array of contact pads on the ?rst surface of the
`rigid interposer. The socket terminals are electrically con
`nected to the associated resilient contacts. Preferably, each
`socket terminal is electrically connected to an associated
`resilient contact by an electrically conductive via, such as a
`blind via or a through hole via. The sheet socket assembly
`is mounted and electrically interconnected to the ?exible
`chip carrier by bonding the socket terminals to the associ
`ated contact pad on the rigid interposer.
`Another aspect of the present invention provides a semi
`conductor chip assembly comprising the test assembly
`described above and a semiconductor chip having solder
`bumps Which have engaged and are in physical and electri
`cal contact With the resilient contacts of the test assembly. In
`preferred embodiments of the semiconductor chip assembly
`of this aspect of present invention, the semiconductor chip
`is soldered to the test assembly.
`If the semiconductor chip assembly of this aspect of the
`invention contains more than one chip, the assembly can be
`described as a multichip module assembly. Each chip of the
`multichip module can be individually plugged into the test
`socket assembly of the present invention and the system can
`be tested. If the system Works properly, each of the chips can
`be soldered in permanently. In the alternative, a module
`containing at least tWo chips can be plugged into the test
`socket assembly and tested. If the system Works properly,
`each of the chips can be soldered in permanently.
`The semiconductor chip assembly of the present invention
`may be incorporated into a larger assembly to form an
`electronic device. Another aspect of the present invention,
`therefore, provides an electronic device. The electronic
`device includes the semiconductor chip assembly described
`above and a support substrate having pads. The pads are
`electrically conductive contact pads and are preferably dis
`posed in a pattern corresponding to the pattern of solid core
`joining units, Wherein each pad is associated With a solid
`core joining unit. The semiconductor chip assembly is
`positioned on the support substrate such that the bottom
`surface of the ?exible interposer faces toWard the support
`substrate and, preferably, such that the solid core joining
`units on the bottom surface of the ?exible interposer are
`aligned With the pads on the support substrate. Generally,
`each solid core joining unit is physically and electrically
`interconnected to an associated pad on the support substrate.
`The ?exible chip carrier of the present invention of the
`present invention may be incorporated into a larger assem
`bly to form an electronic component. Another aspect of the
`present invention, therefore, provides an electronic compo
`nent. The electronic component of the present aspect of the
`invention includes the ?exible chip carrier described above
`and a support substrate having pads. The pads are electri
`cally conductive contacts pads and are preferably disposed
`in a pattern corresponding to the pattern of solid core joining
`units, Wherein each pad is associated With a solid core
`joining unit. The ?exible chip carrier is positioned on the
`support substrate such that the bottom surface of the ?exible
`interposer faces toWard the support substrate and, preferably,
`such that the solid core joining units on the bottom surface
`of the ?exible interposer are aligned With the pads on the
`support substrate. Generally, each solid core joining unit is
`physically and electrically interconnected to an associated
`pad on the support substrate. A semiconductor chip may be
`bonded to the electronic component to form an electronic
`device. Preferred bonding methods include Wire bonding,
`?ip chip bonding and tab bonding With Wire bonding and ?ip
`chip bonding being particularly preferred.
`
`1O
`
`15
`
`25
`
`35
`
`45
`
`55
`
`65
`
`8
`The objects, features and advantages of the present inven
`tion Will be more readily apparent from the detailed descrip
`tion of the preferred embodiments set forth beloW, taken in
`conjunction With the accompanying draWings.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a diagrammatic sectional vieW depicting one
`embodiment of the semiconductor chip assembly of the
`present invention.
`FIG. 2 is a diagrammatic sectional vieW depicting another
`embodiment of the semiconductor chip assembly of the
`present invention.
`FIG. 3 is a diagrammatic sectional vieW depicting one
`embodiment of the test assembly of the present invention.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`
`A semiconductor chip assembly in accordance With one
`embodiment of the present invention is shoWn in FIG. 1 and
`includes a semiconductor chip 1. The semiconductor chip 1
`is Wire bonded to rigid interposer 2 With Wirebonds 3 and
`contact pads 17. This is a “?rst level” interconnection. The
`rigid interposer 2 has a ?rst surface 4, a second surface 5 and
`a plurality of electrical contacts 6 on such second surface 5.
`The rigid interposer may be made from any rigid materials
`and may contain one or more microelectronic components
`and a circuit (not shoWn). The assembly must include
`electrical interconnections betWeen electrical contacts 6 and
`respective Wirebonds 3. When the rigid interposer 2 includes
`a circuit, the interconnection is accomplished by intercon
`necting both the electrical contacts 6 and the Wire bonds 3
`to respective sites on the circuitry.
`The assembly further includes a ?exible interposer 7
`having a top surface 8, a bottom surface 9, apertures (not
`shoWn), and terminals 10. The terminals 10 are disposed on
`the top surface 8 of the ?exible interposer 7. The top surface
`8 faces the second surface 5 of the rigid interposer 2. The
`bottom suf?ce 9 faces aWay from the second surface 5 of the
`rigid interposer 2. Contacts 6 are electrically interconnected
`to terminals 10 With ?exible electrical connections 11. This
`is the second “?rst level interconnection of this assembly. In
`this embodiment electrical connections 11 are ?exible con
`ductive leads. Contacts 6, terminals 10 and leads 11 are
`disposed in respective area arrays, such as is shoWn in
`commonly assigned US. Pat. No. 5,518,964, Which is
`incorporated herein by reference.
`Aplurality of joining units 12 are disposed on the termi
`nals 10. Each joining unit 12 includes a spherical solid core
`13 having a diameter Which is less than the pitch