(12) United States Patent
`Alexander et al.
`
`(10) Patent N0.:
`(45) Date 0f Patent:
`
`US 6,891,258 B1
`May 10, 2005
`
`US006891258B1
`
`(54) INTERPOSER PROVIDING LOW
`INDUCTANCE DECOUPLING
`CAPACITANCE FOR A PACKAGED
`INTEGRATED CIRCUIT
`
`(75) Inventors: Mark A. Alexander, Boulder, CO
`(US); Robert O. Conn, Los Gatos, CA
`(US); Steven J. Carey, San Jose, CA
`(Us)
`(73) Assignee: Xilinx, Inc., San Jose, CA (US)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 139 days.
`
`(21) Appl. No.: 10/313,482
`(22) Filed:
`Dec. 6, 2002
`
`(51) Int. c1.7 ........................ .. H01L 23/48; H01L 23/34
`(52) US. Cl. ..................... .. 257/678; 257/738; 257/774;
`257/777; 257/780; 257/737; 257/713; 257/722;
`257/690; 257/691; 257/698; 257/699; 257/784
`(58) Field of Search ............................... .. 257/738, 774,
`257/777, 780, 737, 713, 722, 784, 690,
`691, 698, 699
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`5,880,925 A
`6,342,681 B1
`
`3/1999 DuPre et a1.
`1/2002 Goldberger et 211.
`
`10/2002 Galvagni et 211.
`6,459,561 B1
`6,477,032 B2 11/2002 Makl, Jr.
`2002/0101702 A1
`8/2002 Maki, Jr.
`2003/0001287 A1 * 1/2003 Sathe ....................... .. 257/780
`2003/0062602 A1 * 4/2003 Frutschy et a1. .......... .. 257/666
`
`* cited by examiner
`
`Primary Examiner—A1lan R. Wilson
`Assistant Examiner—Joseph Nguyen
`(74) Attorney, Agent, or Firm—Lois D. Cartier; LeRoy D.
`Maunu
`(57)
`
`ABSTRACT
`
`Structures that provide decoupling capacitance to packaged
`IC devices With reduced capacitor and via parasitic induc
`tance. A capacitive interposer structure is physically inter
`posed betWeen the packaged IC and the PCB, thus elimi
`nating the leads and vias that traverse the PCB in known
`structures. A capacitive interposer is mounted to a PCB and
`the packaged IC is mounted on the interposer. The interposer
`has an array of lands on an upper surface, to Which the
`packaged IC is coupled, and an array of terminals on a loWer
`surface, Which are coupled to the PCB. Electrically conduc
`tive vias interconnect each land With an associated terminal
`on the opposite surface of the interposer. Within the
`interposer, layers of a conductive material alternate With
`layers of a dielectric material, thus forming parallel plate
`capacitors betWeen adjacent dielectric layers. Each conduc
`tive layer is either electrically coupled to, or is electrically
`isolated from, each via.
`
`53 Claims, 7 Drawing Sheets
`
`Land 316
`
`Dielectric
`31 0
`Layer 311
`(GND)
`Layer 313
`(GND)
`Keepout
`318
`
`Via 315
`
`VCC1
`
`l/O Signal
`
`GND
`
`vcc2
`
`103 through
`GND / Plane 220
`
`Layer 312
`(V002)
`
`Layer 314
`
`Ball 317 V001
`
`l/O Signal
`
`GND
`
`VCCZ
`
`GND
`
`

`
`U.S. Patent
`
`May 10,2005
`
`Sheet 1 0f 7
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`US 6,891,258 B1
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`U.S. Patent
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`May 10, 2005
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`Sheet 2 of 7
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`US 6,891,258 B1
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`U.S. Patent
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`May 10,2005
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`Sheet 3 0f 7
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`US 6,891,258 B1
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`U.S. Patent
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`May 10, 2005
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`US 6,891,258 B1
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`U.S. Patent
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`May 10, 2005
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`Sheet 5 of 7
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`US 6,891,258 B1
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`U.S. Patent
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`May 10,2005
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`Sheet 6 0f 7
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`US 6,891,258 B1
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`U.S. Patent
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`May 10,2005
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`Sheet 7 0f 7
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`US 6,891,258 B1
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`
`US 6,891,258 B1
`
`1
`INTERPOSER PROVIDING LOW
`INDUCTANCE DECOUPLING
`CAPACITANCE FOR A PACKAGED
`INTEGRATED CIRCUIT
`
`FIELD OF THE INVENTION
`The invention relates to surface-mount coupler devices
`and capacitors. More particularly, the invention relates to an
`interposer that can be used to mount a packaged integrated
`circuit on a printed circuit board While providing loW
`inductance capacitive decoupling for the IC.
`BACKGROUND OF THE INVENTION
`Systems that include integrated circuit (IC) devices typi
`cally include decoupling capacitors (also knoWn as bypass
`capacitors) as Well. A decoupling capacitor is a capacitor
`coupled betWeen the poWer and ground pins (i.e., terminals)
`of a packaged IC to reduce noise on the poWer system Within
`the IC. (The Word “coupled” as used herein means “elec
`trically connected in such as Way as to pass direct current”
`as opposed to “capacitively coupled”, except Where the
`phrase “capacitively coupled” is explicitly used.) While in
`some cases the IC itself includes some decoupling
`capacitance, the amount of capacitance required is such that
`one or more additional decoupling capacitors are usually
`added external to the packaged device.
`In the past, the location of these decoupling capacitors
`Was a less important issue. The sWitching frequency of a
`device Was relatively loW, e.g., in the range of hundreds of
`kHZ (kilohertZ) to tens of MHZ (megahertZ). The transient
`currents Within the device Were also relatively loW. Hence,
`parasitic inductance in the printed circuit board (PCB)
`mountings Was not an important consideration. For example,
`for an IC mounted in a medium-performance package,
`Whether leaded or surface-mounted to the PCB, a 0.1 uF
`(microfarad) decoupling capacitor could typically be
`mounted on the PCB anyWhere Within a feW inches of the
`packaged IC.
`Many ICs noW operate at clock frequencies in the hun
`dreds of MHZ. At these higher frequencies, transient currents
`are signi?cantly higher than in the past, and parasitic induc
`tance is a much more important issue. Parasitic inductance
`Within the capacitors themselves has been reduced by
`improving the packaging of the capacitors, e.g., by using
`only surface-mount packages and by reducing the siZe of the
`packages. (Smaller packages inherently have a loWer para
`sitic inductance.) Parasitic inductance Within the PCB
`mountings has also been reduced through improved layout
`techniques, e.g., by using dedicated poWer planes in the
`PCB, by improving capacitor land geometries, and by care
`ful placement of the capacitors to reduce the distance
`betWeen the packaged IC and the capacitors.
`HoWever, as operating frequencies continue to increase,
`even these measures become inadequate. One bottleneck in
`the current path betWeen a decoupling capacitor and the
`associated packaged IC are the vias that transport charge
`from the capacitor lands through the PCB to the poWer
`planes, and then from the poWer planes through the PCB to
`the device. These vias can contribute parasitic inductance in
`the range of 1.5 nH (nanohenrys) each. If this via inductance
`could be reduced or eliminated, providing for high
`frequency transient current Would be much easier.
`Therefore, it is desirable to provide systems and structures
`that provide decoupling capacitance to IC devices With
`reduced capacitor parasitic inductance. It is further desirable
`to reduce via parasitic inductance in these systems and
`structures.
`
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`
`2
`SUMMARY OF THE INVENTION
`The invention provides systems and structures that pro
`vide decoupling capacitance to packaged IC devices With
`reduced capacitor and via parasitic inductance compared to
`knoWn systems and structures. This goal is accomplished by
`interposing a capacitive structure physically betWeen the
`packaged IC and the PCB, thus eliminating the leads and
`vias that traverse the PCB in knoWn systems and structures.
`A capacitive interposer according to the invention is a
`device separate from the packaged IC. In some
`embodiments, the capacitive interposer has a comparable
`footprint (i.e., area of coverage on the PCB) to the packaged
`IC. The interposer is mounted to a PCB and the packaged IC
`is mounted on the interposer. The interposer has an array of
`lands on an upper surface, to Which the packaged IC is
`coupled, and an array of terminals on a loWer surface, Which
`are coupled to the PCB. (The terms “upper surface” and
`“loWer surface” are used herein for convenience, Without
`implying any actual physical orientation of the surfaces With
`respect to any other object or structure.) Electrically con
`ductive vias (e. g., ?lled With conductive plating material and
`then possibly ?lled With solder material) interconnect each
`land With an associated terminal on the opposite surface of
`the interposer. In some embodiments, at least some of the
`vias are manufactured using a resistive material such as a
`thick ?lm resistive material. These resistive vias can
`provide, for example, built-in series termination for the
`signals traversing the vias, or pullup or pulldoWn devices for
`the signals.
`In some embodiments, the IC package is a ball grid array
`(BGA) package having balls soldered to the lands of the
`interposer, While the terminals of the interposer are balls
`soldered to the PCB using knoWn surface-mount techniques.
`The terminals can also be leads, lands, columns, or any other
`structures used for electrically interconnecting tWo devices.
`Within the interposer, layers of a conductive material
`alternate With layers of a dielectric material, thus forming
`parallel plate capacitors betWeen adjacent conductive layers.
`The conductive material can be metal, for example. The
`dielectric material can be, for example, a ceramic material,
`an organic material such as a polyimide or polyamide thin
`?lm, an inorganic material such as tantalum or aluminum
`oxide, or any other suitable dielectric material. In some
`embodiments, the dielectric material is a composite of epoxy
`and glass ?bers, such as the commonly-knoWn material
`called “FR4”. In some embodiments, different dielectrics are
`used in different dielectric layers, or in different portions of
`the same dielectric layer.
`Each conductive layer includes one or more “keepout
`areas” disposed around one or more vias. The keepout areas
`are ?lled With an electrically insulating material (thereby
`forming the “keepouts”). Thus, each keepout electrically
`isolates the conductive layer from the via. Thus, depending
`on Whether or not the keepout is present for each via, a
`conductive layer is either electrically isolated from, or is
`electrically coupled to, each package pin of the packaged IC.
`The interposer vias have a much smaller parasitic induc
`tance than the PCB vias formerly used to transport current
`betWeen a packaged IC and the associated decoupling
`capacitors. This reduced parasitic inductance is due to the
`fact that the interposer is typically much thinner than the
`PCB. Therefore the interposer vias are typically much
`shorter than the PCB vias, and have corresponding loWer
`inductance values.
`In some embodiments, some vias are electrically isolated
`from all of the conductive layers. These vias are used to pass
`
`

`
`US 6,891,258 B1
`
`3
`signals between the packaged IC and the PCB Without
`additional capacitance other than the relatively small capaci
`tance associated With the via itself.
`In some embodiments, every other conductive layer is a
`ground layer (GND), While the remaining conductive layers
`are poWer layers (VCC). Therefore, in some embodiments
`more than one conductive layer is provided for a single
`poWer supply. In some embodiments, one or more conduc
`tive layers are provided for each of tWo or more poWer
`supplies. These embodiments are particularly useful for ICs
`that require decoupling capacitors for tWo or more positive
`poWer supplies at different voltage levels. In some
`embodiments, the interposer includes conductive layers only
`for those poWer supplies having the greatest transient cur
`rents.
`In some embodiments, the body of the interposer includes
`an additional conductive layer that includes conductive
`traces. In these embodiments, not all balls in the packaged
`IC have corresponding vias in the interposer. Instead, the
`balls of the packaged IC come into contact With “partial
`vias” that extend only as far as the additional conductive
`layer, Which routes a signal “sideWays” through the conduc
`tive layer to another partial via that makes contact With the
`land on the PCB. Thus, this additional conductive layer
`makes it possible, for example, to exchange the positions of
`signals betWeen the packaged IC and the PCB. Thus, for
`example, these interposers can be used to correct pinout
`errors in the packaged IC or in the PCB design.
`In some embodiments, the additional conductive layer is
`used to provide interconnections betWeen tWo balls of the
`packaged IC or tWo lands of the PCB.
`In some embodiments, the additional conductive layer is
`used to add inductive features (e.g., transformers) betWeen
`any tWo signals, poWer, and/or ground.
`In some embodiments, the capacitive interposer has a
`comparable footprint to the packaged IC. In other
`embodiments, the capacitive interposer has a larger or
`smaller footprint than the packaged IC.
`In some embodiments, the interposer is manufactured as
`a single unbroken device. In other embodiments, the capaci
`tive interposer is manufactured as an array of separate tiles.
`These tiles can be separately soldered to the packaged IC
`and to the PCB, or can be combined together to form a single
`interposer device prior to mounting. The tiled embodiments
`can be particularly useful for large PC packages Where the
`IC package and the interposer material have Widely different
`coef?cients of thermal expansion. In one embodiment, an
`elastomer is used to hold the tiles together, thus forming a
`single tiled interposer device.
`According to some embodiments, a structure includes a
`packaged IC having a plurality of package pins disposed
`according to a ?rst pattern, a PCB having a plurality of PCB
`lands disposed thereon according to the ?rst pattern, a body
`having upper and loWer surfaces, a plurality of lands dis
`posed upon the upper surface of the body according to the
`?rst pattern and directly coupled to the package pins, and a
`plurality of terminals disposed upon the loWer surface of the
`body according to the ?rst pattern and directly coupled to the
`PCB lands.
`The body is manufactured using a plurality of alternating
`conductive layers and dielectric layers, Where the outermost
`layers are dielectric layers. A plurality of vias extends
`through the body orthogonal to the upper and loWer surfaces,
`and provides an electrically conductive path betWeen an
`associated land and an associated terminal. Each conductive
`layer in the body includes one or more electrically insulating
`keepouts disposed around at least a subset of the vias.
`
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`4
`According to some embodiments, a structure includes a
`packaged integrated circuit (IC) and an interposer structure
`having a comparable footprint to the packaged IC and
`directly coupled to the packaged IC. The packaged IC has a
`plurality of package pins, including at least one ground pin
`and at least one poWer pin. The interposer structure includes
`a body having upper and loWer surfaces, a plurality of lands
`disposed upon the upper surface of the body, and a plurality
`of terminals disposed upon the loWer surface of the body.
`The body is manufactured using a plurality of alternating
`conductive layers and dielectric layers, Where the outermost
`layers are dielectric layers. Each land is coupled to one of the
`package pins of the packaged IC. A plurality of vias extends
`through the body orthogonal to the upper and loWer surfaces,
`and provides an electrically conductive path betWeen an
`associated land and an associated terminal. Each conductive
`layer in the body includes one or more electrically insulating
`keepouts disposed around at least a subset of the vias. One
`or more of the conductive layers are coupled to the ground
`pin, and one or more of the conductive layers are coupled to
`the poWer pin, of the packaged IC.
`According to some embodiments, a system includes a
`packaged IC having a plurality of package pins, a printed
`circuit board (PCB) having a plurality of lands, and a
`capacitive interposer structure physically located betWeen
`the PCB and the packaged IC and directly coupled therebe
`tWeen. The capacitive interposer structure includes a body
`having upper and loWer surfaces, a plurality of lands dis
`posed upon the upper surface, and a plurality of terminals
`disposed upon the loWer surface.
`The body is manufactured using a plurality of alternating
`conductive layers and dielectric layers, Where the outermost
`layers are dielectric layers. Each land of the capacitive
`interposer structure is coupled to one of the package pins of
`the packaged IC. Each terminal of the capacitive interposer
`structure is coupled to one of the lands of the PCB. A
`plurality of vias extends through the body orthogonal to the
`upper and loWer surfaces, and provides an electrically con
`ductive path betWeen an associated land and an associated
`terminal. Each conductive layer in the body includes one or
`more electrically insulating keepouts disposed around at
`least a subset of the vias.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`The present invention is illustrated by Way of example,
`and not by Way of limitation, in the folloWing ?gures.
`FIG. 1 illustrates a packaged integrated circuit (IC)
`mounted on a printed circuit board (PCB) using a capacitive
`interposer according to one embodiment of the invention.
`FIG. 2 is a perspective vieW of a capacitive interposer
`according to one embodiment of the invention, in Which a
`cutaWay plane and vieW area are delineated.
`FIG. 3 is a cutaWay vieW of a capacitive interposer
`according to one embodiment of the invention, through the
`cutaWay plane shoWn in FIG. 2.
`FIG. 4 is a cutaWay vieW of a capacitive interposer similar
`to that of FIG. 3, but clearly shoWing the dielectric and
`conductive areas of the structure.
`FIGS. 5A—5C illustrate the various conductive layers
`shoWn in the cutaWay vieW of FIG. 3, Within the vieW area
`shoWn in FIG. 2.
`FIGS. 6A—6C shoW the conductive layers of FIG. 3 after
`the keepout areas are ?lled With a dielectric material.
`FIGS. 7A—7C shoW the conductive layers of FIG. 3 after
`the keepout areas are ?lled With dielectric material and holes
`for the vias are drilled.
`
`

`
`US 6,891,258 B1
`
`5
`FIG. 8 illustrates hoW several capacitive interposer struc
`tures can be used to couple a single packaged IC to a PCB.
`FIG. 9 shoWs hoW a single conductive layer can be split
`up into several areas to implement several different capaci
`tors.
`
`DETAILED DESCRIPTION OF THE DRAWINGS
`In the following description, numerous speci?c details are
`set forth to provide a more thorough understanding of the
`present invention. HoWever, it Will be apparent to one skilled
`in the art that the present invention can be practiced Without
`these speci?c details.
`FIG. 1 is a side vieW of a packaged integrated circuit (IC)
`102 mounted on a printed circuit board (PCB) 101 using a
`capacitive interposer 103 according to one embodiment of
`the invention. In the pictured embodiment, packaged IC 102
`comprises a ball grid array (BGA) package. Interposer 103
`is a multi-layered parallel-plate capacitive device having an
`array of lands on one side and a corresponding array of balls
`on the other. The balls on the bottom surface of interposer
`103 are mounted (e.g., soldered) to lands on PCB 101 using
`commonly knoWn techniques. Similarly, the balls of pack
`aged IC 102 are mounted (e.g., soldered) to the lands on the
`top surface of PCB 101.
`The lands and balls of the interposer are connected
`through the body of the interposer using vias that extend
`from the top surface to the bottom surface. Within the
`interposer, the facing plates of the capacitors are manufac
`tured using layers of conductive material sandWiched
`betWeen dielectric layers and selectively coupled to the vias.
`For example, conductive layers can be coupled to the vias
`carrying poWer and ground, While vias carrying other signals
`(such as clock signals and I/O signals) simply bypass the
`conductive layers and connect the package pins to the PCB
`Without adding extra capacitance.
`FIG. 2 is a perspective vieW of a capacitive interposer,
`e.g., interposer 103 of FIG. 1. Note that the number of lands
`and terminals (e. g., balls) in all of the ?gures herein is purely
`illustrative. In practice, the number of lands and terminals
`could be larger or smaller, but Would probably be larger in
`most cases. In some embodiments, the number of lands and
`terminals is selected to match the number of terminals on the
`packaged IC.
`The selection of vias to be connected to the conductive
`layers can also be made based on the location of the poWer
`and ground pins of the particular packaged IC. For example,
`an IC manufacturer can provide for each packaged IC a
`capacitive interposer designed to provide the correct amount
`of capacitance to the correct package pins. For example, it
`is common for the I/O portion and the internal logic portion
`of an IC to use tWo different operating voltage levels. Thus,
`this type of IC Would need to add decoupling capacitance
`betWeen the ground pins and the I/O poWer pins, and
`betWeen the ground pins and the poWer pins used for the
`internal logic. The present invention alloWs the manufacture
`of a capacitive interposer tailored to provide the necessary
`capacitance speci?c to each IC product, if desired.
`FIG. 2 shoWs the location of a cutaWay plane 220. FIG.
`1, for example, shoWs a vieW that could be taken along
`cutaWay plane 220. FIG. 3 shoWs the internal construction of
`an exemplary capacitive interposer, also along cutaWay
`plane 220.
`FIG. 3 shoWs the internal structural elements of an
`exemplary interposer according to one embodiment of the
`invention. Dielectric materials 310 are shoWn using a cross
`hatched pattern. The black areas are keepouts 318, Which are
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`also composed of a dielectric material (and can be the same
`material as materials 310). Conductive materials
`(conductive layers 311—314, vias 315, lands 316, and balls
`317) are shoWn in clear (no hatching). FIG. 4 is another vieW
`of the structure of FIG. 3 that more clearly illustrates the
`direct current connections Within the structure. In FIG. 4, the
`dielectric materials are shoWn cross-hatched and the con
`ductive materials are shoWn in clear.
`Referring noW to FIG. 3, the tWo outer layers (the top and
`bottom layers) of the structure are made up of dielectric
`material. BetWeen the tWo outer layers, conductive ground
`layers (GND, 311 and 313) alternate With conductive poWer
`layers (VCC2 312, VCC1 314) to form parallel plate capaci
`tors.
`The number of poWer layers can vary. For ICs having only
`one poWer supply, there might be only one poWer layer.
`Some poWer supplies having heavy transient currents might
`need several conductive layers adjacent to ground layers.
`The several conductive layers are coupled together through
`the poWer vias. Some ICs have more than tWo poWer
`supplies and might require at least one conductive layer for
`each poWer supply. For other ICs, some poWer supplies
`(those With minimal transient currents) might not require
`decoupling capacitors. For some ICs, it might be desirable to
`continue to provide external decoupling capacitors for some
`poWer supplies using previously knoWn methods.
`Similarly, some ICs have more than one ground, e.g., a
`digital ground and an analog ground, or an input/output
`ground and a ground used only for the internal core of the
`IC. Thus, an interposer according to the invention can
`include more than one ground and can require at least one
`conductive layer for each ground.
`It Will be apparent to one skilled in the art that the
`invention can be practiced Within these and other architec
`tural variations.
`The conductive layers are coupled to the desired lands
`316 (and hence to the desired pins of the packaged IC)
`through the vias 315. As can be seen from FIG. 3, a
`connection is made from the via to a conductive layer only
`When no keepout is present. For example, the leftmost via in
`FIG. 3 is coupled to the VCC1 pin of the packaged IC.
`Keepouts are present for the top three conductive layers
`(311, 312, and 313), so the via has no electrical contact With
`these layers. HoWever, no keepout is present for the bot
`tommost conductive layer 314, so this layer is electrically
`coupled to VCC1.
`Similarly, the fourth via from the left is coupled both to
`the VCC2 pin of the packaged IC and to conductive layer
`312. The third and ?fth vias from the left are coupled to
`ground pins of the packaged IC and to conductive layers 311
`and 313. In the pictured embodiment, layers 311 and 313 are
`each coupled to both ground pins. This duplication is
`desirable to reduce inductance and resistance, thereby pro
`viding a more effective decoupling capacitance. The second
`via from the left is coupled to an I/O signal of the packaged
`IC and does not contact any of the conductive layers in the
`interposer structure.
`Each of the vias 315 is coupled to an associated ball 317
`disposed on the bottom surface of the interposer structure.
`Thus, each pin of the packaged IC is coupled through the
`associated via to a corresponding land of the PCB.
`The interposer structure of FIG. 3 can be manufactured
`using conventional manufacturing techniques used, for
`example, for manufacturing PCBs, IC package substrates,
`and various types of capacitors. Examples of techniques that
`can be used include “core panel and pre-preg” techniques
`
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`US 6,891,258 B1
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`7
`commonly used in manufacturing PCBs, “build-up” tech
`niques commonly used in manufacturing IC package
`substrates, and sintering techniques commonly used in
`manufacturing capacitors.
`FIGS. 5A—7C illustrate the formation of the keepouts 318
`shoWn in FIG. 3. The areas of the layer surfaces shoWn in
`FIGS. 5A—7C can correspond, for example, to area 230
`delineated in FIG. 2.
`FIGS. 5A—5C shoW the various conductive layers in the
`structure of FIG. 3, With the keepout areas shoWn as clear
`areas 541 in the conductive material. (The small dashed
`circles 551 indicate Where the vias Will later be inserted.) To
`form the keepout areas, the conductive layers include holes
`in the conductive material. The conductive layers can be
`layers of metal, such as copper, for example. In some
`embodiments, the keepout areas are etched out of a solid
`layer, as in the core panel and pre-preg technique. In some
`embodiments, the keepout areas are simply left open When
`the conducting layer is laid doWn, as in the build-up tech
`nique.
`Where a keepout area is present, there Will be no electrical
`connection betWeen the conductive layer and the associated
`via. FIG. 5A shoWs conductive layers 311 and 313, Which
`are coupled to the tWo ground vias shoWn in FIG. 3.
`Similarly, FIG. 5B shoWs layer 312, Which is coupled to the
`VCC2 via in FIG. 3. FIG. 5C shoWs layer 314, Which is
`coupled to the VCC1 via in FIG. 3.
`Adjacent to each keepout area is a dielectric layer, as
`shoWn in FIG. 3. In some embodiments, the dielectric
`material in the adjacent dielectric layer ?oWs into the
`keepout area, thereby forming the electrically insulating
`keepout. In some embodiments, the keepout area is ?lled
`With dielectric material during the manufacture of the adja
`cent dielectric layer. In other embodiments, other techniques
`are used.
`FIGS. 6A—6C shoW the conductive layers after the kee
`pout areas are ?lled With dielectric material. The small
`dashed circles 651 in FIGS. 6A—6C shoW Where the vias Will
`be located. In some embodiments, via holes are drilled When
`the manufacture of the layered body is complete. In some
`embodiments, the body is manufactured as tWo or more
`separate layered bodies, in Which via holes are drilled before
`the layered bodies are joined to form the complete interposer
`body. In other embodiments, vias are manufactured using
`other techniques, such as laser cutting.
`FIGS. 7A—7C shoW the keepouts 741 in each conductive
`layer of FIG. 3 after the via holes 751 are drilled.
`In some embodiments, the via holes 751 are then plated
`With a conductive plating material using conventional
`techniques, and in some embodiments ?lled With solder. In
`some embodiments, the balls and/or lands are then applied.
`In some embodiments, the capacitive interposer has a
`comparable footprint to the packaged IC, as shoWn in FIG.
`1. In other embodiments, the capacitive interposer has a
`larger footprint than the packaged IC. In yet other
`embodiments, the capacitive interposer has a smaller foot
`print than the packaged IC.
`In some embodiments, the interposer is manufactured as
`a single unbroken device having a comparable footprint to
`the packaged IC. This arrangement has the advantage of
`simplicity, because all of the package pins can be easily
`connected to the PCB using a single interposer. HoWever,
`the arrangement can cause problems if the thermal coeffi
`cient of expansion varies Widely betWeen the interposer and
`either or both of the packaged IC and the PCB.
`PCBs and IC packages are typically made of organic
`materials. HoWever, it can be desirable to use ceramic
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`insulators to manufacture the interposer. Ceramic insulators
`typically have