UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`INTELLECTUAL VENTURES MANAGEMENT, LLC
`
`Petitioner
`
`V.
`
`XILINX, INC.
`Patent Owner
`
`Case IPR2012-00018
`
`Patent 7,566,960
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`DECLARATION GF MGRGAN T. JOHNSON IN SUPPORT OF
`
`PETITIGNER’S OPPOSITION Ti) PATENT GWNER’S MOTIOéI TO
`
`AMEND
`
`IVM 1012
`
`IPR2012-00018
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`INTELLECTUAL VENTURES MANAGEMENT, LLC
`
`Petitioner
`
`V.
`
`XILINX, INC.
`Patent Owner
`
`Case IPR2012-00018
`
`Patent 7,566,960
`
`DECLARATION GF MGRGAN T. JOHNSON IN SUPPORT OF
`
`PETITIGNER’S OPPOSITION Ti) PATENT GWNER’S MOTIOéI TO
`
`AMEND
`
`IVM 1012
`
`IPR2012-00018
`
`
`
`IPR2012-00018
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`Patent 7,566,960
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`I, Morgan T. Johnson, declare as follows:
`
`1.
`
`I have been retained by Intellectual Ventures Management, LLC
`
`(“IVM”) to provide declaratory evidence in inter partes review of US. Patent No.
`
`7,566,960 to Robert O. Conn (“the ‘960 Patent”), which is assigned to Xilinx, Inc.
`
`2.
`
`I have reviewed and am familiar with the specification and the
`
`claims of the ‘960 Patent filed on October 31, 2003.
`
`3.
`
`I have reviewed and am familiar with the following references:
`
`US. Patent No. 6,730,540 to Siniaguine (“Siniaguine”; IVM 1004); US. Patent
`
`No. 6,469,908 to Patel et a1. (“Patel”; IVM 1005); US. Patent No. 6,970,362 to
`
`Chakravorty (“Chakravorty ‘362”; IVM 1007); US. Patent No. 6,423,570 to Ma et
`
`al. (“Ma”; IVM 1008); US. Patent No. 6,891,258 to Alexander et a1. (“Alexander”;
`
`IVM 1016); US. Patent No. 6,319,829 to Pasco et al. (“Pasco”; IVM 1017); and
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`US. Patent No. 6,002,168 to Bellaar et al. (“Bellaar”; IVM 1018). I will cite to
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`these references using the following format: (IVM 1004, 121-10). This example
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`citation points to the Siniaguine specification at column 1, lines 1—10.
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`4.
`
`I am familiar with and am a practitioner of the technology at issue
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`and the state of the art at the time the application leading to the ‘960 Patent was
`
`filed. The filing date of the ‘960 Patent was October 31, 2003. Based on the
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`2
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`Patent 7,566,960
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`technologies disclosed in the ‘960 Patent, I believe that one of ordinary skill in the
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`art would have a BS. degree in Electrical Engineering or equivalent training, as
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`well as 3-5 years of experience in the field of electronics packaging and
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`interconnect design.
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`5.
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`I have been asked to provide my technical review, analysis,
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`insights and opinions regarding the above-noted references.
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`Qualifications
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`6.
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`I have more than 29 years of experience in the electronic
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`interconnect and semiconductor industries.
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`7.
`
`I earned a Bachelor of Science degree in Graphics from the
`
`University of Oregon. My studies included subjects in advanced mathematics
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`related to geodesic domes. I also attended The Art Center College of Design in
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`Pasadena, California, where I majored in Industrial Design.
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`8.
`
`I currently serve as Chief Scientist at Advanced Inquiry Systems,
`
`Inc. (AISI), a company that I founded in 2002. As Chief Scientist, my research
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`focuses on tools and interfaces for full-wafer testing of products such as NAND
`
`and NOR flash, Dynamic Random Access Memory (DRAM) and certain logic
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`3
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`IPR2012—0001 8
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`Patent 7,566,960
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`devices. My research is additionally driven by the semiconductor industry’s
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`demand for highly—parallel wafer testing of System-on—Chips (SOCs), such as
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`processors for mobile devices. Through my research, AISI has implemented a
`
`device that achieves contact with up to 500,000 pads per wafer during tests. AISI
`
`was founded on my patented work in this area and benefits from over 30 issued
`
`patents.
`
`9.
`
`I co-founded Prototype Solutions Corporation in 1994, a company
`
`focused on using advanced interconnect and packaging technology to provide
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`quick—turn prototypes and hardware emulation using programmable logic devices
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`such as Field Programmable Gate Arrays (r‘PGAs). The technology is used to
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`prototype highly-complex Central Processing Units (CPUs), Graphic Processing
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`Units (GPUS), System on Chips (SOCs) and Application Specific Integrated
`
`Circuits (ASICs).
`
`10.
`
`I founded LaserPath Corp. in 1983. LaserPath was a
`
`semiconductor company focused on laser programmable semiconductor gate
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`arrays. The foundation of this technology was based on my inventions and patents.
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`LaserPath achieved over 200 design wins in the first 9 months of sales—setting a
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`record. LaserPath’s technology included Gate Arrays programmed with a laser in a
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`4
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`ceramic package, tested and delivered to customer in as little as two hours and
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`more typically within 5 business days. This rapid Gate Array turnaround time and
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`large number of design wins drastically shifted the ASIC business from a l2-week
`
`delivery to a new standard of 3— week delivery.
`
`1 1.
`
`From 1980-1981, I researched controlled impedance, instant turn-
`
`around circuit boards for the Cray 2 computer system. My research was funded by
`
`Cray Computer Corporation—Boulder, Colorado Team. This research included the
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`development of laser-programmed printed circuit boards, multi-chip module
`
`structures and emitter—coupled logic on—chip wiring. This research was the genesis
`
`for my later-developed technology that evolved into LaserPath.
`
`12.
`
`In addition to my semiconductor industry experience, I am an
`
`inventor on 36 US. patents related to interconnects, high-speed connectors and
`
`semiconductors. Also, I have a faculty appointment as Adjunct Professor in the
`
`Electrical Engineering School at Portland State University in Portland, Oregon. I
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`have also been a guest lecturer at the Jet Propulsion Laboratory (JPL) in Pasadena,
`
`California.
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`13. My professional background and technical qualifications are stated
`
`above and are also reflected in my Curriculum Vitae, which is attached as IVM
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`5
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`1020. I am being compensated at a rate of $300.00 per hour, with reimbursement
`
`for actual expenses, for my work related to this inter partes review proceeding. My
`
`compensation is not dependent on and in no way affects the substance of my
`
`statements in this Declaration.
`
`14.
`
`I understand that “anticipation” is a question of fact and that for a
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`reference to anticipate a claimed invention it must disclose each and every element
`
`set forth in the claim for that invention. I fithher understand that the requirement of
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`strict identity between the claim and the reference is not met if a single element or
`
`limitation required by the claim is missing from the applied reference.
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`15.
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`It is my further understanding that a prior art reference is
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`anticipatory only if it discloses each and every limitation of the claim (as properly
`
`construed) at issue. In other words, every limitation of a claim must identically
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`appear in a single prior art reference for it to anticipate a claim.
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`16.
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`It is also my understanding that a claimed invention is unpatentable
`
`if the differences between the invention and the prior art are such that the subject
`
`matter as a whole would have been obvious at the time the invention was made to a
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`person having ordinary skill in the art to which the subject matter pertains.
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`17.
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`It is my understanding that “obviousness” is a question of law
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`based on underlying factual issues including the content of the prior art and the
`
`level of skill in the art. I understand that for a single reference or a combination of
`
`references to anticipate the claimed invention, a person of ordinary skill in the art
`
`must have been able to arrive at the claims by altering or combining the applied
`
`references.
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`18.
`
`I also understand that when considering the obviousness of a patent
`
`claim, one should consider whether a teaching, suggestion, or motivation to
`
`combine the references exists so as to avoid impermissibly applying hindsight
`
`when considering the prior art. I understand this test should not be rigidly applied,
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`but that the test can be important to avoid such hindsight.
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`Analysis
`
`19.
`
`I now turn to certain aspects of Chakravorty ‘362, Siniaguine, Ma,
`
`Patel, Alexander, Pasco and Bellaar.
`
`20. Alexander discloses an interposing structure with a plurality of
`
`tiled interposing structures. In reference to FIG. 8, smaller interposers (or “tiles”)
`
`can be separately soldered to a packaged integrated circuit 802 and to lands of a
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`7
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`printed circuit board 801. See IVM 1016, 8: 1 8-26. The tiles can be combined to
`
`form a single interposer device. See id. Here, an elastomer can be used to hold the
`
`tiles together to form the signal interposer device. See id. It is well known that
`
`elastomers can be used to absorb mechanical stresses from thermal expansion
`
`and/or contraction. See id.
`
`21.
`
`Previously, in my declaration in support of inter partes review of
`
`the ‘960 Patent, I concluded that an electronic packaging designer would modify
`
`the integrated circuit package of Chakravorty ‘362 to incorporate the teachings of
`
`Siniaguine. See IVM 1002, fl 69. In particular,
`
`The modifications to primary substrate 320 of Chakravorty
`‘362 to include an array of solder balls disposed on an outside
`surface of primary substrate 320 as taught by Siniaguine would
`have been nothing more than applying a known and straight-
`forward packaging technique to primary substrate 320 of
`Chakravorty ‘362. This is because packaging techniques, such
`as the one illustrated in FIG. 12 of Siniaguine were well known
`in the art and widely used at the time of filing of Chakravorty
`‘362
`and Siniaguine. During the
`filing timeframe of
`Chakravorty ‘362 and Siniaguine, ball grid arrays (BGAs) had
`displaced pin grid arrays (PGAs) in several key electronics
`markets and was likely the packaging type of choice for the
`interposer
`structures disclosed in Chakravorty ‘362 and
`Siniaguine. Indeed, Siniaguine discloses that
`the packaging
`illustrated in FIG. 12 is an exemplary, BGA package. See
`Siniaguine, 7:61-67.
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`IVM 1002, ‘ll 69.
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`22.
`
`In addition to incorporating the solder balls of Siniaguine to the
`
`outside surface of Chakravorty ‘3 62’s integrated circuit package, an electronic
`
`packaging designer would also modify interposer 310 in FIG. 3 of Chakravorty
`
`‘362 to incorporate the teachings of Alexander. Alexander notes that printed circuit
`
`boards (PCBs) and integrated circuit (IC) packages are typically manufactured
`
`from organic materials, which can be subjected to deformation due to thermal
`
`coefficients of expansion and/or contraction. See IVM 1016, 7:66-8:1 1. One way
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`to alleviate this issue is to use several smaller interposers to mount a larger IC to a
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`PCB. See id, 8:12-18. An advantage of using several smaller interposers is that
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`“they can individually expand and/or contact over several smaller areas, rather
`
`than experiencing a larger expansion and/or contraction over a single larger area.
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`Thus, the structure can withstand greater variations in temperature without failure.”
`
`Id., 8:14-18.
`
`23.
`
`Figure 8 of Alexander is an illustration of such an interposer
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`structure with a plurality of tiled interposing structures. This interposer structure
`
`can use an elastomer to hold the tiled interposing structures together. See id., 8:23-
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`26. The elastomer can also serve to absorb mechanical stresses due to thermal
`
`expansion and/or contraction. See id.
`
`24. An electronic packaging designer would modify interposer 310 in
`
`FIG. 3 of Chakravorty ‘362 to have a plurality of tiled interposing structures—like
`
`FIG. 8 of Alexander. One reason for this modification is because interposer 310
`
`can be fabricated using high thermal coefficient of expansion (HITCE) technology,
`
`which is vulnerable to thermal expansion and/or contraction. See IVM 1007, 7:42-
`
`46.
`
`25.
`
`The tiled interposing structures in the neodified interposer of
`
`Chakravorty’362 can be held together using an elastomer. This modification would
`
`have been nothing more than a mere design choice by an electronic packaging
`
`designer that would yield predictable results. For example, for larger ICs, an
`
`electronic packaging designer can choose to implement a higher number of tiled
`
`interposing structures (held together by an elastomer) to mitigate for the effects of
`
`different thermal coefficients of expansion and/or contraction.
`
`26.
`
`I would like to re-iterate that Chakravorty ‘362 discloses an IC
`
`package, in which interposer 310 in FIG. 3 is disposed in the IC package.
`
`Chakravorty ‘362 discloses that, in reference to FIG. 3 and other embodiments,
`
`10
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`“the inventive subject matter is not to be construed as limited to use in C4
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`packages, and it can be used with any other type of IC package where the herein-
`
`described features of the inventive subject matter provide an advantage.” IVM
`
`1007, 1028-11. The term “C4” is an abbreviation for controlled collapse chip
`
`connection. C4 packages are a type of IC package. C4 integrated circuit packages
`
`are also referred to as “flip chip” integrated circuit packages.
`
`27.
`
`In FIG. 3 of Chakravorty, interposer 310 is disposed between an IC
`
`die 300 and a primary substrate 320. Solder balls 301 provide electrical contacts
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`between IC die 300 and interposer 310. Similarly, solder balls 311 provide
`
`electrical contacts between interposer 310 and primary substrate 320. The
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`arrangement of IC die 300, interposer 310, primary substrate 320 and solder balls
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`301 and 311 in FIG. 3 is the same as the relative arrangement of IC die 40,
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`interposer 50, primary substrate 60 and solder bumps 42 and 58 in FIG. 2 of
`
`Chakravorty ‘362. Solder balls 301 and 311 in FIG. 3 form a portion of the C4
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`integrated circuit package.
`
`28. Another portion of the C4 integrated circuit package in FIG. 3 of
`
`Chakravorty ‘362 is an underfill encapsulant that fills in the areas between solder
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`balls 301(between IC die 300 and interposer 310) and the areas between solder
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`11
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`balls 311 (between interposer 310 and primary substrate 320). Interposer 310 can
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`be fabricated using high thermal coefficient of expansion (PHTCE) technology. See
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`IVM 1007, 7:42-46. Primary substrate 320 can be fabricated from an organic
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`materégal, which is also subject to I-HTCE. See id., 4:1-3. An underfill encapsulant is
`
`required to mitigate the effects of HITCE. It is well known that underfill
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`encapsulants serve this purpose:
`
`One of the major reasons why solder-bumped flip chip on
`low-cost or organic CSP substrates works is because of the
`underfill epoxy encapsulant. It reduces the effect of the
`global thermal expansion mismatch between the silicon chip
`and the organic substrate,
`i.e.,
`it reduces the stresses and
`strains in the flip-chip solder bumps (since the chip and the
`substrate are tightly held by the underfill) and redistributes
`over the entire chip area the stresses and strains that would
`otherwise be increasingly concentrated near
`the comer
`solder bumps of the chip. Other advantages of underfill
`encapsulant are that it protects the chip from moisture, ionic
`contaminants, radiation, and hostile operating environments
`such as thermal, mechanical pull, shear, and twist, and
`shock/vibration.
`
`IVM 1014, p. 19.
`
`29.
`
`In referring to FIG. 3 of Chakravorty ‘362, the C4 integrated
`
`circuit package includes primary substrate 320 and underfill encapsulant between
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`IC die 300 and interposer 310 and between interposer 310 and primary substrate
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`12
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`320. The underfill encapsulant can surround interposer 310, in which the underfill
`
`encapsulant forms sidewalls of the C4 integrated circuit package—thus
`
`surrounding interposer 310. Here, interposer 310 is disposed inside the C4
`
`integrated circuit package. Further, the portion or area in which solder balls 311
`
`reside in FIG. 3 of Chakravorty ‘362 is an inside surface of the C4 integrated
`
`circuit package.
`
`30.
`
`Previously, in my declaration in support of inter partes review of
`
`the ‘960 Patent, I concluded that an electronic packaging designer would modify
`
`the pattern of micro-bumps and the pattern of pads in Siniaguine to incorporate the
`
`teachings of Ma. See IVM 1002, f; 89. In particular,
`
`The modifications to the first pattern of micro-bumps disposed
`on IC 310 in FIG. 4 of Siniaguine to have a substantially
`identical pattern as the second pattern of pads 388 disposed on
`wiring substrate 330 as taught by Ma would have been a
`relatively simple substitution of the micro-bump/pad pattern
`illustrated in FIG. 4 of Siniaguine with the micro-bump/pad
`pattern illustrated in FIG. 18 of Ma. This substitution can be
`applied using known packaging techniques and would not
`change the operation of the semiconductor integrated circuit
`structure of Siniaguine. Rather, the substitution would provide
`flexibility in the signal distribution between IC 310 and wiring
`substrate 330 of Siniaguine.
`
`IVM 1002, fi 89.
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`13
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`31.
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`In addition, in my declaration in support of inter partes review of
`
`the ‘960 Patent, I concluded that an electronic packaging designer would modify
`
`IC 320 in FIG. 4 of Siniaguine (as modified by Ma) to incorporate the teachings of
`
`Chakravorty ‘362. See IVM 1002, ‘I 92. In particular,
`
`The modifications to IC 320 in FIG. 4 of Siniaguine (as
`modified by Ma) to have a micro-bump beneath IC 310 in a
`first position in the array of micro-bumps electrically coupled to
`a first pad 388 of wiring substrate 330 located opposite to the
`first position and to a second pad 388 of wiring substrate in the
`array of pads 388 would have been a simple substitution of IC
`320 of Siniaguine with interposer 310 of Chakravorty ‘362.
`This substitution would not change the mechanical or electronic
`functionality of the semiconductor integrated circuit structure of
`Siniaguine. For example,
`interposer 310 in FIG.
`3 of
`Chakravorty ‘362 above provides flexibility in the signal
`distribution between solder balls 301 on IC die 300 and signal
`terminals/bumps on primary substrate 320.
`
`IVM 1002, ‘11 92.
`
`32. An electronic packaging designer would further modify IC 320 in
`
`FIG. 4 of Siniaguine to incorporate the teachings of Alexander. Again, Alexander
`
`discloses an interposer structure with a plurality of tiled interposing structures, in
`
`which an elastomer can be used to hold the tiled interposing structures togetléer.
`
`See IVM 1016, 8:18-26. One reason for this modification is because IC 320 of
`
`Siniaguine can be fabricated using high thermal coefficient of expansion (HITCE)
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`14
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`Patent 7,566,960
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`technology, which is vulnerable to thermal expansion and/or contraction. See IVM
`
`1004, 7:66-67 .
`
`33. An electronic packaging designer would modify IC 320 in FIG. 4
`
`of Siniaguine to have a plurality of tiled interposing structures—like FIG. 8 of
`
`Alexander. The tiled interposing structures in the modified interposer of Siniaguine
`
`can be held together using an elastomer. This modification would have been
`
`nothing more than a mere design choice by an electronic packaging designer that
`
`would yield predictable results. For example, for larger ICs, an electronic
`
`packaging designer can choose to implement a higher number of tiled interposing
`
`structures (held together by an elastomer) to mitigate for the effects of different
`
`thermal coefficients of expansion and/or contraction.
`
`34.
`
`I would like to re-iterate that Siniaguine discloses an IC package.
`
`FIG. 12 of Siniaguine illustrates a ball grid array (BGA) package. See IVM 1004,
`
`7:61-62. A BGA package is a type of integrated circuit package.
`
`35.
`
`In FIG. 12 of Siniaguine, “[w]iring substrate 330 is a BGA
`
`substrate (e.g., plastic) with solder balls 810 on the bottom .
`
`.
`
`.
`
`. Underfill 830 fills
`
`the area between the circuits 310, 320 and the area between interposer 320 and
`
`substrate 330.” IVM 1004, 7:62-66. Underfill 830 serves a similar purpose as the
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`15
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`underfill encapsulant of Chakravorty ‘362 discussed above. Also, the arrangement
`
`of circuit 310, interposer 320 and substrate 330 is the same as the relative
`
`arrangement of IC die 40, interposer 50 and primary substrate 60 from FIG. 2 of
`
`Chakravorty ‘3 62.
`
`36.
`
`The BGA integrated circuit package of Siniaguine includes wiring
`
`substrate 330 (e.g., BGA substrate) and underfill 830. As illustrated in FIG. 12,
`
`underfill 830 surrounds interposer 320, in which underfill 830 forms sidewalls of
`
`the BGA integrated circuit package. This is similar to fill material 1520 in FIG. 15
`
`of Siniaguine, which illustrates that fill material 1520 forms the right and left
`
`sidewalls of an integrated circuit package; thus surrounding interposer 320. See
`
`IVM 1004, 8:20-55. As a result, interposer 320 in FIG. 12 is disposed inside the
`
`BGA integrated circuit package. Further, the portion or area in which contacts 323
`
`(not annotated) reside in FIG. 12 of Siniaguine is an inside surface of the BGA
`
`integrated circuit package. In reference to FIG. 4 of Siniaguine, pads 388 are
`
`disposed on the inside surface of the BGA integrated circuit package.
`
`37.
`
`I now turn to Pasco. Pasco discloses an interposer structure with a
`
`plurality of tiled interposing structures. FIG. 4 of Pasco (reproduced below)
`
`illustrates a segmented interposer 48 with a plurality of equal-sized interposers 20
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`16
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`arranged in a planar manner above a printed circuit board (PCB) 50. See IVM
`
`1017, 428—18. Segmented interposer 48 provides interconnections between
`
`substrate 44 (e.g., part of a multichip module 40) and PCB 50 using solder balls 46.
`
`See id. Segmented interposer 48 mitigates stresses on solder balls 46 due to the
`
`effects of different thermal coefficients of expansion (TCE). See id. Interposers 20
`
`can be considered tiled interposing structures since they are the same structure
`
`(e.g., as understood by the common nomenclature “20” used for each of the three
`
`structures) that can be arranged in a side-by-side pattern (as illustrated in FIG. 4 of
`
`Pasco below).
`
`20 EIII:
`
`!I_III
`
`FIG. 4 of Pasco
`
`38.
`
`I now turn to Bellaar. Bellaar discloses an elastomer that can be
`
`used to control spacing/separation between interposers. See IVM 1018, 5 24-26. For
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`17
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`Patent 7,566,960
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`example, Bellaar uses the elastomer to create a compliant layer, or compliant
`
`spacer, between a rigid interposer and a flexible interposer. See id. The elastomer
`
`can be used to compensate for mismatches in the coefficient of thermal expansion
`
`between a chip and the rigid interposer and/or between the rigid interposer and the
`
`flexible interposer. See id., 3:23-33.
`
`39. An electronic packaging designer would modify segmented
`
`interposer 48 in FIG. 4 of Pasco based on the teachings of Bellaar. In particular, an
`
`electronic packaging designer would use the elastomer of Bellaar to hold together
`
`interposers 20 in segmented interposer 48 of Pasco. In referring to FIG. 4 of Pasco,
`
`substrate 44 and PCB 50 can be manufactured from materials different from
`
`interposers 20, thus having a different coefficient of thermal expansion than
`
`interposers 20. The elastomer of Bellaar can be used to control the
`
`spacing/separation between interposers 20—e.g., lateral shifts in solder balls 46—
`
`relative to substrate 44 and PCB 50 under various thermal conditions. For ease of
`
`explanation, the combination of the segmented interposer of Pasco with the
`
`elastomer of Bellaar (holding interposers 20 together) will be referred to herein as
`
`“the modified segmented interposer of Pasco/Bellaar.” This modification would
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`18
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`have been nothing more than a mere design choice by an electronic packaging
`
`designer that would yield predictable results.
`
`40. As discussed above, an electronic packaging designer would
`
`modify the IC package of Chakravorty ‘362 to incorporate the teachings of
`
`Siniaguine. See IVM 1002, fi 69. An electronic packaging designer would also
`
`modify interposer 310 in FIG. 3 of Chakravorty ‘362 to implement the features of
`
`the modified segmented interposer of Pasco/Bellaar. One reason for this
`
`modification is because interposer 310 can be fabricated using high thermal
`
`coefficient of expansion (HITCE) technology, which is vulnerable to thermal
`
`expansion and/or contraction. See IVM 1007, 7:42-46.
`
`41.
`
`The modified segmented interposer of Pasco/Bellaar can mitigate
`
`the stress on solder balls 301 and 311 in FIG. 3 of Chakravorty ‘362 due to the
`
`effects of different thermal coefficients of expansion (TCE). For example, the
`
`modified segmented interposer of Pasco/Bellaar can compensate for mismatches in
`
`the coefficient of thermal expansion between IC die 300 and the modified
`
`segmented interposer and between the modified segmented interposer and primary
`
`substrate 320. This modification would have been nothing more than a mere design
`
`choice by an electronic packaging designer that would yield predictable results.
`
`19
`
`
`
`IPR2012-00018
`
`Patent 7,566,960
`
`For example, for larger ICs, an electronic packaging designer can choose to
`
`implement the modified segmented interposer of Pasco/Bellaar in the interposer of
`
`Chakravorty ‘3 62 to mitigate for the effects of different thermal coefficients of
`
`expansion and/or contraction.
`
`42. As discussed above, an electronic packaging designer would
`
`modify IC 320 in FIG. 4 of Siniaguine (as modified by Ma) to incorporate the
`
`teachings of Chakravorty ‘3 62. See IVM 1002, f| 92. An electronic packaging
`
`designer would also modify IC 320 in FIG. 4 of Siniaguine to implement the
`
`features of the modified segmented interposer of Pasco/Bellaar. One reason for this
`
`modification is because IC 320 of Siniaguine can be fabricated using high thermal
`
`coefficient of expansion (I-HTCE) technology, which is vulnerable to thermal
`
`expansion and/or contraction. See IVM 1004, 7:66—67.
`
`43.
`
`The modified segmented interposer of Pasco/Bellaar can mitigate
`
`the stress on the micro-bumps between IC 310 and IC 320 and contacts 323
`
`between IC 320 and wiring substrate 330 in FIG. 4 of Siniaguine. For example, the
`
`modified segmented interposer of Pasco/Bellaar can compensate for mismatches in
`
`the coefficient of thermal expansion between IC 310 and the modified segmented
`
`interposer and between the modified segmented interposer and wiring substrate
`
`20
`
`
`
`IPR2012-00018
`
`Patent 7,566,960
`
`330. This modification would have been nothing more than a mere design choice
`
`by an electronic packaging designer that would yield predictable results. For
`
`example, for larger ICs, an electronic packaging designer can choose to implement
`
`the modified segmented interposer of Pasco/Bellaar in the interposer of Siniaguine
`
`to mitigate for the effects of different thermal coefficients of expansion and/or
`
`contraction.
`
`44. My analysis above with regard to Chakravorty ‘3 62, Siniaguine,
`
`Ma, Alexander, Pasco and Bellaar does not change my analysis as to the
`
`combination of Chakravorty ‘362, Siniaguine and Patel from my declaration in
`
`support of inter partes review of the ‘960 Patent. See IVM 1002, W 82-83. For
`
`similar reasons set forth in my declaration, an electronic packaging designer would
`
`modify the IC package of Chakravorty ‘3 62, Siniaguine and Alexander (as
`
`described above) to incorporate the teachings of Patel. See id. Similarly, an
`
`electronic packaging designer would modify the IC package of Chakravorty ‘362,
`
`Siniaguine, Pasco and Bellaar (as described above) to incorporate the teachings of
`
`Patel. See id.
`
`45.
`
`The analysis above also does not change my analysis as to the
`
`combination of Siniaguine, Ma, Chakravorty ‘362 and Patel from my declaration in
`
`21
`
`
`
`IPR2012-00018
`
`Patent 7,566,960
`
`support of inter partes review of the ‘960 Patent. See IVM 1002, fi'fi' 104—105. For
`
`similar reasons set forth in my declaration, an electronic packaging designer would
`
`modify the IC package of Siniaguine, Ma, Chakravorty ‘362 and Alexander (as
`
`described above) to incorporate the teachings of Patel. See id. Similarly, an
`
`electronic packaging designer would modify the IC package of Siniaguine, Ma,
`
`Chakravorty ‘362, Pasco and Bellaar (as described above) to incorporate the
`
`teachings of Patel. See id.
`
`I hereby declare that all statements made herein of my own knowledge are
`
`true and that all statements made on information and belief are believed to be true;
`
`and further that these statements were made with the knowledge that willful false
`
`statements and the like so made are punishable by fine or imprisonment, or both,
`
`under Section 1001 of Title 18 of the United States Code.
`
`Executed this 2 7 day of August 2013 in Portland, OR.
`
`
`
`
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