`Lee
`
`[191
`
`||||||||||||||lllllllllllllllllllllllllllllllllIlllllllllllllllllllllllllll
`U8005210846A
`
`[11] Patent Number:
`
`5,210,846
`
`[45] Date of Patent: May 11, 1993
`
`[54]
`
`1751
`
`[73]
`
`[21]
`
`[22]
`
`[51]
`[52]
`
`[58]
`
`[56]
`
`ONE-WIRE BUS ARCHITECTURE
`
`Inventor: Robert D. Lee, Demon, Tex.
`
`Assistant Examiner—Jack A. Lane
`Attorney, Agent, or Firm—Worsham, Forsythe, Sampels
`& Wooldridge
`
`Assignee: Dallas Semiconductor Corporation,
`Dallas, Tex.
`
`[57]
`
`ABSTRACT
`
`App]. No.: 352,581
`
`Filed:
`
`May 15, 1989
`
`Int. Cl.5 ...................... G06F 13/18; 606K 19/06
`US. Cl. .................................... 395/425; 395/400;
`364/DIG. 1; 235/492; 365/ 189.03; 365/ 189.06
`Field of Search
`365/189.03, 189.06,
`365/194; 357/74; 335/488, 489, 492; 368/87,
`88; 70/228; 395/425, 400; IMO/825.08
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`2/1977 Moreno ............................... 235/492
`4.007.355
`4.196.577 4/1980 Ohno et a1. ............... 368/82
`
`4,272,338
`6/1981 Kmma et a1.
`368/88
`4,480,178 10/1984 Miller, 11 et a1.
`..
`..... 235/380
`..... 235/492
`4,621,190 11/1986 Saito et al.
`
`.
`. 395/425
`7/1989 Lighthurt et a1.
`4,845,609
`
`4,868,409
`9/1989 Tanaka et all
`.
`.M 70/278
`.nu 365/228
`4,982,371
`1/1991 Bolan et a1.
`
`..... 235/449
`5,013,898
`5/1991 Glasspool
`9/1991 Curry .................................. 235/441
`5,045,675
`
`A system architecture which provides efficient data
`communication, over a one-wire bus, with a portable
`data module which does not necessarily include any
`accurate time delay circuit whatsoever. The time delay
`circuit in the module can be extremely crude. An open-
`collector architecture is used, with electrical relations
`defined to absolutely minimize the drain on the portable
`module’s battery. A protocol has been specified so that
`the module never sources current to a data line of the
`one-wire bus, but only sinks current. The protocol in-
`cludes signals for read; write-zero; write-one; and reset.
`Each one-bit transaction is initiated by a falling edge of
`a voltage signal from the host. The time delay circuit in
`the module defines a delay, after which (in write mode)
`the module tests the data state of the data line. In read
`mode, after a falling edge of a voltage signal from the
`host the module does or does not turn on a pull-down
`transistor, depending on the value of the bit read. Thus,
`the host system. after the falling edge, attempts to pull
`the data line high again, and then tests the potential of
`the data line to ascertain the value of the bit read.
`
`Primary Examiner—Joseph L. Dixon
`
`6 Claims, 17 Drawing Sheets
`
`—.L NO.p
`
`
`
`RX I
`
`I l 1
`
`HOST ‘— :
`
`—> TOKEN
`
`COMPASS EXH. 1009 - Page1 of 41
`
`COMPASS EXH. 1009 - Page 1 of 41
`
`
`
`US. Patent
`
`May 11, 1993
`
`Sheet 1 of 17
`
`5,210,846
`
`
`FIG. 1B
`
`WRITE ONE TIME SLOT
`
`_,:
`
`k—————eo
`
`I<—1ps Min
`
`I
`
`115
`
`In
`
`M' ——-II
`
`'
`
`II
`
`[STARTOF NEXT CYCLE
`
`I I a
`
`LL
`
`ffix"
`
`FIG. 2A
`
`WRIT
`
`R0 TIM SLOT
`
`I<—————60
`
`-’: h—I 113 Min
`
`l
`
`[.15
`
`m
`
`M' —————-I
`
`|M F
`
`l
`
`I
`
`l
`
`l
`
`I
`
`START OF NEXT CYCLE
`
`I
`
`l
`
`IG. ZB
`
`COMPASS EXH. 1009 - Page 2 of 41
`
`COMPASS EXH. 1009 - Page 2 of 41
`
`
`
`US. Patent
`
`May 11, 1993
`
`Sheet 2 of 17
`
`5,210,846
`
`READ DATA IIME SLOTS
`
`k————50ps MlN———" ' START or NExr CYCLE
`-*: h—I p8 MIN
`|
`I
`
`I
`
`I
`
`I
`
`->:
`
`*1
`
`I
`
`k—15 us MAX
`
`#1118 MIN
`
`FIG. 3
`
`Von —
`(>VTP +VTN)
`
`I
`
`VOW
`
`FIG. 5A
`
`v
`
`$5
`
`_
`
`I
`VSS
`
`I
`VTRIP
`
`I
`(VDD'VTP)
`
`.
`VTN'I‘VSS
`
`VIN
`
`I
`VDD
`
`F10- 5B
`
`[FIRST arr TRANSMITTED ,
`HEB—m
`
`--
`
`
`
`
`I
`
`ALL 1's - warm
`ANY 0 - READ
`
`I
`00 - 051271
`01 - 051271-2
`10 — 051271-25
`11 - 051271-4
`
`FIG. 4
`
`W
`
`COMPASS EXH. 1009 - Page 3 of 41
`
`COMPASS EXH. 1009 - Page 3 of 41
`
`
`
`US. Patent
`
`May 11, 1993
`
`Sheet 3 of 17
`
`5,210,846
`
`1- T0 3-vnRE
`comma
`m
`
`E!
`
`m E
`
`!-
`
`mm I
`
`COMPASS EXH. 1009 - Page 4 of 41
`
`COMPASS EXH. 1009 - Page 4 of 41
`
`
`
`US. Patent
`
`May 11, 1993
`
`Sheet 4 of 17
`
`5,210,846
`
`mmdcE
`
`COMPASS EXH. 1009
`
`- Page 5 of 41
`
`COMPASS EXH. 1009 - Page 5 of 41
`
`
`
`US. Patent
`
`May 11, 1993
`
`Sheet 5 of 17
`
`5,210,846
`
`Emma‘
`
`N“.UEN
`
`25.2AI”Ivso:___.
`
`<m.05o»
`
`COMPASS EXH. 1009
`
`- Page 6 of 41
`
`COMPASS EXH. 1009 - Page 6 of 41
`
`
`
`
`US. Patent
`
`May 11, 1993
`
`Sheet 6 of 17
`
`5,210,846
`
`FIG.9A
`
`T0FIG.98
`
`w-l-l-l-l}.
`
`DATIND
`
`CLOCK- RESET9
`
`COMPASS EXH. 1009 - Page 7 of 41
`
`COMPASS EXH. 1009 - Page 7 of 41
`
`
`
`US. Patent
`
`May 11, 1993
`
`Sheet 7 of 17
`
`5,210,846
`
`T0FIG.9A
`
`FIG.QB
`
`COMPASS EXH. 1009 - Page 8 of 41
`
`COMPASS EXH. 1009 - Page 8 of 41
`
`
`
`US. Patent
`
`May 11, 1993
`
`Sheet 8 of 17
`
`5,210,846
`
`
`
`COMPASS EXH. 1009 - Page 9 of 41
`
`COMPASS EXH. 1009 - Page 9 of 41
`
`
`
`US. Patent
`
`May 11, 1993
`
`Sheet 9 of 17
`
`5,210,846
`
`D
`
`COLSEL
`
`DB
`
`
`
`COMPASS EXH. 1009 - Page 10 of 41
`
`COMPASS EXH. 1009 - Page 10 of 41
`
`
`
`US. Patent
`
`May 11, 1993;
`
`Sheet 10 of 17
`
`5,210,846
`
`I/I/I/I/Il.
`
`+ '/////////1
`
`A
`
` (Mfully/71'"
`+.._///Aux/i
`
`
`
`
`
`mm 13'.
`N
`VIII/Ill}
`W ‘? q
`Will/l4
`H CO
`W é “
`m 5
`.
`Vl/I/I/I/A
`E Q,
`W V N
`W E k
`W E
`Will/J
`g:
`
`
`
`
`
`”"0"""111
`
`
`
`(27:532.,
`
`V-
`g'mqnig
`
`
`
`<3
`puma/r;
`g to
`5 (11111111? a
`gag/'3 g N
`
`
`Liam"!
`8
`,
`g¢,,,,,,,,':
`1’ (5
`
`
`5 {11,111.11 5
`z N
`at”);
`Eh.
`”Emmi
`
`
`gamma.)
`
`
`
`®
`
`®
`
`I'IIIIIII'...
`
`
`
`5f////////////;.
`
`+i’///////////'
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`'
`
`
`
`
`
`
`
`
`
`
`‘
`
`
`
`
`
`
`
`
`m
`N
`,;////////4;
`1
`1M 41
`.
`.
`
`
`Vt:
`/‘
`v/
`v
`‘0
`”III///////1 ,
`://////5 j ‘0
`
`
`
`' LW N
`57/ /: u; “
`1//1llllllIII/l
`a; 6: A
`7
`.
`t
`,
`
`
`
`9// £1.
`,
`.
`E
`N
`
`
`
`
`i/////i W “K
`?////////1‘
`5 r / g
`
`
`
`
`
`
`
`
`
`
`
`’l'I’Ill
`
`
`
`®
`
`@
`
`COMPASS EXH. 1009 - Page 11 of 41
`
`COMPASS EXH. 1009 - Page 11 of 41
`
`
`
`US. Patent
`
`May 11, 1993
`
`Sheet 11 of 17
`
`5,210,846
`
`‘1"
`
`®
`
`.15...
`
`mu
`2;»- =-
`
`.{Hlmlnlmnmjegég
`'
`§
`.3222:
`-:—':.-::. 2:
`3!
`2222.222222212222: 2;“
`2222:: 2:22:
`*2
`2222.12222m:2:
`8 (5
`E22222222222222:
`E
`
`222;Illliliflllllilili:222
`
`.....%®
`
`.23...
`
`
`
`‘‘J‘OL““‘L““‘.‘““.““‘“'
`
`
`
`
`
`
`
`
`
`
`
`
`
`I [It'll
`till/,1 .11
`7 2. I [[111 4
`1517 (LN
`
`
`
`
`
`
`
`16A—5
`
`L5
`
`P+
`
`------.
`
`
`
`
`
` ““‘
`
`Q
`
`
`-........l
`i
`'1
`
`
`
`.OIIIIIIIII/
`
`A
`Eco
`
`5g
`«
`g
`:5
`5E
`2
`
`
`
`METALFIG.76A—7
`
`
`+ xfi/fl/
`
`
`
`
`
`
`
`
`
`
`/
`
`COMPASS EXH. 1009 - Page 12 of 41
`
`COMPASS EXH. 1009 - Page 12 of 41
`
`
`
`US. Patent
`
`May 11, 1993
`
`Sheet 12 of 17
`
`5,210,846
`
`(PRIOR ART)
`
`FIG.
`
`1 6B
`
`BATTERY
`
`14
`
`VEXT
`
`F]G.
`
`7 6 C'
`
`VOLTS
`
`3mm
`
`12
`
`.
`28
`
`o vous
`
`(PRIOR AR T)
`
`
`FIG. 160 3’4
`
`COMPASS EXH. 1009 - Page 13 of 41
`
`COMPASS EXH. 1009 - Page 13 of 41
`
`
`
`
`
`3)" 17
`
`FIG. 16H
`
`COMPASS EXH. 1009 - Page 14 of 41
`
`
`
`US. Patent
`
`May 11, 1993
`
`Sheet 14 of 17
`
`5,210,846
`
`-‘WIJI&H‘ 40Ii! 38'
`
`36 P—WELL
`
`32
`
`.52
`
`
` 113A
`
`
`Ill-
`'
`-
`-m
`
`
`
`COMPASS EXH. 1009 - Page 15 of 41
`
`COMPASS EXH. 1009 - Page 15 of 41
`
`
`
`US. Patent
`
`May 11, 1993
`
`Sheet 15 of 17
`
`5,210,846
`
`MARKER (—2.512mA . 2.5mm . 45.00;»)
`15.02 III-II...-
`III-I-I-IE
`==------El
`
`
`
`
`
`
`
`E-
`.-
`III-II
`
`Iflflflfl-ll-II
`
`l'AIIIIIIIIII
`
`
`15—12 III-III... -15-12
`1E ‘2
`E 02
`IE
`DECADE/ON.
`( A)
`
`_ _
`
`-1 ._
`
`FIG. 76M
`
`1E-01
`
`
`
`
`
`
`
`| BAT
`
`1E-01 ----------
`---------a
`I...— In! IGND
`III-I
`any
`DECADE ------n-l‘ DECADE
`/DIV III-In-Iu- /D~
`----n IBAT 7".-
`
`
`..IE- 1...
`
`
`"Ill-II"..-
`!-!l--'A----
`1:42 I-IlI-I-I-I 15-12
`- —
`-1E-01
`‘5 ‘2
`IDQ
`owns/ow.
`(A)
`
`FIG.
`
`7 SP
`
`COMPASS EXH. 1009 - Page 16 of 41
`
`COMPASS EXH. 1009 - Page 16 of 41
`
`
`
`US. Patent
`
`May 11, 1993
`
`Sheet 16 of 17
`
`5,210,846
`
`
`
`COMPASS EXH. 1009 - Page 17 of 41
`
`COMPASS EXH. 1009 - Page 17 of 41
`
`
`
`US. Patent
`
`May 11, 1993
`
`Sheet 17 of 17
`
`5,210,846
`
`
`
`WR
`
`:
`
`."3
`§
`5
`
`m
`
`I
`
`”El 0 WE ISLOT
`I
`g?
`I
`.55
`I
`t—g
`'---------
`I
`READ
`I
`TIME
`l
`SLOT
`I
`
`FIG.20
`
`VIRIIE 1 TIME SLOT
`
`(0R READ TIME SLOT)
`£3
`=6 I
`
`m I!
`
`E
`8
`
`I
`I
`I
`
`-
`
`71111”?
`g a a a {is}
`s .2, 8 8.
`rt. #3.
`‘9.
`2 5 a a s as a
`23 —"'"_"'
`lg OTHER SAMPLES
`3
`(IGNORED)
`
`COMPASS EXH. 1009 - Page 18 of 41
`
`COMPASS EXH. 1009 - Page 18 of 41
`
`
`
`5,210,846
`
`1
`
`ONE-WIRE BUS ARCHITECTURE
`
`CROSS-REFERENCE TO OTHER
`APPLICATIONS
`
`The following applications of common assignee con-
`tain related subject matter, and are believed to have
`effective filing dates identical with that of the present
`application:
`Ser. No. 351,759, Filed May 15, 1989, U.S. Pat. No.
`4,982,371
`entitled
`"COMPACT ELECTRONIC
`MODULE" (DSC-SS);
`Ser. No. 351,760, Filed May 15, 1989, U.S. Pat. No.
`5,091,771 entitled “COMPACT PACKAGE FOR
`ELECTRONIC MODULE" (DSC-86);
`Ser. No. 351,998, Filed May 15, 1989, U.S. Pat. No.
`4,972,377 entitled “LOW-VOLTAGELOW-POWER
`STATIC RAM” (DSC-107);
`Ser. No. 352,598, Filed May 15, 1989, U.S. Pat. No.
`4,945,217 entitled “HAND-HELD WAND FOR
`READING ELECTRONIC TOKENS” (DSC-157);
`Ser. No. 352,596, Filed May 15, 1989, U.S. Pat. No.
`4,948,954 entitled “INTERFACE FOR RECEIVING
`ELECTRONIC TOKENS” (BBC—158);
`Ser. No. 351,999, Filed May 15, 1989, U.S. Pat. No.
`5,045,675 entitled “SERIAL PORT INTERFACE TO
`LOW-VOLTAGE LOW-POWER DATA MOD-
`ULE" (DSC-159);
`Ser. No. 352,142, Filed May 15, 1989, U.S. Pat. No.
`4,995,004 entitled “RAM/ROM HYBRID MEMORY
`ARCHITECTURE” (DSC-l60); and
`Ser. No. 351,997, Filed May 15, 1989, now aban-
`doned entitled “MODULAR DATA SYSTEM”
`(DSC-161).
`Ser. No. 345,144, filed Apr. 28, 1989, entitled “INTE«
`GRATED CIRCUIT WITH IMPROVED PROTEC-
`TION AGAINST NEGATIVE TRANSIENTS”
`(2846-153); all of which are hereby incorporated by
`reference.
`
`BACKGROUND AND SUMMARY OF THE
`INVENTION
`
`The present invention relates to compact electronic
`modules, and to components and packaging for use with
`such modules.
`One of the long-term trends in electronics has been to
`provide higher functionality at lower cost in a more
`compact package. Many pages have been written on
`this long-term trend, and it will not be analyzed here.
`However, the numerous innovations disclosed in the
`present application are believed to contribute to a major
`advance in this direction.
`Innovative Module
`The present application discloses a very compact
`electronic module, which includes an integrated circuit
`(preferably including memory) and a battery. The mod-
`ule is preferably coin-shaped, and the two faces of the
`module are isolated from each other. Host systems can
`read/write access such modules, by using a one-wire-
`bus protocol.
`One-Wireto—Three-Wire Converter
`The module may contain one integrated circuit or
`several, but the integrated circuits in the module prefer-
`ably include a one-wire-to-three-wire converter circuit.
`In the presently preferred embodiment,
`this is inte-
`grated on a single chip with a small amount of serial-
`access memory. However, alternatively the converter
`may be used to provide a standard three-wire serial bus
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`45
`
`50
`
`55
`
`65
`
`2
`output, which provides an interface to one or more
`other chips. The other chips may include, for example,
`electronic keys (such as the DS1207 from Dallas Semi-
`conductor).
`ESD Protection Needs
`A common specification for integrated circuits is the
`ability to withstand five successive electrostatic dis-
`charges (ESDs), each of 1000 volts, at the circuit pads,
`without the leakage current increasing to l microAm-
`pere. However, a de facto standard of 2000 V ESD
`immunity has been springing up for many applications.
`However, even this level of ESD immunity may be
`insufficient for high-noise applications. Specifically, in
`the large.scale systems environment of the presently
`preferred embodiment, the data modules will face some
`unusual integrity requirements. Since the modules may
`be exposed to very rough treatment, in consumer and
`industrial environments, they should preferably have a
`very high level of immunity to electrostatic discharge
`(ESD).
`The electronic data module of the presently preferred
`embodiment
`includes an innovative ESD protection
`diode structure, which helps to protect against data loss
`under severe electrostatic discharge conditions.
`Innovative Packaging Scheme
`To fit the integrated circuit into this very small space,
`an innovative packaging scheme is used in the preferred
`embodiment. A two-part metal container is used, which
`has two shallow concave pieces which fit together. The
`integrated circuit (preferably in a low-height package,
`such as a flat-pack or small out line integrated circuit
`(SOIC)) is mounted on a very small printed circuit
`board (preferably a flexible board), which fits inside the
`container. Laterally spaced from the integrated circuit,
`on the other end of the small board, the board end is
`sandwiched between a battery and a piece of elastic
`conductive material (such as conductive plastic foam).
`Thus, the battery is connected between one face of the
`container and a power conductor on the board. The
`piece of elastic conductive material makes contact be-
`tween a data trace on the board and the other face of the
`container. Another trace on the board makes contact
`directly to the container face on which the battery’s
`ground terminal is connected. Thus, simple wiring on
`the small board, using through-hole vias, suffices to
`route power, ground, and data lines to the integrated
`circuit, while providing a sealed durable package with
`two external contacts.
`
`The battery is preferably a low-voltage battery (1.5
`V, in the preferred embodiment.) This is cheaper, and
`maximizes power efficiency, but requires some innova-
`tive circuit design features to accommodate the electri-
`cal interface. (Electronic watches have often been pow-
`ered by 1.5 V batteries, but such devices do not have
`any direct electrical interface to the outside world. By
`contrast, the module of the presently preferred embodi-
`ment communicates over a one-wire bus which is
`driven by full CMOS voltage levels.)
`Module Mounting and Adhesion
`The electronic token modules can be used in several
`ways. For example, in some embodiments it may be
`preferable to use loose tokens. However, in many appli-
`cations (such as inventory control, machinery mainte-
`nance records, or retail tagging) it may be preferable to
`mount the tokens on the physical items to which the
`data in the individual tokens refers. In this case, the
`token must be mounted so that both terminals of the
`
`COMPASS EXH. 1009 - Page 19 of 41
`
`COMPASS EXH. 1009 - Page 19 of 41
`
`
`
`5,210,846
`
`5
`
`IO
`
`25
`
`35
`
`45
`
`55
`
`65
`
`3
`token can be contacted by the user. In the presently
`preferred embodiment (using a package like that shown
`in FIG. 1A), only one of the possible orientations will
`work. (The inner casing piece 100A must be exposed,
`and therefore, if the token is to be mounted on a surface,
`it is the outer casing piece 1003 which should be ad-
`hered to the surface.)
`For such applications, the packaged modules (in em-
`bodiments using packages like those of FIGS. 1A and
`13) are preferably shipped with doublevsided adhesive
`tape already affixed to the side of the module which is
`to be adhered to a surface (face 1003, in the example of
`FIG. 13).
`Innovative Integrated Circuit
`The module. in the presently preferred embodiment, 15
`contains an integrated circuit which itself includes sev-
`eral innovative features. This integrated circuit, in the
`presently preferred embodiment, includes an electrical
`interface to the one-wire bus (including heavy protec-
`tion against minority carrier injection), a one-wire-to- 20
`three-wire converter circuit, and a small amount of
`seriabaccess memory.
`The integrated circuit, in the preferred embodiment,
`contains 256 bits of serial-access memory. This memory
`is read- or write-accessed as a single block transfer. It is
`contemplated that larger amounts of memory may be
`advantageous. Of course, other types of memory orga-
`nization can be used instead; but for many applications
`it is contemplated that use of a very small amount of
`memory (4K or less) may be particularly advantageous, 30
`since this extends the battery lifetime.
`Low-Voltage SRAM Architecture
`Among the innovative teachings set forth in the pres-
`ent application is a low-power low-voltage CMOS six-
`transistor static random access memory (SRAM),
`which can operate on a power supply voltage which is
`less than the sum of the NMOS and PMOS threshold
`voltages, and which does not include any analog or
`metastable sense amplifier stages. The selected cell is
`allowed to pull one of its bitline pair all the way down
`to ground. Thus, full logic levels appear on the bitline
`pair. Only one line of the bitline pair is connected to the
`following gate stage. Preferably bitline precharge tran-
`sistors are connected to pull up all bitline pairs when-
`ever the RAM is not selected.
`RAM/ROM Hybrid Memory
`A further innovative teaching, in the preferred em-
`bodiment, is the use of RAM/ROM hybrid for a portion
`of the memory array. An innovative memory cell
`is
`used, which can operate as a static RAM, or which can
`be programmed to operate as a read only memory
`(ROM) cell. Thus users who need the extra security
`permitted by ROM encoding can have this capability,
`while users who do not need ROM encoding can use
`off-the-shelf parts as RAM only.
`Chip Series with Unique Hard-wired Identifications
`A further innovative large-scale system concept is to
`use the capability to introduce ROM into the memory
`space to provide memory chips with completely unique
`hard-wired identifications. This provides tremendous
`advantages for security-related needs.
`In this embodiment, an external system can test the
`chip‘s integrity, by performing a read-write-read opera-
`tion on the memory space which is supposed to be
`ROM, and also on a portion of the memory space which
`is expected to be RAM. This will provide at least some
`insurance against the ROM identification being emu-
`lated in RAM. Optionally, the external system can even
`
`4
`test the data output timing, to ascertain whether the
`RAM and ROM outputs are timed identically (and
`therefore to assure that the address inputs are not being
`decoded to address two different chips).
`This also provides advantages of failure protection.
`Very few catastrophes will be able to eradicate the
`hardware encoding of the cells which have been con-
`verted to ROM. (Even if the electrical functionality is
`totally destroyed, the fuse pattern can be read opti-
`cally.) Thus, recovery of these bits may provide useful
`information in failure analysis. (For example, a manu-
`facturing lot number can be cross-referenced from a
`unique identification number in ROM. This would pro-
`vide greatly enhanced capabilities for analysis of late
`failures.
`For another example, where the nonvolatility is elec-
`trically programmable, a system which recognized an
`imminent catastrophic failure (e.g. an avionics system
`facing a crash) might be able to save some data in the
`memory at the last minute.
`Innovative ESD Protection Diode
`The presently preferred embodiment uses an innova-
`tive protection diode structure, in which a significant
`device-level feature, is the provision of an intermediate-
`depth diffusion. This intermediate-depth diffusion will
`have a junction depth (inside the P-well or N-well)
`which is significantly deeper than the source/drain
`junction depth, but significantly shallower than the
`depth of the well. This intermediate-depth diffusion is
`useful in the innovative diode structure described, but
`can also be used for other device structures. For exam-
`ple. this structure provides a compact bipolar transistor
`structure with reasonably high gain. This intermediate-
`depth diffusion can also be used for input protection
`structures (i.e. to provide device structures which will
`rapidly and recoverably break down, when a high‘volt-
`age pulse appears, to discharge the high-voltage pulse
`without damaging the primary circuitry of the chip).
`For another example, this intermediate-depth diffusion
`can also be used to form diffused capacitors with rela-
`tively large capacitance per unit area, or capacitors
`whose capacitance varies greatly with voltage (such
`capacitors are commonly referred to as varactors.)
`A further advantage of this structure, and a further
`innovative teaching set forth herein, is that the innova-
`tive structure can be fabricated with minimal added
`process complexity. An intermediate-depth diffusion is
`added to a standard process flow; but the shallow diffu-
`sions in the battery protection structure simply make
`use of the source/drain implants, and the deepest diffu-
`sion simply uses the N~well (or P-well) fabrication steps.
`For process simplicity, the intermediate-depth diffu-
`sion is most preferably formed by using an implant
`which is identical (in dose and energy) to another im—
`plant used in the same process. The additional junction
`depth is achieved by exposing the earlier implant to a
`high-temperature step before the later implant is per-
`formed, so that the earlier implant will have a corre-
`spondingly greater diffusion length (integral (DOG-5).
`A variety of “substra ” structures are commonly
`used for integrated circuits, and far more have been
`proposed or have seen limited use. For example, the
`“substrate" which surrounds the N-wells and P-wells is
`
`often an epitaxial layer atop a much more heavily doped
`underlying layer. For another example, the N-wells and
`P-wells are commonly formed by separate implantation
`(and drive-in) steps, and such processes are referred to
`as “twin tub” processes; but alternatively one of these
`
`COMPASS EXH. 1009 - Page 20 of 41
`
`COMPASS EXH. 1009 - Page 20 of 41
`
`
`
`5,210,846
`
`5
`steps may be omitted, so that, for example, the PMOS
`devices might be formed directly in an N-type upper
`substrate portion. Other important structure types in-
`clude silicon-on-insulator structures and full dielectric
`isolation structures, where there is no electrically con-
`tinuous body linking all of the wells. It is important to
`note that the innovative teachings set forth herein can
`advantageously be adapted to a tremendous variety of
`substrate structures,
`including not only the embodi-
`ments listed or mentioned, but also many others.
`It should be noted that the disclosed families of de-
`vices structures can also be used for a variety of other
`purposes. in particular, the disclosed structure provides
`a diode structure which may be adapted for use in other
`types of device structures,
`in very-low-power inte-
`grated circuit applications.
`It should also be noted that some prior art CMOS
`structures have used guard ring structures to suppress
`latchup. The problem of latchup (suppressing the para-
`sitic thyristor) is a quite different problem from the
`leakage problems discussed above, but in both cases
`collection of minority carriers is desirable. Guard ring
`structures are commonly used to surround locations
`(such as output drivers) where transient signals are most
`likely to cause injection of minority carriers. (A suffi—
`cient injection of minority carriers could fire the para-
`sitic thyristor, and thus lead to latchup.)
`In the preferred class of embodiments, the innovative
`diffusion structure described is used to conserve the
`charge in the battery. One drain on the battery is caused
`by negative excursions on an incoming data line (for
`example, when a negative voltage spike occurs due to
`an electrostatic discharge (ESD) event). In a normal
`battery-powered integrated circuit, the current drawn
`during such a negative voltage surge would be drawn
`both from the ground connection and also from the
`power supply connection. However,
`in stringently
`power-limited applications, even this amount of cur-
`rent, over the lifetime of the part, can use enough of the
`battery capacity to shorten the part‘s lifetime substan-
`tially.
`That is, when a negative transient occurs, a large
`number of electrons will be injected. If these electrons
`are allowed to diffuse freely many of them will diffuse
`toward the high-potential regions which are connected
`to the battery. This charge transfer reduces the total
`charge available during the lifetime of the battery.
`The shielded diode structure of FIG. 16K is pro-
`tected: almost all electrons injected at first junction 111
`will be collected at second junction 112. By contrast, a
`simple field effect transistor (FET) output driver, like
`transistor 150 in FIG. 16M, is not isolated: when the
`drain junction of such an NMOS PET is forward bi-
`ased, electrons will be released into substrate 140, and
`many of these electrons can then diffuse to regions of
`high potential.
`Therefore, a further innovative teaching is to use the
`innovative diffusion structure to source current to nega-
`tive transients which may occur on the I/O lines of a
`chip. In this embodiment, an 1/0 line is connected so
`that the first junction (in a structure as described above)
`will be forward biased when the I/O line goes negative,
`and the other side of the first junction is connected to
`ground potential. Thus. when a negative-going tran-
`sient occurs, current will be sourced, through the first
`junction, from ground.
`When a negative-going transient occurs, some cur-
`rent will also be sourced, at the output transistor which
`
`10
`
`15
`
`20
`
`25
`
`3D
`
`35
`
`4O
`
`45
`
`50
`
`55
`
`65
`
`6
`drives the [/0 line, and some of this current component
`will cause minority carrier diffusion; but the use of this
`innovative teaching helps to reduce the amount of cur-
`rent sourced which can cause minority carrier diffusion.
`Preferably the area of the first junction is substantially
`larger than that of the junction area of the source/drain
`diffusion, in the output transistor, which is connected to
`the power supply.
`This innovative teaching also has two further advan-
`tages. First, the reduced risk of minority carrier injec-
`tion means that the risk of stored data states being upset
`by transient signals is reduced. Second,
`the risk of
`latchup is reduced.
`Thus, this innovative teaching advantageously pro-
`vides a battery-powered integrated circuit which is
`protected against battery depletion by electrical noise
`appearing at input/output connections. This innovative
`teaching may be particularly advantageous in inte-
`grated circuits which are intended for use in systems
`where high levels of noise must be tolerated.
`Innovative Bus Organization
`To communicate with this memory, in the preferred
`embodiment, an innovative one-wire bus protocol is
`used. This protocol is well adapted for interface to the
`low-cost architecture of the module of the presently
`preferred embodiment.
`Time-Domain Relations
`A bidirectional one-wire bus requires some use of
`time-domain or frequency-domain relations, to track the
`two half-channels of communication.
`It is quite possible to put an accurate time base in a
`low-power integrated circuit, using CMOS oscillators
`stabilized with quartz crystals; but the use of such tech-
`niques adds to the cost of the part. A crude time base
`can be provided simply by using an oscillator which is
`not stabilized. However, the response time of a simple
`timing circuit will be dependent on processing parame-
`ters. In conventional integrated circuit processing, there
`will normally be significant variation in parameters such
`as layer thickness, 1ine-to~space ratio, and net dopant
`concentration in various locations. Thus, the electrical
`parameters, such as the series resistance of a polysilicon
`resistor of a given nominal dimension, can easily vary
`by i20% or more, even in a well-controlled process.
`This means that the net speed of a timing circuit can
`vary by even more, since the net speed will be depen-
`dent on several electrical parameters, which may vary
`together or in opposition.
`Parameter variation can be compensated for, by test-
`ing a newly fabricated wafer and programming ele-
`ments on-chip (such as trimming capacitors) to adjust
`the net delay of timing elements; but this additional
`manufacturing step adds significant expense.
`Low-Voltage CMOS Logic
`Moreover, in a low-voltage CMOS system (i.e. where
`the supply voltage is less than the sum of the PMOS and
`NMOS threshold voltages), achieving even a crude
`time base is much more difficult. This is due to the
`transfer characteristics of a logic gate in this technol-
`ogy.
`FIG. 5A shows the voltage transfer characteristics
`(Vom- graphed as a function of VIN) for an inverter in
`conventional CMOS technology (e.g. where the supply
`voltage Vppis about 5 Volts, and the PMOS threshold
`voltage V nand the NMOS threshold voltage Vmboth
`have magnitudes in the range of about 0.8 V to L] V.)
`Suppose that the input voltage VIN was initially at
`ground voltage V55 (0 V), so that the inverter’s NMOS
`
`COMPASS EXH. 1009 - Page 21 of 41
`
`COMPASS EXH. 1009 - Page 21 of 41
`
`
`
`5,210,846
`
`7
`transistor is off and the inverter‘s PMOS transistor is on.
`NOW, as VIN starts to rise, Vow-will stay at Van until
`VIN rises to VTN. At this point the NMOS device will
`start to pass current. However, the NMOS device will
`not be able to overpower the PMOS device until the
`voltage reaches a trip point Vnup. The trip point volt-
`age V flap is welhdefmed for each particular logic gate,
`but is dependent on the device dimensions. (If the width
`of the PMOS device is increased, or the length of the
`PMOS device decreased, or the width of the NMOS
`device is decreased, or the length of the NMOS device
`increased, then the NMOS device will have more diffi-
`culty in overpowering the PMOS device, and the trip
`point Vnupwill occur at a higher voltage.) As the input
`voltage Vmincreases, the NMOS device will pass more
`current and the PMOS device will pass less current,
`until at voltage VpD-VTP the PMOS transistor turns
`off.
`By contrast, the transfer characteristic of a lowwolt-
`age CMOS inverter, as shown in FIG. SB, are quite
`different. (Suppose, for example, that Vpp= 1.5 V, and
`V7~p=Vm=O.9 V. Thus, note that FIGS. 5A and SB
`are not drawn to the same scale.) Here there is no region
`where both the NMOS and PMOS devices are on.
`When the input voltage Vm increases above VpD-V Tp
`(0.6 V in this example), the PMOS device will turn off,
`but the NMOS device has not yet turned on. Therefore,
`until the input voltage increases to an (0.9 V in this
`example), the output node will be floated. (The node
`capacitance usually faces a fairly high-impedance load,
`and therefore, within the time normally required for the
`input voltage to swing across this voltage range, the
`output voltage will remain fairly constant. Moreover, a
`weak latch will typically be added to bridge this dead
`zone.) Thus, the transfer characteristic shown includes
`a significant hysteresis, since, between VDD-Vrp and
`VrN. the output voltage is dependent on the direction
`of change of the input voltage.
`Error of Crude Time Base
`A response curve like that of FIG. 58 makes it more
`difficult to control the net delay of a circuit, since small
`changes in electrical parameters may produce large
`changes in the response characteristics. Thus, in such
`low-voltage technOIOgy. the frequency of an unstabil-
`ized oscillator may easily vary over a very large range
`(for example, over a range of 4:1), even in a well—con—
`trolled process.
`The system of the presently preferred embodiment
`makes use of such an unstabilized oscillator to provide a
`crude time base within the module. This crude time
`base, together with electrical relationships, provides the
`necessary referent for communication over a one-wire
`bus. The use of a one-wire bus is very advantageous to
`the system user.
`Electrical 1/0 Relationships
`The bus protocol is also designed to minimize the
`charge transfer out of the battery in the module. This is
`done by using an “open-collector" type architecture.
`The protocol has been specified so that the module
`never sources current to the data line, but only sinks
`current.
`When a data module is in contact with a host system,
`the host system intially pulls up the data line. (The
`module also preferably contains a very high-impedance
`pull-down resistor at this node, but this is included, in
`the preferred embodiment, merely to avoid the risk of
`floating nodes.) The host system initiates each stage of a
`data transfer operation by driving the data line low. The
`
`10
`
`15
`
`25
`
`30
`
`35
`
`45
`
`55
`
`65
`
`8
`module detects this falling edge, and one of several
`further events can then occur.
`If the module is being read (as previously determined
`by overhead bits), the module, after seeing the falling
`edge which starts the cycle, either will or will not turn
`on its NMOS pull-down transistor, depending on the
`value of the data bit being read at that cycle. When the
`NMOS pull-down is turned on, the module lets its pre-
`set timing period elapse. and then turns off the NMOS
`pull-down. Thus. when the system wants to read from
`the module, it applies a falling edge, waits a short time
`to be sure that the module has received the falling edge,
`and then attempts to pull up the data line, using a pull-
`up resistor which is not strong enough to overpower
`the NMOS pull-down transistor in the module. After
`waiting a sufficient time for the pull-up resistor to have
`raised the line to a high level (if the NMOS pull-down
`is off), the system tests the data voltage to ascertain the
`data bit. The system then waits for the maximum time
`period of the module delay to elapse, plus enough time
`for the data line to