United States Patent [19]
`Lee (cid:9)
`
`1111111111111111111111111111ER11 1,1111111111111111111111111111
`
`5,210,846
`[11) Patent Number: (cid:9)
`[45] Date of Patent: May 11, 1993
`
`[54] ONE-WIRE BUS ARCHITECTURE
`[75] Inventor: Robert D. Lee, Denton, Tex.
`[73] Assignee: Dallas Semiconductor Corporation,
`Dallas, Tex.
`[21] Appl. No.: 352,581
`[22] Filed: (cid:9)
`May 15, 1989
`[51] Int. Q,5 (cid:9)
` GO6F 13/18; G06K 19/06
`[52] U.S. Cl (cid:9)
` 395/425; 395/400;
`364/DIG. 1; 235/492; 365/189.03; 365/189.06
`[58] Field of Search (cid:9)
` 365/189.03, 189.06,
`365/194; 357/74; 335/488, 489, 492; 368/87,
`88; 70/228; 395/425, 400; 340/825.08
`References Cited
`U.S. PATENT DOCUMENTS
`4,007.355 2/1977 Moreno (cid:9)
`4,196,577 4/1980 Ohno et al. (cid:9)
`4,272,838 6/1981 Kasama et al. (cid:9)
`4,480,178 10/1984 Miller, II et al. (cid:9)
`4,621,190 11/1986 Saito et al. (cid:9)
`4,845,609 7/1989 Lighthurt et al. (cid:9)
`4,868,409 9/1989 Tanaka et al. (cid:9)
`4,982,371 1/1991 Bolan et al. (cid:9)
`5,013,898 5/1991 Glasspool (cid:9)
`5,045,675 9/1991 Curry (cid:9)
`Primary Examiner—Joseph L. Dixon
`
` 235/492
` 368/82
` 368/88
` 235/380
` 235/492
` 395/425
` 70/2'78
` 365/228
` 235/449
` 235/441
`
`[56] (cid:9)
`
`Assistant Examiner—Jack A. Lane
`Attorney, Agent, or Firm—Worsham, Forsythe, Sampels
`& Wooldridge
`[57) (cid:9)
`ABSTRACT
`A system architecture which provides efficient data
`communication, over a one-wire bus, with a portable
`data module which does not necessarily include any
`accurate time delay circuit whatsoever. The time delay
`circuit in the module can be extremely crude. An open-
`collector architecture is used, with electrical relations
`defined to absolutely minimize the drain on the portable
`module's battery. A protocol has been specified so that
`the module never sources current to a data line of the
`one-wire bus, but only sinks current. The protocol in-
`cludes signals for read; write-zero; write-one; and reset.
`Each one-bit transaction is initiated by a falling edge of
`a voltage signal from the host. The time delay circuit in
`the module defines a delay, after which (in write mode)
`the module tests the data state of the data line. In read
`mode, after a falling edge of a voltage signal from the
`host the module does or does not turn on a pull-down
`transistor, depending on the value of the bit read. Thus,
`the host system, after the falling edge, attempts to pull
`the data line high again, and then tests the potential of
`the data line to ascertain the value of the bit read.
`
`6 Claims, 17 Drawing Sheets
`
`vcc
`1204 \*.
`
`5K
`
`OPEN
`DRAIN
`
`500K
`
`1202 (cid:9)
`
`TX
`
`RX
`
`HOST
`
`TOKEN
`
`RX
`
`I TX
`100 OHM MOSFET
`
`AMEX 1008 - Page 1 of 41
`
`(cid:9)
`(cid:9)
`

`

`U.S. Patent (cid:9)
`
`May 11, 1993
`
`Sheet 1 of 17 (cid:9)
`
`5,210,846
`
`0140
`
`0100A
`
`FIG. 1 A
`
`01008
`
`0120'
`0140 1
`
`0144
`
`LI
`
`0110
`
`0130'
`
`0142
`
`FIG. 1 B
`
`WRITE ONE TIME SLOT
`
`AS Min
`
`I
`
`
`I (cid:9)
`
`60 /LS Min (cid:9)
`
`01
`
`START OF NEXT CYCLE
`
`I
`II
`
`I
`I re-15 µS Max (cid:9)
`k-, AS Min
`
`FIG. 2A
`
`—04 10-1µS Min
`I
`
`_ZU
`
`(cid:9)
`
`WRITE ZERO TIME SLOT
`
`60µS Min
`
`1
`I I I START OF NEXT CYCLE
`
`
`
`I1 I~I
`
`FIG. 2B
`
`AMEX 1008 - Page 2 of 41
`
`(cid:9)
`

`

`U.S. Patent (cid:9)
`
`May 11, 1993 (cid:9)
`
`Sheet 2 of 17 (cid:9)
`
`5,210,846
`
`READ DATA TIME SLOTS
`
`60 pS MIN
`
`I START OF NEXT CYCLE
`I I
`II
`
`
`
`-01 14.-1 AS MIN
`I (cid:9)
`I
`12/ (cid:9)
`
`///////////// (cid:9)
`1.0-15 AS MAX
`ro-1 AS MIN
`
`FIG. 3
`
`VDD -
`(Alm +VTN)
`
`VOUT
`
`VSS
`
`VDD-
`
`VouT
`
`FIG. 5A
`
`VSS (cid:9)
`
`i (cid:9)
`VTN+Vss (cid:9)
`
`VTRIP (cid:9)
`
`(VDD-VTP)
`
`VIN
`
`VDD
`
`FIG. 5B
`
`1. S S IVW:R/W:R/W:R/W:Rni
`
`of-- FIRST BIT TRANSMITTED
`
`— —1
`I
`I (cid:9)
`T
`4 (cid:9)
`I
`I (cid:9)
`I
`I (cid:9)
`
`I (cid:9)
`
`1
`
`ALL 1'S - WRITE
`ANY 0 - READ
`
`00 - DS1271
`01 - DS1271-2
`10 - DS1271-3
`11 - DS1271-4
`FIG. 4
`COMMAND WORD
`
`VSS
`
`VSS (cid:9)
`
`I
`
`INTNI+VSS) (cid:9)
`
`A, (cid:9)
`
`VIN
`
`VDD
`
`AMEX 1008 - Page 3 of 41
`
`(cid:9)
`

`

`U.S. Patent (cid:9)
`
`May 11, 1993 (cid:9)
`
`Sheet 3 of 17 (cid:9)
`
`5,210,846
`
`FIG. 6
`
`1- TO 3-WIRE
`CONVERTER
`630
`
`5_42 (cid:9)
`
`BAT 0 (cid:9)
`
`
`
`•613
`
`644
`
`RAM
`..om
`
`I
`
`642
`
`I (cid:9)
`
`
`
`CONTROL
`620
`
`611
`
`AND
`ESD
`310
`
`o
`DATA
`
`IOPAD o (cid:9)
`
`lOPAD
`
`IOPAD
`
`1-
`3—WIRE
`_62
`
`FIG. 7
`
`Q0
`Q1
`Q2
`Q3
`Q4
`Q5
`Q6
`Q7
`Q8
`Q9
`
`CONTROL
`620
`
`CLOCK
`
`DAT1N
`
`•
`
`RESET
`
`QXF1
`
`QXF1
`
`210
`DATOUT
`
`61
`
`0
`GROUND
`
`Ul
`
`RAM
`
`DATOUT
`
`AMEX 1008 - Page 4 of 41
`
`

`

`gly,' •ssa
`
`;u
`
`£661 'II AvIN
`
`a JO t pails
`
`805 (cid:9)
`
`VDD
`
`807
`
`
`
`IOPAD
`
`804
`
`806
`
`819
`
`VDD
`
`818
`
`174--
`
`TuN-815
`
`FIG. 8A
`
`TO FIG. 8B
`
`QXF1
`
`CLOCK
`
`DATIN
`
`AMEX 1008 - Page 5 of 41
`
`

`

`alycl 'S'il
`
`;u
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`£661 li ABIN
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`LI JO S P.M
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`TO FIG. 8A
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`
`ADD
`
`(cid:9)C> RESET
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`Y._
`
`10010111•111 .‘
`
`FIG. 8B 830
`
`832
`
`VCC
`1204
`Nik.
`
`5K
`
`1202 (cid:9)
`
`
`TX
`
`RX
`
`OPEN
`DRAIN
`
`500K
`
`RX
`
`TX
`100 OHM MOSFET
`=
`
`HOST -is- -IP' TOKEN
`
`FIG. 12
`
`AMEX 1008 - Page 6 of 41
`
`(cid:9)
`

`

`lualsil Vfl
`
`£661 'II SEW
`
`LI Jo 9 laatiS
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`9 1 rz 922 ri 923 ri 924 x1925 rl 926 rz927 ri928
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`940
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`950
`
`938
`L
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`RESET
`CLOCK
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`945
`
`TO FIG. 98
`
`FIG. 9A
`
`AMEX 1008 - Page 7 of 41
`
`

`

`1
`
`.
`I
`.
`
`4ualud *S
`
`£661 `II iCBI,I
`
`934
`
`FIG. 9B
`
`TO FIG. 9A
`
`912
`
`913
`
`914
`
`915
`
`916
`
`918
`
`919
`
`908
`
`909
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`917
`i-1.--
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`i 910
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`911
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`932
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`910
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`T
`
`7 7 V 7
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`T
`'114 ;11f ;11
`
`05 (cid:9)
`
`06 (cid:9)
`
`Q7 (cid:9)
`
`Q8 (cid:9)
`
`T
`
`Q9
`
`10PAD
`
`DATAOUT
`
`210
`
`AMEX 1008 - Page 8 of 41
`
`

`

`U.S. Patent (cid:9)
`
`May 11, 1993 (cid:9)
`
`Sheet 8 of 17 (cid:9)
`
`5,210,846
`
`1032
`
`1034
`
`1010
`
`1020
`
`1030
`
`C(15:0) CB(15:0)
`
`RAM
`644/646
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`RE
`
`SDOUTB
`
`Q1
`Q2
`03 C:*---
`Q0
`QB
`
`DioN
`
`DATOUT <0.---
`SDOUTB
`
`FIG. 10 (cid:9)
`
`ER2 C>-•- ER2
`Q5 (cid:9)
`Q5
`Q6 (cid:9)
`Q6
`Q7
`0*--- Q7
`Q9
`Q4
`Q4 (cid:9)
`
`RESET
`
`
`
`DATOUT
`
`1330
`
`1332
`
`FIG. 13
`
`1310
`
`der1320
`
`f:79-1
`
`ADD ADD
`
`AMEX 1008 - Page 9 of 41
`
`

`

`U.S. Patent (cid:9)
`
`May 11, 1993 (cid:9)
`
`Sheet 9 of 17 (cid:9)
`
`5,210,846
`
`FIG. 14
`
`1512
`
`1516
`
`1510
`
`FIG. 15A
`
`FIG. 15B
`
`1590
`*---'
`
`FIG. 15C
`
`AMEX 1008 - Page 10 of 41
`
`

`

`lua4Ecl 'S'fl
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`LI JO in Pails
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`FIG. 16A-1
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`DEPLETION (INTERMEDIATE-DEPTH P-TYPE)
`FIG. 1 6A-2
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`FIG. 1 6A-3
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`N+ (COMPLEMENTED)
`FIG. 1 6A-4
`
`AMEX 1008 - Page 11 of 41
`
`(cid:9)
`(cid:9)
`

`

`U.S. Patent (cid:9)
`
`May 11, 1993 (cid:9)
`
`Sheet 11 of 17 (cid:9)
`
`5,210,846
`
`•••
`
`• (cid:9)i.e./ ••••
`
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`AMEX 1008 - Page 12 of 41
`
`(cid:9)
`

`

`U.S. Patent (cid:9)
`
`May 11, 1993 (cid:9)
`
`Sheet 12 of 17 (cid:9)
`
`5,210,846
`
`0 VOLTS (cid:9)
`28 (cid:9)
`
`26 (cid:9)
`
`14 (cid:9)
`
`VEXT (cid:9)
`
`BATTERY
`12
`
`FIG. 16B
`(PRIOR ART)
`
`BATTERY
`12
`
`FIG. 16E
`
`BATTERY
`12 (cid:9)
`
`28.
`0 VOLTS
`
`14
`VEkr
`
`FIG. 16C
`(PRIOR ART)
`
`44 (cid:9)
`
`43
`
`0 VOLTS
`28
`
`26 14
`
`
`VExr
`
`43 (cid:9)
`
`BATTERY
`12/
`
`,
`
`40
`IRMA
`112 36 P—WELL 111 348d
`32
`
`1/4 (cid:9)
`
`P—WELL 24 42
`
`
`38
`
`1/4 (cid:9)
`
`25
`
`N —TYPE
`FIG. 16D
`
`48_1
`1
`N+ L2-t_-k
`
`40
`
`N+
`
`36
`
`FIG. 16G 34
`
`AMEX 1008 - Page 13 of 41
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`(cid:9)
`

`

`U.S. Patent (cid:9)
`
`May 11, 1993 (cid:9)
`
`Sheet 13 of 17 (cid:9)
`
`5,210,846
`
`43
`
`/
`
`32
`
`28 (cid:9)
`
`FIG. 1 6F
`
`20 7-
`
`19 =
`
`18
`LOG (cid:9)
`CONCENTRATION _
`(ATOMS/cm3) 17 :
`
`FIG. 16H
`
`167
`
`15=
`
`14
`
`I
`I (cid:9)
`I (cid:9)
`1.5 (cid:9)
`1.0 (cid:9)
`0.5 (cid:9)
`0.0 (cid:9)
`DISTANCE FROM SURFACE (MICRONS)
`
`2.0
`
`AMEX 1008 - Page 14 of 41
`
`

`

`U.S. Patent (cid:9)
`
`May 11, 1993 (cid:9)
`
`Sheet 14 of 17 (cid:9)
`
`5,210,846
`
`0 VOLTS (cid:9)
`28 26 141 (cid:9)
`t (cid:9)
`la/
`42AL) 2
`,f-±.) 4044i)
`s_ 38
`36 p-
`1,25 (cid:9)
`N-TYPE
`INSULATOR
`
`
`VEr43
`
`BATTERY FIG. 161
`12
`
`40
`34
`
`` 38
`
`32
`
`5.2
`
`P-WELL
`
`24 (cid:9)
`
`0 VOLTS (cid:9)
`VEXT (cid:9)
`28 26 141 (cid:9)
`laii
`42Atit1 2
`-.-25 (cid:9)
`N-EPI
`j
`
`P-WELL
`S
`24 (cid:9)
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`N-1YPE
`
`
`43
`
`
` 38
`
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`
`12 (cid:9)
`
`FIG. 16J
`
`40
`
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`
`38
`34
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`
`I
`
`'
`32
`
`FIG. 16K
`
`133
`VDD0--2-
`122 (cid:9)
`
`113A
`l.../1±J
`113
`
`N
`
`121A I (cid:9)
`
`113A
`
`140A
`
`111
`
`121B
`
`J
`
`P 140
`
`112
`
`P 140
`
`BAT
`3V
`
`iB
`
`
`SUB (cid:9)
`
`P SUB
`
`t
`
`P depl
`N WELL
`
`FIG. 16L
`1c
`
`1,4
`
`N WELL
`
`AMEX 1008 - Page 15 of 41
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`(cid:9)
`

`

`U.S. Patent (cid:9)
`
`May 11, 1993 (cid:9)
`
`Sheet 15 of 17 (cid:9)
`
`5,210,846
`
`MARKER (-2.512mA , 2.510mA , -45.00pA)
`
`1E-02
`
`B
`
`DECADE
`/DIV
`
`1E-12 (cid:9)
`
`-1E-12
`
`1E-01
`
`I BAT
`
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`/DIV
`
`1E-12
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`
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`
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`
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`
`DECADE
`/DIV
`
`'SUB.
`
`-1E-12
`-1E-02
`
`IE (cid:9)
`
`DECADE/DIV. (cid:9)
`
`( A)
`
`FIG. 16M
`
`1E-01
`
`I GND
`
`DECADE
`/DIV
`
`I GND (cid:9)
`
`
`
`I BAT
`
`r-
`
`IDQ (cid:9)
`
`DECADE/DIV. (cid:9)
`
`(A)
`
`FIG. 16P
`
`1E-12
`-1E-01
`
`AMEX 1008 - Page 16 of 41
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`

`

`U.S. Patent (cid:9)
`
`May 11, 1993 (cid:9)
`
`Sheet 16 of 17 (cid:9)
`
`5,210,846
`
`st•
`
`0-
`
`Cs4
`II- - v.-
`
`....
`
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`
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`
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`
`-4-
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`
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`
`co
`
`s
`
`8
`
`0
`
`L
`
`CI
`
`AMEX 1008 - Page 17 of 41
`
`

`

`U.S. Patent (cid:9)
`
`May 11, 1993 (cid:9)
`
`Sheet 17 of 17 (cid:9)
`
`5,210,846
`
`RTS 4
`
`DTR 20
`
`GND 7
`
`SERIAL 3 (cid:9)
`IN
`SERIAL 2 (cid:9)
`OUT
`
`1914 (cid:9)
`
`1900A
`
`DATA 100A
`
`v._..,. 100B
`
`GROUND
`
`411.1912 (cid:9)
`
`19008
`
`FIG. 19
`
`11.=.1.± I= lc, ciI—I.—I'—I—I— I.-I
`
`60.764 /As (cid:9)
`
`•-8.698.
`
`60.764 ps
`
`WRITE 0 TIME SLOT
`I
`I (cid:9)
`
`WRITE 1 TIME SLOT
`(OR READ TIME SLOT)
`a a
`to• —
`co 4
`
`N
`
`READ
`TIME
`SLOT
`
`FIG. 20
`
`CO (cid:9)
`
`• (cid:9)
`C•J (cid:9)
`
`111
`t tit t tt
`in VS
`a.' (cid:9)
`4. 4.
`• C•4
`"It f".:
`•
`t g (cid:9)
`•
`
`•
`
`r (cid:9)
`
`10
`
`a3 (cid:9)
`
`OTHER SAMPLES
`(IGNORED)
`
`AMEX 1008 - Page 18 of 41
`
`

`

`5,210,846
`
`ONE-WIRE BUS ARCHITECTURE
`
`5
`
`CROSS-REFERENCE TO OTHER
`APPLICATIONS (cid:9)
`The following applications of common assignee con-
`tain related subject matter, and are believed to have
`effective filing dates identical with that of the present
`application:
`Ser. No. 351,759, Filed May 15, 1989, U.S. Pat. No.
`4,982,371 entitled "COMPACT ELECTRONIC
`MODULE" (DSC-85);
`Ser. No. 351,760, Filed May 15, 1989, U.S. Pat. No.
`5,091,771 entitled "COMPACT PACKAGE FOR
`ELECTRONIC MODULE" (DSC-86);
`Ser. No. 351,998, Filed May 15, 1989, U.S. Pat. No.
`4,972,377 entitled "LOW-VOLTAGELOW-POWER
`STATIC RAM" (DSC-107);
`Ser. No. 352,598, Filed May 15, 1989, U.S. Pat. No.
`4,945,217 entitled "HAND-HELD WAND FOR
`READING ELECTRONIC TOKENS" (DSC-157);
`Ser. No. 352,596, Filed May 15, 1989, U.S. Pat. No.
`4,948,954 entitled "INTERFACE FOR RECEIVING
`ELECTRONIC TOKENS" (DSC-158);
`Ser. No. 351,999, Filed May 15, 1989, U.S. Pat. No.
`5,045,675 entitled "SERIAL PORT INTERFACE TO
`LOW-VOLTAGE LOW-POWER DATA MOD-
`ULE" (DSC-159);
`Ser. No. 352,142, Filed May 15, 1989, U.S. Pat. No.
`4,995,004 entitled "RAM/ROM HYBRID MEMORY
`ARCHITECTURE" (DSC-160); and
`Ser. No. 351,997, Filed May 15, 1989, now aban-
`doned entitled "MODULAR DATA SYSTEM"
`(DSC-161).
`Ser. No. 345,144, filed Apr. 28, 1989, entitled "INTE- 35
`GRATED CIRCUIT WITH IMPROVED PROTEC-
`TION AGAINST NEGATIVE TRANSIENTS"
`(2846-153); all of which are hereby incorporated by
`reference.
`
`2
`output, which provides an interface to one or more
`other chips. The other chips may include, for example,
`electronic keys (such as the DS1207 from Dallas Semi-
`conductor).
`ESD Protection Needs
`A common specification for integrated circuits is the
`ability to withstand five successive electrostatic dis-
`charges (ESDs), each of 1000 volts, at the circuit pads,
`without the leakage current increasing to 1 microAm-
`pere. However, a de facto standard of 2000 V ESD
`immunity has been springing up for many applications.
`However, even this level of ESD immunity may be
`insufficient for high-noise applications. Specifically, in
`the large-scale systems environment of the presently
`preferred embodiment, the data modules will face some
`unusual integrity requirements. Since the modules may
`be exposed to very rough treatment, in consumer and
`industrial environments, they should preferably have a
`very high level of immunity to electrostatic discharge
`(ESD).
`The electronic data module of the presently preferred
`embodiment includes an innovative ESD protection
`diode structure, which helps to protect against data loss
`under severe electrostatic discharge conditions.
`Innovative Packaging Scheme
`To fit the integrated circuit into this very small space,
`an innovative packaging scheme is used in the preferred
`embodiment. A two-part metal container is used, which
`30 has two shallow concave pieces which fit together. The
`integrated circuit (preferably in a low-height package,
`such as a flat-pack or small out line integrated circuit
`(SOIC)) is mounted on a very small printed circuit
`board (preferably a flexible board), which fits inside the
`container. Laterally spaced from the integrated circuit,
`on the other end of the small board, the board end is
`sandwiched between a battery and a piece of elastic
`conductive material (such as conductive plastic foam).
`Thus, the battery is connected between one face of the
`container and a power conductor on the board. The
`piece of elastic conductive material makes contact be-
`tween a data trace on the board and the other face of the
`container. Another trace on the board makes contact
`directly to the container face on which the battery's
`ground terminal is connected. Thus, simple wiring on
`the small board, using through-hole vias, suffices to
`route power, ground, and data lines to the integrated
`circuit, while providing a sealed durable package with
`two external contacts.
`The battery is preferably a low-voltage battery (1.5
`V, in the preferred embodiment.) This is cheaper, and
`maximi7es power efficiency, but requires some innova-
`tive circuit design features to accommodate the electri-
`cal interface. (Electronic watches have often been pow-
`ered by 1.5 V batteries, but such devices do not have
`any direct electrical interface to the outside world. By
`contrast, the module of the presently preferred embodi-
`ment communicates over a one-wire bus which is
`driven by full CMOS voltage levels.)
`Module Mounting and Adhesion
`The electronic token modules can be used in several
`ways. For example, in some embodiments it may be
`preferable to use loose tokens. However, in many appli-
`cations (such as inventory control, machinery mainte-
`nance records, or retail tagging) it may be preferable to
`mount the tokens on the physical items to which the
`data in the individual tokens refers. In this case, the
`token must be mounted so that both terminals of the
`
`10
`
`15
`
`20
`
`25
`
`40
`
`45
`
`BACKGROUND AND SUMMARY OF THE
`INVENTION
`The present invention relates to compact electronic
`modules, and to components and packaging for use with
`such modules. (cid:9)
`One of the long-term trends in electronics has been to
`provide higher functionality at lower cost in a more
`compact package. Many pages have been written on
`this long-term trend, and it will not be analyzed here.
`However, the numerous innovations disclosed in the 50
`present application are believed to contribute to a major
`advance in this direction.
`Innovative Module
`The present application discloses a very compact
`electronic module, which includes an integrated circuit 55
`(preferably including memory) and a battery. The mod-
`ule is preferably coin-shaped, and the two faces of the
`module are isolated from each other. Host systems can
`read/write access such modules, by using a one-wire-
`bus protocol. (cid:9)
`One-Wire-to-Three-Wire Converter
`The module may contain one integrated circuit or
`several, but the integrated circuits in the module prefer-
`ably include a one-wire-to-three-wire converter circuit.
`In the presently preferred embodiment, this is inte- 65
`grated on a single chip with a small amount of serial-
`access memory. However, alternatively the converter
`may be used to provide a standard three-wire serial bus
`
`60
`
`AMEX 1008 - Page 19 of 41
`
`

`

`5,210,846
`
`45
`
`3
`token can be contacted by the user. In the presently
`preferred embodiment (using a package like that shown
`in FIG. 1A), only one of the possible orientations will
`work. (The inner casing piece 100A must be exposed,
`and therefore, if the token is to be mounted on a surface, 5
`it is the outer casing piece 100B which should be ad-
`hered to the surface.)
`For such applications, the packaged modules (in em-
`bodiments using packages like those of FIGS. lA and
`1B) are preferably shipped with double-sided adhesive 10
`tape already affixed to the side of the module which is
`to be adhered to a surface (face 100B, in the example of
`FIG. 1B).
`Innovative Integrated Circuit
`The module, in the presently preferred embodiment, 15
`contains an integrated circuit which itself includes sev-
`eral innovative features. This integrated circuit, in the
`presently preferred embodiment, includes an electrical
`interface to the one-wire bus (including heavy protec-
`tion against minority carrier injection), a one-wire-to- 20
`three-wire converter circuit, and a small amount of
`serial-access memory.
`The integrated circuit, in the preferred embodiment,
`contains 256 bits of serial-access memory. This memory
`is read- or write-accessed as a single block transfer. It is 25
`contemplated that larger amounts of memory may be
`advantageous. Of course, other types of memory orga-
`nization can be used instead; but for many applications
`it is contemplated that use of a very small amount of
`memory (4K or less) may be particularly advantageous, 30
`since this extends the battery lifetime.
`Low-Voltage SRAM Architecture
`Among the innovative teachings set forth in the pres-
`ent application is a low-power low-voltage CMOS six-
`transistor static random access memory (SRAM), 35
`which can operate on a power supply voltage which is
`less than the sum of the NMOS and PMOS threshold
`voltages, and which does not include any analog or
`metastable sense amplifier stages. The selected cell is
`allowed to pull one of its bitline pair all the way down 40
`to ground. Thus, full logic levels appear on the bitline
`pair. Only one line of the bitline pair is connected to the
`following gate stage. Preferably bitline precharge tran-
`sistors are connected to pull up all bitline pairs when-
`ever the RAM is not selected. (cid:9)
`RAM/ROM Hybrid Memory
`A further innovative teaching, in the preferred em-
`bodiment, is the use of RAM/ROM hybrid for a portion
`of the memory array. An innovative memory cell is
`used, which can operate as a static RAM, or which can 50
`be programmed to operate as a read only memory
`(ROM) cell. Thus users who need the extra security
`permitted by ROM encoding can have this capability,
`while users who do not need ROM encoding can use
`off-the-shelf parts as RAM only. (cid:9)
`Chip Series with Unique Hard-wired Identifications
`A further innovative large-scale system concept is to
`use the capability to introduce ROM into the memory
`space to provide memory chips with completely unique
`hard-wired identifications. This provides tremendous 60
`advantages for security-related needs.
`In this embodiment, an external system can test the
`chip's integrity, by performing a read-write-read opera-
`tion on the memory space which is supposed to be
`ROM, and also on a portion of the memory space which 65
`is expected to be RAM. This will provide at least some
`insurance against the ROM identification being emu-
`lated in RAM. Optionally, the external system can even
`
`55
`
`4
`test the data output timing, to ascertain whether the
`RAM and ROM outputs are timed identically (and
`therefore to assure that the address inputs are not being
`decoded to address two different chips).
`This also provides advantages of failure protection.
`Very few catastrophes will be able to eradicate the
`hardware encoding of the cells which have been con-
`verted to ROM. (Even if the electrical functionality is
`totally destroyed, the fuse pattern can be read opti-
`cally.) Thus, recovery of these bits may provide useful
`information in failure analysis. (For example, a manu-
`facturing lot number can be cross-referenced from a
`unique identification number in ROM. This would pro-
`vide greatly enhanced capabilities for analysis of late
`failures.
`For another example, where the nonvolatility is elec-
`trically programmable, a system which recognized an
`imminent catastrophic failure (e.g. an avionics system
`facing a crash) might be able to save some data in the
`memory at the last minute.
`Innovative ESD Protection Diode
`The presently preferred embodiment uses an innova-
`tive protection diode structure, in which a significant
`device-level feature, is the provision of an intermediate-
`depth diffusion. This intermediate-depth diffusion will
`have a junction depth (inside the P-well or N-well)
`which is significantly deeper than the source/drain
`junction depth, but significantly shallower than the
`depth of the well. This intermediate-depth diffusion is
`useful in the innovative diode structure described, but
`can also be used for other device structures. For exam-
`ple, this structure provides a compact bipolar transistor
`structure with reasonably high gain. This intermediate-
`depth diffusion can also be used for input protection
`structures (i.e. to provide device structures which will
`rapidly and recoverably break down, when a high-volt-
`age pulse appears, to discharge the high-voltage pulse
`without damaging the primary circuitry of the chip).
`For another example, this intermediate-depth diffusion
`can also be used to form diffused capacitors with rela-
`tively large capacitance per unit area, or capacitors
`whose capacitance varies greatly with voltage (such
`capacitors are commonly referred to as varactors.)
`A further advantage of this structure, and a further
`innovative teaching set forth herein, is that the innova-
`tive structure can be fabricated with minimal added
`process complexity. An intermediate-depth diffusion is
`added to a standard process flow; but the shallow diffu-
`sions in the battery protection structure simply make
`use of the source/drain implants, and the deepest diffu-
`sion simply uses the N-well (or P-well) fabrication steps.
`For process simplicity, the intermediate-depth diffu-
`sion is most preferably formed by using an implant
`which is identical (in dose and energy) to another im-
`plant used in the same process. The additional junction
`depth is achieved by exposing the earlier implant to a
`high-temperature step before the later implant is per-
`formed, so that the earlier implant will have a corre-
`spondingly greater diffusion length (integral (D00.5).
`A variety of "substrate" structures are commonly
`used for integrated circuits, and far more have been
`proposed or have seen limited use. For example, the
`"substrate" which surrounds the N-wells and P-wells is
`often an epitaxial layer atop a much more heavily doped
`underlying layer. For another example, the N-wells and
`P-wells are commonly formed by separate implantation
`(and drive-in) steps, and such processes are referred to
`as "twin tub" processes; but alternatively one of these
`
`AMEX 1008 - Page 20 of 41
`
`

`

`10
`
`5
`steps may be omitted, so that, for example, the PMOS
`devices might be formed directly in an N-type upper
`substrate portion. Other important structure types in-
`clude silicon-on-insulator structures and full dielectric
`isolation structures, where there is no electrically con- 5
`tinuous body linking all of the wells. It is important to
`note that the innovative teachings set forth herein can
`advantageously be adapted to a tremendous variety of
`substrate structures, including not only the embodi-
`ments listed or mentioned, but also many others. (cid:9)
`It should be noted that the disclosed families of de-
`vices structures can also be used for a variety of other
`purposes. In particular, the disclosed structure provides
`a diode structure which may be adapted for use in other
`types of device structures, in very-low-power inte- 15
`grated circuit applications.
`It should also be noted that some prior art CMOS
`structures have used guard ring structures to suppress
`latchup. The problem of latchup (suppressing the para-
`sitic thyristor) is a quite different problem from the 20
`leakage problems discussed above, but in both cases
`collection of minority carriers is desirable. Guard ring
`structures are commonly used to surround locations
`(such as output drivers) where transient signals are most
`likely to cause injection of minority carriers. (A suffi- 25
`cient injection of minority carriers could fire the para-
`sitic thyristor, and thus lead to latchup.)
`In the preferred class of embodiments, the innovative
`diffusion structure described is used to conserve the
`charge in the battery. One drain on the battery is caused 30
`by negative excursions on an incoming data line (for
`example, when a negative voltage spike occurs due to
`an electrostatic discharge (ESD) event). In a normal
`battery-powered integrated circuit, the current drawn
`during such a negative voltage surge would be drawn 35
`both from the ground connection and also from the
`power supply connection. However, in stringently
`power-limited applications, even this amount of cur-
`rent, over the lifetime of the part, can use enough of the
`battery capacity to shorten the part's lifetime substan- 40
`tially.
`That is, when a negative transient occurs, a large
`number of electrons will be injected. If these electrons
`are allowed to diffuse freely many of them will diffuse
`toward the high-potential regions which are connected 45
`to the battery. This charge transfer reduces the total
`charge available during the lifetime of the battery.
`The shielded diode structure of FIG. 16K is pro-
`tected: almost all electrons injected at first junction 111
`will be collected at second junction 112. By contrast, a 50
`simple field effect transistor (FET) output driver, like
`transistor 150 in FIG. 16M, is not isolated: when the
`drain junction of such an NMOS FET is forward bi-
`ased, electrons will be released into substrate 140, and
`many of these electrons can then diffuse to regions of 55
`high potential.
`Therefore, a further innovative teaching is to use the
`innovative diffusion structure to source current to nega-
`tive transients which may occur on the I/O lines of a
`chip. In this embodiment, an I/O line is connected so 60
`that the first junction (in a structure as described above)
`will be forward biased when the I/O line goes negative,
`and the other side of the first junction is connected to
`ground potential. Thus, when a negative-going tran-
`sient occurs, current will be sourced, through the first 65
`junction, from ground.
`When a negative-going transient occurs, some cur-
`rent will also be sourced, at the output transistor which
`
`5,210,846
`
`6
`drives the I/O line, and some of this current component
`will cause minority carrier diffusion; but the use of this
`innovative teaching helps to reduce the amount of cur-
`rent sourced which can cause minority carrier diffusion.
`Preferably the area of the first junction is substantially
`larger than that of the junction area of the source/drain
`diffusion, in the output transistor, which is connected to
`the power supply.
`This innovative teaching also has two further advan-
`tages. First, the reduced risk of minority carrier injec-
`tion means that the risk of stored data states being upset
`by transient signals is reduced. Second, the risk of
`latchup is reduced.
`Thus, this innovative teaching advantageously pro-
`vides a battery-powered integrated circuit which is
`protected against battery depletion by electrical noise
`appearing at input/output connections. This innovative
`teaching may be particularly advantageous in inte-
`grated circuits which are intended for use in systems
`where high levels of noise must be tolerated.
`Innovative Bus Organization
`To communicate with this memory, in the preferred
`embodiment, an innovative one-wire bus protocol is
`used. This protocol is well adapted for interface to the
`low-cost architecture of the module of the presently
`preferred embodiment.
`Time-Domain Relations
`A bidirectional one-wire bus requires some use of
`time-domain or frequency-domain relations, to track the
`two half-channels of communication.
`It is quite possible to put an accurate time base in a
`low-power integrated circuit, using CMOS oscillators
`stabilized with quartz crystals; but the use of such tech-
`niques adds to the cost of the part. A crude time base
`can be provided simply by using an oscillator which is
`not stabilized. However, the response time of a simple
`timing circuit will be dependent on processing parame-
`ters. In conventional integrated circuit processing, there
`will normally be significant variation in parameters such
`as layer thickness, line-to-space ratio, and net dopant
`concentration in various locations. Thus, the electrical
`parameters, such as the series resistance of a polysilicon
`resistor of a given nominal dimension, can easily vary
`by ±20% or more, even in a well-controlled pror-Pcs
`This means that the net speed of a timing circuit can
`vary by even more, since the net speed will be depen-
`dent on several electrical parameters, which may vary
`together or in opposition.
`Parameter variation can be compensated for, by test-
`ing a newly fabricated wafer and programming ele-
`ments on-chip (such as trimming capacitors) to adjust
`the net delay of timing elements; but this additional
`manufacturing step adds significant expense.
`Low-Voltage CMOS Logic
`Moreover, in a low-voltage CMOS system (i.e. where
`the supply voltage is less than the sum of the PMOS and
`NMOS threshold voltages), achieving even a crude
`time base is much more difficult. This is due to the
`transfer characteristics of a logic gate in this technol-
`ogy.
`FIG. SA shows the voltage transfer characteristics
`( V our graphed as a function of VW for an inverter in
`conventional CMOS technology (e.g. where the supply
`voltage VDD is about 5 Volts, and the PMOS threshold
`voltage Vrpand the NMOS threshold voltage VrArboth
`have magnitudes in the range of about 0.8 V to 1.1 V.)
`Suppose that the input voltage VIN was initially at
`ground voltage Vss (0 V), so that the inverter's NMOS
`
`AMEX 1008 - Page 21 of 41
`
`

`

`7
`transistor is off and the inverter's PMOS transistor is on.
`Now, as VIN starts to rise, V our will stay at V DD until
`VIN rises to VTN. At this point the NMOS device will
`start to pass current. However, the NMOS device will
`not be able to overpower the PMOS device until the 5
`voltage reaches a trip point V nip. The trip point volt-
`age V TRIpis well-defined for each particular logic gate,
`but is dependent on the device dimensions. (If the width
`of the PMOS device is increased, or the length of the
`PMOS device decreased, or the width of the NMOS 10
`device is decreased, or the length of the NMOS device
`increased, then the NMOS device will have more diffi-
`culty in overpowering the PMOS device, and the trip
`point VTRipwill occur at a higher voltage.) As the input
`voltage ViNincreases, the NMOS device will pass more 15
`current and the PMOS device will pass less current,
`until at voltage VDD-V Tp the PMOS transistor turns
`off.
`By contrast, the transfer characteristic of a low-volt-
`age CMOS inverter, as shown in FIG. 5B, are quite 20
`different. (Suppose, for example, that V DD= 1.5 V, and
`Vyr= V TN=0.9 V. Thus, note that FIGS. SA and 5B
`are not drawn to the same scale.) H