A HIGH SPEED TELECOMMUNICATIONS INTERFACE
`FOR DIGITAL AUDIO TRANSMISSION AND RECEPTION
`
`214 3
`
`(D - 2)
`
`Hyun Heinz Sohn
`CompuSonics Corporation
`Cambridge , Massachusetts
`
`Presented at
`the 76th Convention
`1984 October 8-11
`New York
`
`This preprint has been reproduced from the author's advance
`mant!SCript, without editirlg, corrections or consideration by
`the Review Board. The AES takes no responsibility for the
`contems.
`
`Additional preprints may be obtained by sending request
`and remittance to the Audio Engineering Society, 60 East
`42nd Street, New York, New York 10165 USA.
`
`All rights reserved. Reproduction of this preprint, or any
`portion thereof, is not permitted without direct permission
`from the Journal of the Audio Engineering Society.
`
`AN AUDIO ENGINEERING SOCIETY PREPRINT
`
`Page 00001
`
`

`
`A HIGH SPEED TELECOMMUNICATIONS INTERFACE FOR
`DIGITAL AUDIO TRANSMTSSION AND RECEPTION
`
`by
`
`Hyun Heinz Sohn
`Shugart Corporation
`475 Oakmead Parkway, MS 4-l
`Sunnyvale , CA 94086
`(415 ) 969 - 7743
`
`for
`
`CompuSonics Corporation
`l Arnold Circle
`Cambridge, MA 02139
`(617 ) 354- 0050
`
`ABSTRACT
`
`transmission and
`speed digital interface for the
`A high
`reception of digital audio signals over AT&T's Accunet was
`designed
`and
`i mp l emented
`to operate
`in
`a MultiRus
`based
`microcomputer;
`This interface will transmit and receive digital
`data at 56,000 bits per second. Such a capability will allow the
`distribution of
`recordings
`in digital
`format
`from
`central
`databases which can be accessed by conventional telephone over
`the Accunet.
`
`refining,
`Much of the .audio industry is devoted to using.
`and developing new Methods of storing,
`retrieving, transmitting,
`and receiving sound information. A great deal of effort has been
`directed at
`reducing as much as possible
`the
`introduction of
`noise and distortion to the audio signal path. Until recently,
`ell stages of signal processing have been analog.
`These systems
`have undergone continuous improvements that reduce the noise and
`distortion in small but usually measurable increments.
`
`in
`resulted
`introduction of digital systems has
`The
`significant
`performance
`i•provements
`in
`terms of
`frequency
`response, background noise, · and distortion. There are "still some
`skeptics who claim that "breaking up of the sound"
`into finite
`numbers result in losses of the original audio signal, leading to
`"impure'' sound, causing listener fatigue and stress, among ot&er
`is not the intention of
`pychoacoustical aberrations.
`It
`the
`to defend digital audio technology.
`author
`It is sufficient to
`t hat with the proper application of mathematics
`and signal
`say
`processing theory, the process of digitizing and recovering audio
`signals is nondestructive and clean.
`
`1
`
`Page 00002
`
`

`
`Conventional analog signals require careful modulation and
`demodulation in any storage or transmission process ,
`In fact, by
`definition,
`analog
`techniques hinge on modulating some physical
`property of a medium to carry or store the desired signal.
`The
`vinyl
`'record has modulated grooves;
`radio
`transmission
`is
`modulated electromagnetic radiation. The fact that the signal is
`intimately related to the medium makes it dependent wholly on the
`purity
`and quality of
`that medium.
`The
`introduction of
`"audiophile quality virgin vinylh recordings is ample evidence of
`this dependence.
`
`to signal
`A digital system encourages a modular approach
`processing.
`Cascading of
`functional modules
`in
`the digital
`domain
`is equivalent
`to routing patch cords
`through various
`mixers,
`recorders,
`and equalizers.
`Once sound (or any analog
`signal) has been digitized into a series of bits (contraction for
`Binary digiT), it can not be distinguished from ordinary computer
`data.
`At this point, the strength of digital processing becomes
`apparent: the signal has been separated from the medium. Since a
`representation of the signal in the form of a sequence of numbers
`is manipulated,
`as long as the numbers are not corrupted,
`the
`original signal can be recovered. This means that the signal can
`be processed
`in any convenient manner without
`fear of adding
`noi~e.
`
`is because of this property of digital signals that high
`It
`quality audio signals can be transmitted over
`such bandwidth
`limited medium as a phone line.
`The AT&T Accune• high speed
`digital
`link is intended for communications between computers at
`a
`rate of 56,000 BPS (bits per second).
`This service uses
`conventional phone lines with special interface equipment. Since
`high quality ADCs (analog to digital converters) exist,
`the
`missing
`link
`is an interface to the phone line that will allow
`the
`"pumping" of the sound data to a suitable interface at
`the
`other end of the line.
`
`such
`which
`audio
`
`of
`This paper will describe the design and implementation
`a
`link,
`the Digital Audio Transceiver
`Interface
`(DATI),
`enables two Intel MultiBus based microcomputers to exchange
`signals over the Accunet.
`
`2
`
`Page 00003
`
`

`
`DESIGN PHILOSOPHY AND OVERVIEW
`
`unrelated
`previously
`two
`bridges
`project
`this
`As
`technologies, many issues were encountered in the initial product
`definition.
`It was felt that in order to be effective as a first
`generation design,
`it had
`to be a modular, generic design.
`Transmitting digital audio with computers over phone
`lines had
`not been performed before (to the knowledge of the author),
`so
`the design had
`to be flexible to
`in order
`to accommodate
`unforeseen situations.
`
`In keeping with the modular approach consistent in digital
`systems,
`the Digital Audio Transceiver
`Interface
`( DATI ) was
`designed as
`a computer peripheral with only digital circuits .
`Such an approach may be co unter -intuitive, but computers are much
`more sensitive to data errors than human ears, so this results in
`a system more than adequate to handle audio data.
`The DATI only
`handles digital -data,
`thus may be effectively used to
`transmit
`and receive computer data as well.
`
`The design goals included: 1) simplest possible interface to
`hos~ computer and
`its software environment,
`2)
`use
`the
`conventional ,
`readily
`available components,
`and 3)
`short
`development cycle. Once a market and host product is targeted, a
`simplified,
`low cost version can be implemented in custom chip
`sets.
`To
`keep
`the development
`time
`to
`a
`minimum,
`no
`microprocessor was used.
`This had two effects:
`1) there was no
`lengthy software development,
`and 2) significantly
`increased
`bandwidth as a result of using a microsequencer, or microcoded
`control module.
`A microsequencer is,
`in short, a very stripped
`down microprocessor that can only perform a few
`tasks, but at
`very high speeds because of its simplicity.
`Even a high speed
`microprocessor
`implementation of
`the DATI would be able
`to
`operate at only 30% speed of the curren t design.
`Of course, the
`current capacity is not fully utilized through the Accunet,
`so
`absolute
`speed is not as great a concern as the development
`and
`debugging cyc le.
`
`The entire DATI is built using industry standard transistor(cid:173)
`transistor
`logic
`(TTL) and complementary metal oxide silicon
`(CMOS) devices. Functionally, the interface is a 16 bit to 8 bit
`converting
`transceiver buffer.
`The 16 bit level is at the host
`computer level, where the data bus can handle 16 bits at a
`time
`most efficiently.
`'f he
`8 bit level is the connectio n to other
`equipment, such as other DATis and AT&T Accunet terminals.
`
`l.
`The configuratio n diagram of a system is shown in Fig.
`The analog signal can be from any source; it does not matter once
`it has been digitized.
`
`3
`
`Page 00004
`
`

`
`ANALOG SIGNAL SOURCE
`
`ANALOG TO DIGITAL
`CONVERTER
`
`HOST COMPUTER
`
`DIGITAL AUDIO
`TRANSCEIVER
`INTERFACE
`
`~ ACCUNET THRMINAL
`!
`l
`
`PHONE SERVICE
`
`ACCUNET TERMINAL
`
`DIGITAL AUDIO----------~ HOST COMPUTER
`TRANSCEIVER
`I N'l'ERFACE
`
`DIGITAL TO ANALOG-------~ RECOVERED ANALOG
`CONVERTER
`SIGNAL
`
`Fig. 1. System configuration diagram.
`
`The functional modules of the DATI are:
`
`- Intel MultiBus Interface
`- Buffer Memory Module
`- Command and Status Registers
`- Transceiver Protocol Module
`- Microcoded Control Module
`
`The functi~nal block diagram of the DATI is shown in Fig. 2.
`
`4
`
`Page 00005
`
`

`
`TRANCRIVBR
`PROTOCOL
`MODULR
`
`If
`
`MICROCODBD
`CONTROL
`MODULE
`
`~
`
`r--- 1
`
`BUFFRR
`MBMORY
`MODULI\
`
`...
`
`COMMAND
`REGISTER
`
`1+-
`
`STATUS
`REGISTER
`
`t
`
`1
`
`MULTI BUS
`INTERFACE
`
`Fig. 2.
`
`Block diagram of the Digital Audio Tranceiver
`Interface.
`
`The DATI is interfaced to the host computer's MultiBua
`to
`All
`it appear
`like an ordinary memory peripheral.
`make
`the DATI are
`communications between
`the host computer and
`channeled through this module.
`
`to
`information received over the phone line or waiting
`All
`be transmitted are held in the Buffer Memory Module until it can
`There are four banks of 8 kB ( kilobytes or 1024
`be aervice,
`bytes )
`each.
`Two banks are reserved
`for
`receive data,
`the
`remaining
`two are for the transmit data.
`At any given time,
`a
`buffer can be allocated for only one function.
`There are
`four
`basic functions or services:
`
`5
`
`Page 00006
`
`

`
`1) HOST DATA READ:
`the computer reads the data out of Lhe
`memory bank currently allocated for this
`function
`to be
`processed.
`
`2) HOST DATA WRITE:
`the computer writes the d~la out to
`the
`memory bank currently allocated for this
`funct i on
`to be
`transmitted.
`
`3) DATA RECF.IVR:
`this is the bank allocated to receive all the
`data:
`it is not acces~ible by the host when a bank has been
`allocated for this function.
`
`SEND :
`4) DATA
`transmitted
`this bank holds all the data to be
`the the computer had loaded it;
`it is not accessible
`after
`by
`the host when
`a bank has been allocated
`for
`this
`functi.on.
`
`four possible
`four buffer and a maximum of
`there are
`Since
`to be performed concurrently, . the DATI
`is capable
`services
`sending and receiving data aL full bandwidth simultaneously. The
`btiffer allocations scheme ~s shown in Fig. 3.
`
`TRANSCHIVER
`PROTOCOL
`MODUI.IO:
`
`t
`
`DATA RECEIVE
`BUFFER
`
`c
`
`HOST DATA
`RRAD BU~'FER
`
`HOST COMPUTER
`
`i
`
`DATA SEND
`BUFFER
`
`HOST DATA
`WRITE BUFFER
`
`J
`
`)
`
`Fig. 3.
`
`Buffer memory allocation scheme.
`
`6
`
`.
`
`Page 00007
`
`

`
`the
`DATI,
`the
`initiate operations on
`to
`order
`In
`microsequencer or Microcoded Control Module needs to be given the
`proper instructions. This is accomplished by loading the desired
`operation code
`into
`the appropriate
`command
`register.
`The
`operations that can be initiated by the host are:
`
`The number of bytes of data to be sent
`1) SEND BYTE COUNT:
`loaded into Send Counter Command Register.
`
`is
`
`the
`into
`loaded
`is
`This operation code
`2) SEND BUFFER:
`Operation Command Register. When executed,
`the two banks
`that were allocated for the functions HOST DATA WRITE
`and
`DATA
`SEND are switched .
`This will allocate a new memory
`bank
`into which new data to be transmitted can be
`loaded.
`The bank that was previously for HOST DATA WRITE is now for
`DATA SEND.
`This mode of operation makes
`the
`transmit
`procedure totally transparent to the host computer.
`
`the
`This operation code is also loaded into
`3} READ BUFFER:
`Operation Command Register. When executed,
`the two banks
`that were allocated for the functions HOST DATA READ
`and
`DATA RECEIVE are switched. This makes available to the host
`the data
`that has been received while the other bank was
`being read.
`
`two status register that indicates
`There are
`state of the DATI:
`
`the current
`
`reading this register will
`1) RECEIVED DATA COUNT REGISTER:
`show how many bytes have been received into the current DATA
`RECEIVE memory bank.
`If it is zero. it indicates that there
`are
`is no new received data.
`The host would issue a
`READ
`BUFFER operation code upon finding a non-zero number in this
`register.
`
`reading this register will show
`2} SEND DATA COUNT REGISTER:
`the DATA
`SEND bank
`to
`be
`in
`how many bytes
`remain
`transmitted.
`The host would issue a SEND BUFFER operation
`code only when this register holds zero to avoid losing data
`that would not get transmitted.
`
`command and status register appear simply as memory
`These
`to the host computer;
`the process of sending commands
`locations
`to
`the DATI is no more that writing the codes
`to memory.
`The
`microsequencer
`reads
`the
`command
`registers.
`performs
`the
`necessary sequence of operations.
`and then loads the appropriate
`status register .
`
`This operational simplicity of the interface allows flexible
`adaptations
`to be made
`to a great variety of hardware
`and
`software configurations.
`
`7
`
`Page 00008
`
`

`
`the actual interface the user will see
`is
`This module
`connected to other OATis or an Accunet terminal,
`lt consists of
`two unidirectional 8 bit parallel data lines with handshake and
`strobe lines (Fig. 2). This is a very simple configuration that
`allows easy testing and connections with other devices.
`
`MigrQ£QQ~g QQn~rQl MQg~!~
`
`the
`This module supplies
`is the heart of the DATI.
`This
`It
`»intelligence» required to make the interface so easy to use.
`must check for all the conditions thut can exist in terms of read
`and write
`request from the host aa well as da·ta coming
`in and
`data waiting to be transmitted.
`It must take correct action when
`an operation code is loaded into a command register. After
`the
`operation has been executed,
`the command register is cleared and
`the status
`register
`loaded
`so
`the host may
`know
`that all
`operations have been completed, successful or otherwise.
`It also
`keeps
`track of which memory bank has been allocated
`to which
`function so that data cannot be accidentally lost or overwritten.
`
`the host must service it
`a buffer has been filled up,
`When
`before more data comes in to overwrite the previous date.
`ln the
`event that the host is occupied with another task such that it is
`not able to check the RECEIVED DATA COUNT REGISTER,
`the Control
`Module
`initiates a bus interrupt. A bus
`interrupt physically
`asserts one of
`the bus
`interrupt
`lines,
`reserved
`for
`this
`purpose,
`to notify the host processor that an immediate service
`request is being made.
`This "interrupts" whatever the computer
`was doing before eo that the data can be handled before
`loss
`occurs.
`This, by definition, makes the DATI an interrupt driven
`device.
`
`This module
`been "hard-wired",
`one program.
`
`that has
`amounts to a very efficient program
`or a small computer dedicated to running this
`
`8
`
`Page 00009
`
`

`
`IMPLEMENTATION OVERVIEW
`
`logic,
`The address decoders and data buffers us e standard
`i.e. devices such as 74LS374, 74LS240, 74LS273, and an assortment
`of discrete gates. While MultiBus uses inverted logic, that is a
`»low" or 0 volt le~els indicate the asserted "1" state,
`the DATI
`uses positive logic, where the asserted "1" state is defined
`to
`be "high" or 5 volts.
`To keep the logic consistent, all signal
`lines that are •onitored by the DATI are first inverted.
`
`~yff~r M~~Qr~ MQ~Y!~
`
`The RAM (Random Access Memory) devices used are Hitachi 6 167
`CMOS static RAMs with a cycle time of 70 nanoseconds.
`The high
`speed of this RAM enables the DATI to always stay ahead of
`the
`host computer.
`Sixteen of theae 16 kilobit x 1 bit wide devices
`result
`in. a · total buffer me•ory space of 16 ki lowords or 32
`kilobytes.
`
`the RECEIVED and SEND DATA COUNT REGISTERS ere 12 bits
`Both
`wide.
`Four cascaded 74LS161 4 bit synchronous counters are used
`for each register.
`The command registers ere implemented us i ng
`74LS273 8 bit register devices .
`
`The main function of this module is performed by a pair of
`74LS167 data multiplexors . After a 16 bit data word is
`loaded
`into a ho ldi ng register in this module, the mu ltiplexor sends the
`lower 8 bits,
`followed by the upper 8 bits.
`The status of the
`•odule
`( hence the presence of in c oming data) is indicated by t he
`output
`of a
`74LS74
`flip-flop
`( which
`is checked
`by
`t he
`microsequencer).
`
`This module is implemented in a very straight forward manner
`using
`two 4 bit counters as the current state register
`( or
`"program counter"). All
`the states are decoded into discrete
`signals
`through a pair of 74154 4 - to- 16 demultiplexor devices.
`These demultiplexed outputs are used to assert
`the
`required
`control signals as well as generate the next state.
`
`Page 00010
`
`

`
`Transceiver
`The first generation design of the Digital Audio
`of
`using
`Interface
`has
`demonstrated
`the
`viability
`data.
`The
`telecommunications
`for purposes other than computer
`although no
`laboratory prototypes have been successfully tested,
`performed.
`actual
`transmissions over AT&T's Accunet have been
`currently
`More durable versions suitable for field testing are
`have been
`under construction;
`full scale tests will probably
`October,
`performed by
`the time of the 76th AES Convention
`in
`1984.
`
`in
`One of the considerations for not using a microprocessor
`the
`the design, other
`than absolute speed, was maintaining
`feasibility of using VLSI (Very Large Scale Integration) devices
`to compress all
`the functional modules down to at most
`a
`few
`integrated circuits or "chips". Microprocessors, already being
`VLSI or LSI ( Large Scale Integration}, would be difficult
`to
`incorporate.
`
`The author and his colleagues at CompuSonics Corporation see
`great potential
`for expanding the music market through digita l
`technology .
`Imagine
`that a large database of the latest music
`chart successes exist only a
`phone call away. Video music
`services which broadcast over cable networks can
`simultaneously
`release new
`album and have it ready for immediate sale without
`first having filled the distribution pipeline.
`In fact , a trend
`of selling the music, not the media would have been set.
`This
`would
`reduce expensive inventory and shipping costs and at
`the
`same
`time assure a supply of recording that can meet any demand.
`Record stores can have direct connections to the music databases
`and become,
`in a sense, the record manufacturer, paying royalties
`to the recording company for each copy sold. Since each copy of a
`recording can be accounted for by the computers that
`run
`the
`databases, the piracy problem may also be reduced.
`
`For
`These are exciting times for the electronics industry.
`in
`the first time,
`the audio industry can benefit from advances
`computer
`technology as well as new developments in
`traditional
`areas.
`
`the
`All material used for the design and implementation of
`Digital Audio Transceiver Interface was drawn from the author's
`personal and class notes taken from courses in Digital Design
`(6.032 and 6.111,
`for those who are familiar with the Department
`of
`EECS) while attending
`the Massachusetts
`Institute
`of
`Technology.
`
`10
`
`Page 00011