D Powerful 16-Bit TMS320C5x CPU
`D 20-, 25-, 35-, and 50-ns Single-Cycle
`Instruction Execution Time for 5-V
`Operation
`D 25-, 40-, and 50-ns Single-Cycle Instruction
`Execution Time for 3-V Operation
`D Single-Cycle 16 × 16-Bit Multiply/Add
`D 224K × 16-Bit Maximum Addressable
`External Memory Space (64K Program, 64K
`Data, 64K I/O, and 32K Global)
`D 2K, 4K, 8K, 16K, 32K × 16-Bit Single-Access
`On-Chip Program ROM
`D 1K, 3K, 6K, 9K × 16-Bit Single-Access
`On-Chip Program/Data RAM (SARAM)
`D 1K Dual-Access On-Chip Program/Data
`RAM (DARAM)
`D Full-Duplex Synchronous Serial Port for
`Coder/Decoder Interface
`D Time-Division-Multiplexed (TDM) Serial Port
`D Hardware or Software Wait-State
`Generation Capability
`D On-Chip Timer for Control Operations
`D Repeat Instructions for Efficient Use of
`Program Space
`D Buffered Serial Port
`D Host Port Interface
`
`TMS320C5x, TMS320LC5x
`DIGITAL SIGNAL PROCESSORS
`
`
`SPRS030A – APRIL 1995 – REVISED APRIL 1996
`
`D Multiple Phase-Locked Loop (PLL)
`Clocking Options (×1, ×2, ×3, ×4, ×5, ×9
`Depending on Device)
`D Block Moves for Data/Program
`Management
`D On-Chip Scan-Based Emulation Logic
`D Boundary Scan
`D Five Packaging Options
`– 100-Pin Quad Flat Package (PJ Suffix)
`– 100-Pin Thin Quad Flat Package
`(PZ Suffix)
`– 128-Pin Thin Quad Flat Package
`(PBK Suffix)
`– 132-Pin Quad Flat Package (PQ Suffix)
`– 144-Pin Thin Quad Flat Package
`(PGE Suffix)
`D Low Power Dissipation and Power-Down
`Modes:
`– 47 mA (2.35 mA/MIP) at 5 V, 40-MHz
`Clock (Average)
`– 23 mA (1.15 mA/MIP) at 3 V, 40-MHz
`Clock (Average)
`– 10 mA at 5 V, 40-MHz Clock (IDLE1 Mode)
`– 3 mA at 5 V, 40-MHz Clock (IDLE2 Mode)
`– 5 m A at 5 V, Clocks Off (IDLE2 Mode)
`D High-Performance Static CMOS Technology
`D IEEE Standard 1149.1† Test-Access Port
`(JTAG)
`
`description
`The TMS320C5x generation of the Texas Instruments (TI) TMS320 digital signal processors (DSPs) is
`fabricated with static CMOS integrated circuit technology; the architectural design is based upon that of an
`earlier TI DSP, the TMS320C25. The combination of advanced Harvard architecture, on-chip peripherals,
`on-chip memory, and a highly specialized instruction set is the basis of the operational flexibility and speed of
`the ’C5x‡ devices. They execute up to 50 million instructions per second (MIPS).
`The ’C5x devices offer these advantages:
`
`D Enhanced TMS320 architectural design for increased performance and versatility
`D Modular architectural design for fast development of spin-off devices
`D Advanced integrated-circuit processing technology for increased performance
`D Upward-compatible source code (source code for ’C1x and ’C2x DSPs is upward compatible with ’C5x DSPs.)
`D Enhanced TMS320 instruction set for faster algorithms and for optimized high-level language operation
`D New static-design techniques for minimizing power consumption and maximizing radiation tolerance
`
`Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
`Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
`
`TI is a trademark of Texas Instruments Incorporated.
`† IEEE Standard 1149.1–1990, IEEE Standard Test-Access Port and Boundary-Scan Architecture
`‡ References to ’C5x in this document include both TMS320C5x and TMS320LC5x devices unless specified otherwise.
`Copyright  1996, Texas Instruments Incorporated
`
`PRODUCTION DATA information is current as of publication date.
`Products conform to specifications per the terms of Texas Instruments
`standard warranty. Production processing does not necessarily include
`testing of all parameters.
`
`POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
`
`1
`
`

`
`TMS320C5x, TMS320LC5x
`DIGITAL SIGNAL PROCESSORS
`
`
`SPRS030A – APRIL 1995 – REVISED APRIL 1996
`
`description (continued)
`
`
`
`Table 1 provides a comparison of the devices in the ’C5x generation. It shows the capacity of on-chip RAM and
`ROM memories, number of serial and parallel I/O ports, execution time of one machine cycle, and type of
`package with total pin count.
`
`Table 1. Characteristics of the ’C5x Processors
`
`PACKAGE
`
`TYPETYPE
`QFP‡
`
`132 pin
`132 pin
`100/132 pin
`100/132 pin
`100 pin
`100 pin
`132 pin
`132 pin
`100 pin
`100 pin
`100 pin
`128 pin
`144 pin
`144 pin
`
`TMS320
`DEVICES
`
`ON-CHIP MEMORY (16-BIT WORDS)
`DARAM
`SARAM
`ROM
`DATA +
`DATA +
`PROG
`PROG
`
`PROG
`
`DATA
`
`
`
`I/O PORTSI/O PORTS
`
`SERIAL
`
`PARALLEL†
`
`POWERPOWER
`
`
`SUPPLYSUPPLY
`(V)
`
`CYCLECYCLE
`
`
`TIMETIME
`(ns)
`
`9K
`512
`544
`TMS320C50
`9K
`512
`544
`TMS320LC50
`1K
`512
`544
`TMS320C51
`1K
`512
`544
`TMS320LC51
`–
`512
`544
`TMS320C52
`–
`512
`544
`TMS320LC52
`3K
`512
`544
`TMS320C53
`3K
`512
`544
`TMS320LC53
`3K
`512
`544
`TMS320C53S
`3K
`512
`544
`TMS320LC53S
`6K
`512
`544
`TMS320LC56
`6K
`512
`544
`TMS320LC57
`6K
`512
`544
`TMS320C57S
`6K
`512
`544
`TMS320LC57S
`† Sixteen of the 64K parallel I/O ports are memory mapped.
`‡ QFP = Quad flatpack
`§ ROM boot loader available
`¶ TDM serial port not available
`# Includes auto-buffered serial port (BSP) but TDM serial port not available
`|| HPI = Host port interface
`
`2K§
`2K§
`8K§
`8K§
`4K§
`4K§
`16K§
`16K§
`16K§
`16K§
`32K
`32K
`2K§
`2K§
`
`2
`2
`2
`2
`1¶
`1¶
`2
`2
`2 ¶
`2 ¶
`2 #
`2 #
`2 #
`2 #
`
`Pinouts for each package are device-specific.
`
`64K
`64K
`64K
`64K
`64K
`64K
`64K
`64K
`64K
`64K
`64K
`64K + HPI ||
`64K + HPI ||
`64K + HPI ||
`
`5
`3.3
`5
`3.3
`5
`3.3
`5
`3.3
`5
`3.3
`3.3
`3.3
`5
`3.3
`
`50/35/25
`50/40/25
`50/35/25/20
`50/40/25
`50/35/25/20
`50/40/25
`50/35/25
`50/40/25
`50/35/25
`50/40/25
`35/25
`35/25
`50/35/25
`50/35
`
`2
`
`POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
`
`

`
`
`
`TMS320C5x, TMS320LC5x
`DIGITAL SIGNAL PROCESSORS
`
`
`SPRS030A – APRIL 1995 – REVISED APRIL 1996
`
`TMS320C50, TMS320LC50, TMS320C51, TMS320LC51, TMS320C53, TMS320LC53
`PQ PACKAGE
`( TOP VIEW )
`
`NC
`EMU0
`EMU1/OFF
`SSC V
`SSC V
`TOUT
`TCLKX
`CLKX
`TFSR/TADD
`TCLKR
`RS
`READY
`HOLD
`BIO
`DDC V
`DDC V
`IAQ
`TRST
`SSI V
`SSI V
`MP/MC
`D15
`D14
`D13
`D12
`D11
`D10
`D9
`D8
`DDD V
`DDD V
`NC
`NC
`
`17 16 15 14 13 12 11 10
`
`9
`
`8
`
`7
`
`6
`
`5
`
`4
`
`3
`
`2
`
`1 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117
`
`NC
`NC
`VSSD
`VSSD
`NC
`D7
`D6
`D5
`D4
`D3
`D2
`D1
`D0
`TMS
`VDDD
`VDDD
`TCK
`VSSD
`VSSD
`NC
`INT1
`INT2
`INT3
`INT4
`NMI
`DR
`TDR
`FSR
`CLKR
`VDDA
`VDDA
`NC
`NC
`
`18
`19
`20
`21
`22
`23
`24
`25
`26
`27
`28
`29
`30
`31
`32
`33
`34
`35
`36
`37
`38
`39
`40
`41
`42
`43
`44
`45
`46
`47
`48
`49
`50
`
`116
`115
`114
`113
`112
`111
`110
`109
`108
`107
`106
`105
`104
`103
`102
`101
`100
`99
`98
`97
`96
`95
`94
`93
`92
`91
`90
`89
`88
`87
`86
`85
`84
`
`NC
`NC
`VDDI
`VDDI
`IACK
`NC
`CLKOUT1
`XF
`HOLDA
`TDX
`DX
`TFSX / TFRM
`FSX
`CLKMD2
`VSSI
`VSSI
`TDO
`VDDC
`VDDC
`X1
`X2 / CLKIN
`CLKIN2
`BR
`STRB
`R/ W
`PS
`IS
`DS
`NC
`VSSC
`VSSC
`NC
`NC
`
` 79
`51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78
`
`80 81 82 83
`
`WE
`RD
`DDA
`DDA
`NC
`NC
`A15
`A14
`A13
`A12
`A11
`A10
`CLKMD1
`NC
`SSA V
`SSA V
`TDI
`DDI
`DDI
`A9
`A8
`A7
`A6
`A5
`A4
`A3
`A2
`A1
`A0
`SSA V
`SSA V
`NC
`NC
`
`V
`
`V
`
`V
`
`V
`
`NOTE: NC = No connect (These pins are reserved.)
`
`POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
`
`3
`
`

`
`TMS320C5x, TMS320LC5x
`DIGITAL SIGNAL PROCESSORS
`
`
`SPRS030A – APRIL 1995 – REVISED APRIL 1996
`
`
`
`Pin Functions for Devices in the PQ Package
`DESCRIPTION
`PARALLEL INTERFACE BUS
`16-bit external address bus (MSB: A15, LSB: A0)
`16-bit external data bus (MSB: D15, LSB: D0)
`Program, data, and I /O space select outputs, respectively
`Timing strobe for external cycles and external DMA
`Read / write select for external cycles and external DMA
`Read and write strobes, respectively, for external cycles
`External bus ready/ wait-state control input
`Bus request. Arbitrates global memory and external DMA
`SYSTEM INTERFACE / CONTROL SIGNALS
`Reset. Initializes device and sets PC to zero
`Microprocessor/microcomputer mode select. Enables internal ROM
`Puts parallel I/ F bus in high-impedance state after current cycle
`Hold acknowledge. Indicates external bus in hold state
`External flag output. Set /cleared through software
`I /O branch input. Implements conditional branches
`Timer output signal. Indicates output of internal timer
`Instruction acquisition signal
`Interrupt acknowledge signal
`External interrupt inputs
`Nonmaskable external interrupt
`SERIAL PORT INTERFACE (SPI)
`Serial receive-data input
`Serial transmit-data output. In high-impedance state when not transmitting
`Serial receive-data clock input
`Serial transmit-data clock. Internal or external source
`Serial receive-frame-synchronization input
`Serial transmit-frame-synchronization signal. Internal or external source
`TDM SERIAL-PORT INTERFACE
`TDM serial receive-data input
`TDM serial transmit-data output. In high-impedance state when not transmitting
`TDM serial receive-data clock input
`TDM serial transmit-data clock. Internal or external source
`TDM serial receive-frame-synchronization input. In the TDM mode, TFSR / TADD is used to output /
`input the address of the port.
`TDM serial transmit-frame-synchronization signal. Internal or external source. In the TDM mode,
`TFSX / TFRM becomes TFRM, the TDM frame synchronization.
`
`TYPE
`
`I / O / Z
`I / O / Z
`O / Z
`I / O / Z
`I / O / Z
`O / Z
`I
`I / O / Z
`
`I
`I
`I
`O / Z
`O / Z
`I
`O / Z
`O / Z
`O / Z
`I
`I
`
`I
`O / Z
`I
`I / O / Z
`I
`I / O / Z
`
`I
`O / Z
`I
`I / O / Z
`
`I / O / Z
`
`I
`
`SIGNAL
`
`A0 – A15
`D0 – D15
`PS, DS, IS
`STRB
`R / W
`RD, WE
`READY
`BR
`
`RS
`MP/ MC
`HOLD
`HOLDA
`XF
`BIO
`TOUT
`IAQ
`IACK
`INT1 – INT4
`NMI
`
`DR
`DX
`CLKR
`CLKX
`FSR
`FSX
`
`TDR
`TDX
`TCLKR
`TCLKX
`
`TFSR / TADD
`
`TFSX / TFRM
`
`LEGEND:
`I = Input
`O = Output
`Z = High impedance
`
`4
`
`POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
`
`

`
`
`
`TDI
`TDO
`TMS
`TCK
`TRST
`EMU0
`EMU1 / OFF
`
`X1
`X2 / CLKIN
`CLKIN2
`CLKMD1, CLKMD2
`CLKOUT1
`
`VDDA
`VDDD
`VDDC
`VDDI
`VSSA
`VSSD
`VSSC
`VSSI
`LEGEND:
`I = Input
`O = Output
`S = Supply
`Z = High impedance
`
`TMS320C5x, TMS320LC5x
`DIGITAL SIGNAL PROCESSORS
`
`
`SPRS030A – APRIL 1995 – REVISED APRIL 1996
`
`I
`O / Z
`I
`I
`I
`I / O / Z
`I / O / Z
`
`O
`I
`I
`I
`O / Z
`
`Pin Functions for Devices in the PQ Package (Continued)
`EMULATION/IEEE STANDARD 1149.1 TEST ACCESS PORT (TAP)
`TAP scan data input
`TAP scan data output
`TAP mode select input
`TAP clock input
`TAP reset (with pulldown resistor). Disables TAP when low
`Emulation control 0. Reserved for emulation use
`Emulation control 1. Puts outputs in high-impedance state when low
`CLOCK GENERATION AND CONTROL
`Oscillator output
`Clock/oscillator input
`Clock input
`Clock-mode select inputs
`Device system-clock output
`POWER SUPPLY CONNECTIONS
`Supply connection, address-bus output
`Supply connection, data-bus output
`Supply connection, control output
`Supply connection, internal logic
`Supply connection, address-bus output
`Supply connection, data-bus output
`Supply connection, control output
`Supply connection, internal logic
`
`S
`S
`S
`S
`S
`S
`S
`S
`
`POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
`
`5
`
`

`
`TMS320C5x, TMS320LC5x
`DIGITAL SIGNAL PROCESSORS
`
`
`SPRS030A – APRIL 1995 – REVISED APRIL 1996
`
`
`
`TMS320LC57
`PBK PACKAGE
`( TOP VIEW )
`
`SSC
`SSC
`
`V V
`
`HD2
`DS
`IS
`PS
`R/W
`STRB
`HD3
`BR
`CLKMD3
`X2/CLKIN
`X1
`VDDC
`TDO
`VSSI
`VSSI
`HD4
`CLKMD2
`HD5
`FSX
`HD6
`BFSX
`HD7
`DX
`BDX
`HOLDA
`XF
`CLKOUT1
`
`DDI
`DDI
`DDC
`
`V
`
`V
`
`V
`
`128
`
`127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97
`
`96
`95
`94
`93
`92
`91
`90
`89
`88
`87
`86
`85
`84
`83
`82
`81
`80
`79
`78
`77
`76
`75
`74
`73
`72
`71
`70
`69
`68
`67
`66
`65
`
`WE
`HD1
`RD
`HD0
`HRDY
`VDDA
`A15
`A14
`A13
`A12
`A11
`A10
`CLKMD1
`VSSA
`VSSA
`TDI
`HDS1
`HDS2
`VDDI
`VDDI
`A9
`A8
`A7
`A6
`A5
`A4
`A3
`A2
`A1
`A0
`VSSA
`HCS
`
`33
`
`34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
`
`1 2 3 4 5 6 7 8 9 1
`
`0
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`26
`27
`28
`29
`30
`31
`32
`
`HINT
`EMU0
`EMU1 / OFF
`VSSC
`VSSC
`TOUT
`BCLKX
`CLKX
`VDDC
`BFSR
`BCLKR
`RS
`READY
`HOLD
`BIO
`VDDC
`VDDC
`IAQ
`TRST
`VSSI
`VSSI
`MP / MC
`D15
`D14
`D13
`D12
`D11
`D10
`D9
`D8
`VDDD
`VDDD
`
`HAS
`DDA
`DDA
`CLKR
`FSR
`BDR
`DR
`NMI
`HBIL
`INT4
`INT3
`INT2
`INT1
`HR/W
`SSD
`SSD
`TCK
`DDD
`DDD
`HCNTL1
`TMS
`HCNTL0
`D0
`D1
`D2
`D3
`D4
`D5
`D6
`D7
`SSD
`SSD
`
`V V
`
`V V V V
`
`V V
`
`6
`
`POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
`
`

`
`
`
`SIGNAL
`
`A0 – A15
`D0 – D15
`PS, DS, IS
`STRB
`R / W
`RD, WE
`READY
`BR
`
`RS
`MP/ MC
`HOLD
`HOLDA
`XF
`BIO
`TOUT
`IAQ
`INT1 – INT4
`NMI
`
`DR
`DX
`CLKR
`CLKX
`FSR
`FSX
`
`HCNTL0
`HCNTL1
`HINT
`HDS1
`HDS2
`HR / W
`HAS
`HRDY
`HCS
`HBIL
`HD0 – HD7
`LEGEND:
`I = Input
`O = Output
`Z = High impedance
`
`TMS320C5x, TMS320LC5x
`DIGITAL SIGNAL PROCESSORS
`
`
`SPRS030A – APRIL 1995 – REVISED APRIL 1996
`
`I / O / Z
`I / O / Z
`O / Z
`I / O / Z
`I / O / Z
`O / Z
`I
`I / O / Z
`
`I
`I
`I
`O / Z
`O / Z
`I
`O / Z
`O / Z
`I
`I
`
`Pin Functions for the TMS320LC57 in the PBK Package
`TYPE
`DESCRIPTION
`PARALLEL INTERFACE BUS
`16-bit external address bus (MSB: A15, LSB: A0)
`16-bit external data bus (MSB: D15, LSB: D0)
`Program, data, and I /O space select outputs, respectively
`Timing strobe for external cycles and external DMA
`Read / write select for external cycles and external DMA
`Read and write strobes, respectively, for external cycles
`External bus ready/ wait-state control input
`Bus request. Arbitrates global memory and external DMA
`SYSTEM INTERFACE / CONTROL SIGNALS
`Reset. Initializes device and sets PC to zero
`Microprocessor/microcomputer mode select. Enables internal ROM
`Puts parallel I/ F bus in high-impedance state after current cycle
`Hold acknowledge. Indicates external bus in hold state
`External flag output. Set /cleared through software
`I /O branch input. Implements conditional branches
`Timer output signal. Indicates output of internal timer
`Instruction acquisition signal
`External interrupt inputs
`Nonmaskable external interrupt
`SERIAL PORT INTERFACE
`Serial receive-data input
`Serial transmit-data output. In high-impedance state when not transmitting
`Serial receive-data clock input
`Serial transmit-data clock. Internal or external source
`Serial receive-frame-synchronization input
`Serial transmit-frame-synchronization signal. Internal or external source
`HOST PORT INTERFACE (HPI)
`HPI mode control 1
`HPI mode control 2
`Host interrupt
`HPI data strobe 1
`HPI data strobe 2
`HPI read / write strobe
`HPI address strobe
`HPI ready signal
`HPI chip select
`HPI byte identification input
`HPI data bus
`
`I
`O / Z
`I
`I / O / Z
`I
`I / O / Z
`
`I
`I
`O / Z
`I
`I
`I
`I
`O / Z
`I
`I
`I / O / Z
`
`POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
`
`7
`
`

`
`TMS320C5x, TMS320LC5x
`DIGITAL SIGNAL PROCESSORS
`
`
`SPRS030A – APRIL 1995 – REVISED APRIL 1996
`
`
`
`Pin Functions for the TMS320LC57 in the PBK Package (Continued)
`TYPE
`DESCRIPTION
`BUFFERED SERIAL PORT
`BSP receive data input
`BSP transmit data output; in high-impedance state when not transmitting
`BSP receive-data clock input
`BSP transmit-data clock; internal or external source
`BSP receive frame-synchronization input
`BSP transmit frame-synchronization signal; internal or external source
`EMULATION/JTAG INTERFACE
`JTAG-test-port scan data input
`JTAG-test-port scan data output
`JTAG-test-port mode select input
`JTAG-port clock input
`JTAG-port reset (with pull-down resistor). Disables JTAG when low
`Emulation control 0. Reserved for emulation use
`Emulation control 1. Puts outputs in high-impedance state when low
`CLOCK GENERATION AND CONTROL
`Oscillator output
`Clock input
`
`I
`O / Z
`I
`I / O / Z
`I
`I / O / Z
`
`I
`O / Z
`I
`I
`I
`I / O / Z
`I / O / Z
`
`O
`I
`
`SIGNAL
`
`BDR
`BDX
`BCLKR
`BCLKX
`BFSR
`BFSX
`
`TDI
`TDO
`TMS
`TCK
`TRST
`EMU0
`EMU1 / OFF
`
`X1
`X2 / CLKIN
`CLKMD1, CLKMD2,
`CLKMD3
`CLKOUT1
`
`VDDA
`VDDD
`VDDC
`VDDI
`VSSA
`VSSD
`VSSC
`VSSI
`LEGEND:
`I = Input
`O = Output
`S = Supply
`Z = High impedance
`
`I
`
`O / Z
`
`S
`S
`S
`S
`S
`S
`S
`S
`
`Clock-mode select inputs
`
`Device system-clock output
`POWER SUPPLY CONNECTIONS
`Supply connection, address-bus output
`Supply connection, data-bus output
`Supply connection, control output
`Supply connection, internal logic
`Supply connection, address-bus output
`Supply connection, data-bus output
`Supply connection, control output
`Supply connection, internal logic
`
`8
`
`POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
`
`

`
`
`
`TMS320C5x, TMS320LC5x
`DIGITAL SIGNAL PROCESSORS
`
`
`SPRS030A – APRIL 1995 – REVISED APRIL 1996
`
`TMS320C51, TMS320LC51, TMS320C52, TMS320LC52, TMS320C53S, TMS320LC53S, TMS320LC56
`PZ PACKAGE
`( TOP VIEW )
`
`SSC V
`DS
`IS
`PS
`R/W
`STRB
`
`R
`† B
`
`X2/CLKIN
`X1
`
`DDC
`
`V
`
`TDO
`SSI
`SSI V
`CLKMD2
`
`V
`
`†
`
`†
`
`HOLDA
`XF
`CLKOUT1
`
`† †
`
`DDI
`DDI
`DDC
`
`V
`
`V
`
`V
`
`100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
`
`75
`74
`73
`72
`71
`70
`69
`68
`67
`66
`65
`64
`63
`62
`61
`60
`59
`58
`57
`56
`55
`54
`53
`52
`51
`
`WE
`RD
`VDDA
`A15
`A14
`A13
`A12
`A11
`A10
`CLKMD1
`VSSA
`VSSA
`TDI
`VDDI
`A9
`A8
`A7
`A6
`A5
`A4
`A3
`A2
`A1
`A0
`VSSA
`
`26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
`
`987654321
`
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`
`EMU0
`EMU1/ OFF
`VSSC
`TOUT
`
`† † ††
`
`RS
`READY
`HOLD
`BIO
`TRST
`VSSI
`VSSI
`MP/ MC
`D15
`D14
`D13
`D12
`D11
`D10
`D9
`D8
`VDDD
`
`DDA
`
`V
`
`†
`
`†
`
`††
`
`NMI
`INT4
`INT3
`INT2
`INT1
`SSD
`SSD V
`TCK
`DDD
`TMS
`D0
`D1
`D2
`D3
`D4
`D5
`D6
`D7
`SSD V
`SSD V
`
`V
`
`V
`
`NOTE: NC = No connect (These pins are reserved.)
`† See Table 2 for device-specific pinouts.
`
`Table 2. Device-Specific Pinouts for the PZ Package
`
`’C53S, ’LC53S
`’C52, ’LC52
`’C51, ’LC51
`PIN
`CLKX2
`VSSI
`TCLKX
`5
`6§
`CLKX1
`CLKX
`CLKX
`FSR2
`VSSI
`TFSR / TADD
`7
`CLKR2
`VSSI
`TCLKR
`8
`46§
`DR1
`DR
`DR
`DR2
`VSSI
`TDR
`47
`48§
`FSR1
`FSR
`FSR
`49§
`CLKR1
`CLKR
`CLKR
`CLKIN2
`CLKIN2
`CLKIN2
`83
`91§
`FSX1
`FSX
`FSX
`FSX2
`VSSI
`TFSX / TFRM
`92
`93§
`DX1
`DX
`DX
`DX2
`NC
`TDX
`94
`‡ Pin names beginning with “B” indicate signals on the buffered serial port (BSP).
`§ No functional change
`
`’LC56‡
`BCLKX
`CLKX
`BFSR
`BCLKR
`DR
`BDR
`FSR
`CLKR
`CLKMD3
`FSX
`BFSX
`DX
`BDX
`
`POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
`
`9
`
`

`
`TMS320C5x, TMS320LC5x
`DIGITAL SIGNAL PROCESSORS
`
`
`SPRS030A – APRIL 1995 – REVISED APRIL 1996
`
`
`
`Pin Functions for Devices in the PZ Package
`DESCRIPTION
`PARALLEL INTERFACE BUS
`16-bit external address bus (MSB: A15, LSB: A0)
`16-bit external data bus (MSB: D15, LSB: D0)
`Program, data, and I /O space select outputs, respectively
`Timing strobe for external cycles and external DMA
`Read / write select for external cycles and external DMA
`Read and write strobes, respectively, for external cycles
`External bus ready/ wait-state control input
`Bus request. Arbitrates global memory and external DMA
`SYSTEM INTERFACE / CONTROL SIGNALS
`Reset. Initializes device and sets PC to zero
`Microprocessor/microcomputer mode select. Enables internal ROM
`Puts parallel I/ F bus in high-impedance state after current cycle
`Hold acknowledge. Indicates external bus in hold state
`External flag output. Set /cleared through software
`I /O branch input. Implements conditional branches
`Timer output signal. Indicates output of internal timer
`External interrupt inputs
`Nonmaskable external interrupt
`SERIAL PORT INTERFACE
`Serial receive-data input
`Serial transmit-data output. In high-impedance state when not transmitting
`Serial receive-data clock input
`Serial transmit-data clock. Internal or external source
`Serial receive-frame-synchronization input
`Serial transmit-frame-synchronization signal. Internal or external source
`BUFFERED SERIAL PORT (BSP) (SEE NOTE 1)
`BSP receive data input
`BSP transmit data output; in high-impedance state when not transmitting
`BSP receive-data clock input
`BSP transmit-data clock; internal or external source
`BSP receive frame-synchronization input
`BSP transmit frame-synchronization signal; internal or external source
`
`TYPE
`
`I / O / Z
`I / O / Z
`O / Z
`I / O / Z
`I / O / Z
`O / Z
`I
`I / O / Z
`
`I
`I
`I
`O / Z
`O / Z
`I
`O / Z
`I
`I
`
`I
`O / Z
`I
`I / O / Z
`I
`I / O / Z
`
`I
`O / Z
`I
`I / O / Z
`I
`I / O / Z
`
`SIGNAL
`
`A0 – A15
`D0 – D15
`PS, DS, IS
`STRB
`R / W
`RD, WE
`READY
`BR
`
`RS
`MP/ MC
`HOLD
`HOLDA
`XF
`BIO
`TOUT
`INT1 – INT4
`NMI
`
`DR, DR1, DR2
`DX, DX1, DX2
`CLKR, CLKR1, CLKR2
`CLKX, CLKX1, CLKX2
`FSR, FSR1, FSR2
`FSX, FSX1, FSX2
`
`BDR
`BDX
`BCLKR
`BCLKX
`BFSR
`BFSX
`LEGEND:
`I = Input
`O = Output
`Z = High impedance
`NOTE 1:
`’LC56 devices only
`
`10
`
`POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
`
`

`
`TMS320C5x, TMS320LC5x
`DIGITAL SIGNAL PROCESSORS
`
`
`SPRS030A – APRIL 1995 – REVISED APRIL 1996
`
`Pin Functions for Devices in the PZ Package (Continued)
`TYPE
`DESCRIPTION
`TDM SERIAL PORT INTERFACE
`TDM serial receive-data input
`TDM serial transmit-data output. In high-impedance state when not transmitting
`TDM serial receive-data clock input
`TDM serial transmit-data clock. Internal or external source
`TDM serial receive-frame-synchronization input. In the TDM mode, TFSR / TADD is used to output /
`input the address of the port
`TDM serial transmit-frame-synchronization signal. Internal or external source. In the TDM mode,
`TFSX / TFRM becomes TFRM, the TDM frame sync.
`EMULATION/JTAG INTERFACE
`JTAG-test-port scan data input
`JTAG-test-port scan data output
`JTAG-test-port mode select input
`JTAG-port clock input
`JTAG-port reset (with pull-down resistor). Disables JTAG when low
`Emulation control 0. Reserved for emulation use
`Emulation control 1. Puts outputs in high-impedance state when low
`CLOCK GENERATION AND CONTROL (SEE NOTE 2)
`Oscillator output
`Clock/oscillator input (PLL clock input for ’C56)
`Clock input (PLL clock input for ’C50, ’C51, ’C52, ’C53, ’C53S)
`
`I
`O / Z
`I
`I / O / Z
`
`I / O / Z
`
`I
`
`I
`O / Z
`I
`I
`I
`I / O / Z
`I / O / Z
`
`O
`I
`I
`
`I
`
`O / Z
`
`
`
`SIGNAL
`
`TDR
`TDX
`TCLKR
`TCLKX
`
`TFSR / TADD
`
`TFSX / TFRM
`
`TDI
`TDO
`TMS
`TCK
`TRST
`EMU0
`EMU1 / OFF
`
`X1
`X2 / CLKIN
`CLKIN2
`CLKMD1, CLKMD2,
`CLKMD3
`CLKOUT1
`
`S
`S
`S
`S
`S
`S
`S
`S
`
`VDDA
`VDDD
`VDDC
`VDDI
`VSSA
`VSSD
`VSSC
`VSSI
`LEGEND:
`I = Input
`O = Output
`S = Supply
`Z = High impedance
`NOTE 2: CLKIN2 pin is replaced by CLKMD3 pin on ’LC56 devices.
`
`Clock-mode select inputs
`
`Device system-clock output
`POWER SUPPLY CONNECTIONS
`Supply connection, address-bus output
`Supply connection, data-bus output
`Supply connection, control output
`Supply connection, internal logic
`Supply connection, address-bus output
`Supply connection, data-bus output
`Supply connection, control output
`Supply connection, internal logic
`
`POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
`
`11
`
`

`
`TMS320C5x, TMS320LC5x
`DIGITAL SIGNAL PROCESSORS
`
`
`SPRS030A – APRIL 1995 – REVISED APRIL 1996
`
`TMS320C52, TMS320LC52
`PJ PACKAGE
`( TOP VIEW )
`
`
`
`SSC
`TOUT
`SSI
`CLKX
`SSI
`SSI
`
`VV
`
`V V
`
`RS
`READY
`HOLD
`BIO
`
`RST
`SSI
`
`V T
`
`MP/MC
`D15
`D14
`D13
`D12
`D11
`D10
`D9
`
`EMU1/ OFF
`EMU0
`VDDC
`VDDC
`VDDI
`VDDI
`CLKOUT1
`XF
`HOLDA
`NC
`DX
`VSSI
`FSX
`CLKMD2
`VSSI
`VSSI
`TDO
`VDDC
`X1
`X2 / CLKIN
`CLKIN2
`BR
`STRB
`R/ W
`PS
`IS
`DS
`VSSC
`WE
`RD
`
`99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
`80
`79
`78
`77
`76
`75
`74
`73
`72
`71
`0
`70
`11
`69
`12
`68
`13
`67
`14
`66
`15
`65
`16
`64
`17
`63
`18
`62
`19
`61
`20
`60
`21
`59
`22
`58
`23
`57
`24
`56
`25
`55
`26
`54
`27
`53
`28
`52
`29
`51
`30
`31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
`
`1 2 3 4 5 6 7 8 9 1
`
`100
`
`D8
`VDDD
`VSSD
`VSSD
`D7
`D6
`D5
`D4
`D3
`D2
`D1
`D0
`TMS
`VDDD
`VDDD
`TCK
`VSSD
`VSSD
`INT1
`INT2
`INT3
`INT4
`NMI
`DR
`VSSI
`FSR
`CLKR
`VDDA
`VSSA
`A0
`
`DDA
`A15
`A14
`A13
`A12
`A11
`A10
`CLKMD1
`SSA
`TDI
`DDI
`A9
`A8
`A7
`A6
`A5
`A4
`A3
`A2
`A1
`
`V V
`
`V
`
`NOTE: NC = No connect (These pins are reserved.)
`
`12
`
`POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
`
`

`
`Pin Functions for the TMS320C52, TMS320LC52 in the PJ Package
`TYPE
`DESCRIPTION
`PARALLEL INTERFACE BUS
`16-bit external address bus (MSB: A15, LSB: A0)
`16-bit external data bus (MSB: D15, LSB: D0)
`Program, data, and I /O space select outputs, respectively
`Timing strobe for external cycles and external DMA
`Read / write select for external cycles and external DMA
`Read and write strobes, respectively, for external cycles
`External bus ready/ wait-state control input
`Bus request. Arbitrates global memory and external DMA
`SYSTEM INTERFACE / CONTROL SIGNALS
`Reset. Initializes device and sets PC to zero
`Microprocessor/microcomputer mode select. Enables internal ROM
`Puts parallel I/ F bus in high-impedance state after current cycle
`Hold acknowledge. Indicates external bus in hold state
`External flag output. Set /cleared through software
`I /O branch input. Implements conditional branches
`Timer output signal. Indicates output of internal timer
`External interrupt inputs
`Nonmaskable external interrupt
`SERIAL PORT INTERFACE
`Serial receive-data input
`Serial transmit-data output. In high-impedance state when not transmitting
`Serial receive-data clock input
`Serial transmit-data clock. Internal or external source
`Serial receive-frame-synchronization input
`Serial transmit-frame-synchronization signal. Internal or external source
`EMULATION/JTAG INTERFACE
`JTAG-test-port scan data input
`JTAG-test-port scan data output
`JTAG-test-port mode select input
`JTAG-port clock input
`JTAG-port reset (with pulldown resistor). Disables JTAG when low
`Emulation control 0. Reserved for emulation use
`Emulation control 1. Puts outputs in high-impedance state when low
`
`I / O / Z
`I / O / Z
`O / Z
`I / O / Z
`I / O / Z
`O / Z
`I
`I / O / Z
`
`I
`I
`I
`O / Z
`O / Z
`I
`O / Z
`I
`I
`
`I
`O / Z
`I
`I / O / Z
`I
`I / O / Z
`
`I
`O / Z
`I
`I
`I
`I / O / Z
`I / O / Z
`
`
`
`SIGNAL
`
`A0 – A15
`D0 – D15
`PS, DS, IS
`STRB
`R / W
`RD, WE
`READY
`BR
`
`RS
`MP/ MC
`HOLD
`HOLDA
`XF
`BIO
`TOUT
`INT1 – INT4
`NMI
`
`DR
`DX
`CLKR
`CLKX
`FSR
`FSX
`
`TDI
`TDO
`TMS
`TCK
`TRST
`EMU0
`EMU1 / OFF
`LEGEND:
`I = Input
`O = Output
`Z = High impedance
`
`TMS320C5x, TMS320LC5x
`DIGITAL SIGNAL PROCESSORS
`
`
`SPRS030A – APRIL 1995 – REVISED APRIL 1996
`
`POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
`
`13
`
`

`
`TMS320C5x, TMS320LC5x
`DIGITAL SIGNAL PROCESSORS
`
`
`SPRS030A – APRIL 1995 – REVISED APRIL 1996
`
`
`
`Pin Functions for the TMS320C52, TMS320LC52 in the PJ Package (Continued)
`SIGNAL
`TYPE
`DESCRIPTION
`CLOCK GENERATION AND CONTROL
`Oscillator output
`Clock/oscillator input
`Clock input (PLL clock input for ’C52, ’LC52)
`Clock-mode select inputs
`Device system-clock output
`POWER SUPPLY CONNECTIONS
`Supply connection, address-bus output
`Supply connection, data-bus output
`Supply connection, control output
`Supply connection, internal logic
`Supply connection, address-bus output
`Supply connection, data-bus output
`Supply connection, control output
`Supply connection, internal logic
`
`O
`I
`I
`I
`O / Z
`
`S
`S
`S
`S
`S
`S
`S
`S
`
`X1
`X2 / CLKIN
`CLKIN2
`CLKMD1, CLKMD2
`CLKOUT1
`
`VDDA
`VDDD
`VDDC
`VDDI
`VSSA
`VSSD
`VSSC
`VSSI
`LEGEND:
`I = Input
`O = Output
`S = Supply
`
`14
`
`POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
`
`

`
`
`
`TMS320C5x, TMS320LC5x
`DIGITAL SIGNAL PROCESSORS
`
`
`SPRS030A – APRIL 1995 – REVISED APRIL 1996
`
`TMS320C57S, TMS320LC57S
`PGE PACKAGE
`( TOP VIEW )
`
`VSSC
`VSSC
`HD2
`DS
`IS
`PS
`R/W
`STRB
`NC
`HD3
`BR
`NC
`CLKMD3
`X2/CLKIN
`X1
`VDDC
`NC
`TDO
`VSSI
`VSSI
`HD4
`CLKMD2
`HD5
`FSX
`HD6
`BFSX
`HD7
`DX
`BDX
`HOLDA
`XF
`CLKOUT1
`NC
`DDI
`VDDI
`VDDC
`
`V
`
`109
`110
`111
`112
`113
`114
`115
`116
`117
`118
`119
`120
`121
`122
`123
`124
`125
`126
`127
`128
`129
`130
`131
`132
`133
`134
`135
`136
`137
`138
`139
`140
`141
`142
`143
`144
`
`ADVANCE INFORMATION
`
`108
`107
`106
`105
`104
`103
`102
`101
`100
`99
`98
`97
`96
`95
`94
`93
`92
`91
`90
`89
`88
`87
`86
`85
`84
`83
`82
`81
`80
`79
`78
`77
`76
`75
`74
`73
`
`WE
`HD1
`RD
`HD0
`HRDY
`VDDA
`A15
`NC
`A14
`A13
`A12
`NC
`A11
`A10
`CLKMD1
`VSSA
`VSSA
`TDI
`HDS1
`HDS2
`VDDI
`VDDI
`A9
`A8
`A7
`NC
`A6
`A5
`A4
`A3
`NC
`A2
`A1
`A0
`VSSA
`HCS
`
`1 2 3 4 5 6 7 8 9 1
`
`0
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`26
`27
`28
`29
`30
`31
`32
`33
`34
`35
`36
`
`HINT
`EMU0
`NC
`EMU1/OFF
`VSSC
`VSSC
`TOUT
`BCLKX
`CLKX
`VDDC
`BFSR
`BCLKR
`RS
`READY
`HOLD
`NC
`BIO
`VDDC
`VDDC
`IAQ
`TRST
`VSSI
`VSSI
`MP/MC
`D15
`D14
`D13
`NC
`D12
`D11
`D10
`D9
`NC
`D8
`VDDD
`VDDD
`
`72
`71
`70
`69
`68
`67
`66
`65
`64
`63
`62
`61
`60
`59
`58
`57
`56
`55
`54
`53
`52
`51
`50
`49
`48
`47
`46
`45
`44
`43
`42
`41
`40
`39
`38
`37
`
`NC
`HAS
`DDA
`DDA
`CLKR
`FSR
`BDR
`DR
`NMI
`HBIL
`INT4
`INT3
`INT2
`INT1
`HR/W
`NC
`SSD V
`SSD V
`TCK
`DDD
`DDD
`HCNTL1
`TMS
`HCNTL0
`D0
`D1
`D2
`NC
`D3
`D4
`D5
`NC
`D6
`D7
`SSD V
`SSD V
`
`V
`
`V
`
`V
`
`V
`
`NOTE: NC = No connect (These pins are reserved.)
`
`POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
`
`15
`
`

`
`TMS320C5x, TMS320LC5x
`DIGITAL SIGNAL PROCESSORS
`
`
`SPRS030A – APRIL 1995 – REVISED APRIL 1996
`
`
`
`Pin Functions for the TMS320C57S, TMS320LC57S in the PGE Package
`TYPE
`DESCRIPTION
`PARALLEL INTERFACE BUS
`16-bit external address bus (MSB: A15, LSB: A0)
`16-bit external data bus (MSB: D15, LSB: D0)
`Program, data, and I /O space select outputs, respectively
`Timing strobe for external cycles and external DMA
`Read / write select for external cycles and external DMA
`Read and write strobes, respectively, for external cycles
`External bus ready/ wait-state control input
`Bus request. Arbitrates global memory and external DMA
`SYSTEM INTERFACE / CONTROL SIGNALS
`Reset. Initializes device and sets PC to zero
`Microprocessor/microcomputer mode select. Enables internal ROM
`Puts parallel I/ F bus in high-impedance state after current cycle
`Hold acknowledge. Indicates external bus in hold state
`External flag output. Set /cleared through software
`I /O branch input. Implements conditional branches
`Timer output signal. Indicates output of internal timer
`Instruction acquisition signal
`External interrupt inputs
`Nonmaskable external interrupt
`SERIAL PORT INTERFACE (SPI)
`Serial receive-data input
`Serial transmit-data output. In high-impedance state when not transmitting
`Serial receive-data clock input
`Serial transmit-data clock. Internal or external source
`Serial receive-frame-synchronization input
`Serial transmit-frame-synchronization signal. Internal or external source
`HOST PORT INTERFACE (HPI)
`HPI mode control 1
`HPI mode control 2
`Host interrupt
`HPI data strobe 1
`HPI data strobe 2
`HPI read / write strobe
`HPI address strobe
`HPI ready signal
`HPI chip select
`HPI byte identification input
`HPI data bus
`
`SIGNAL
`
`A0 – A15
`D0 – D15
`PS, DS, IS
`STRB
`R / W
`RD, WE
`READY
`BR
`
`RS
`MP/ MC
`HOLD
`HOLDA
`XF
`BIO
`TOUT
`IAQ
`INT1 – INT4
`NMI
`
`DR
`DX
`CLKR
`CLKX
`FSR
`FSX
`
`HCNTL0
`HCNTL1
`HINT
`HDS1
`HDS2
`HR / W
`HAS
`HRDY
`HCS
`HBIL
`HD0 – HD7
`LEGEND:
`I = Input
`O = Output
`Z = High impedance
`
`I / O / Z
`I / O / Z
`O / Z
`I / O / Z
`I / O / Z
`O / Z
`I
`I / O / Z
`
`I
`I
`I
`O / Z
`O / Z
`I
`O / Z
`O / Z
`I
`I
`
`I
`O / Z
`I
`I / O / Z
`I
`I / O / Z
`
`I
`I
`O / Z
`I
`I
`I
`I
`O / Z
`I
`I
`I / O / Z
`
`16
`
`POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
`
`

`
`
`
`TMS320C5x, TMS320LC5x
`DIGITAL SIGNAL PROCESSORS
`
`
`SPRS030A – APRIL 1995 – REVISED APRIL 1996
`
`BDR
`BDX
`BCLKR
`BCLKX
`BFSR
`BFSX
`
`TDI
`TDO
`TMS
`TCK
`TRST
`EMU0
`EMU1 / OFF
`
`X1
`X2 / CLKIN
`CLKMD1, CLKMD2,
`CLKMD3
`CLKOUT1
`
`VDDA
`VDDD
`VDDC
`VDDI
`VSSA
`VSSD
`VSSC
`VSSI
`LEGEND:
`I = Input
`O = Output
`S = Supply
`Z = High impedance
`
`Pin Functions for the TMS320C57S, TMS320LC57S in the PGE Package (Continued)
`SIGNAL
`TYPE
`DESCRIPTION
`BUFFERED SERIAL PORT
`BSP receive data input
`BSP transmit data output; in high-impedance state when not transmitting
`BSP receive-data clock input
`BSP transmit-data clock; internal or external source
`BSP receive frame-synchronization input
`BSP transmit frame-synchronization signal; internal or external source
`EMULATION/JTAG INTERFACE
`JTAG-test-port scan data input
`JTAG-test-port scan data output
`JTAG-test-port mode select input
`JTAG-port clock input
`JTAG-port reset (with pulldown resistor). Disables JTAG when low
`Emulation control 0. Reserved for emulation use
`Emulation control 1. Puts outputs in high-impedance state when low
`CLOCK GENERATION AND CONTROL
`Oscillator output
`PLL clock input
`
`I
`O / Z
`I
`I / O / Z
`I
`I / O / Z
`
`I
`O / Z
`I
`I
`I
`I / O / Z
`I / O / Z
`
`O
`I
`
`I
`
`O / Z
`
`S
`S
`S
`S
`S
`S
`S
`S
`
`Clock-mode select inputs
`
`Device system-clock output
`POWER SUPPLY CONNECTIONS
`Supply connection, address-bus output
`Supply connection, data-bus output
`Supply connection, control output
`Supply connection, internal logic
`Supply connection, address-bus output
`Supply connection, data-bus output
`Supply connection, control output
`Supply connection, internal logic
`
`POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
`
`17
`
`

`
`TMS320C5x, TMS320LC5x
`DIGITAL SIGNAL PROCESSORS
`
`
`SPRS030A – APRIL 1995 – REVISED APRIL 1996
`
`architecture
`
`
`
`The ’C5x’s advanced Harvard-type architecture maximizes the processing power by maintaining two separate
`memory bus structures, program and data, for full-speed execution. Instructions support data transfers between
`the two spaces. This architecture permits coefficients stored in program memory to be read into the RAM,
`eliminating the need for a separate coefficient ROM. The ’C5x architecture also makes available immediate
`instructions and subroutines based on computed values. Increased throughput on the ’C5x for many DSP
`applications is accomplished using single-cycle multiply/accumulate instructions with a data-move option, up
`to eight auxiliary registers with a dedicated arithmetic unit, a parallel logic unit, and faster I/O necessary for
`data-intensive signal processing. The architectural design emphasizes overall speed, communication, and
`flexibility in processor configuration. Control signals and instructions provide floating-point support,
`block-memory transfers, communication to slower off-chip devices, and multiprocessing implementations
`as shown in the functional block diagram.
`
`Table 3 explains the symbols that are used in the functional block diagram.
`
`Table 3. Symbols Used in Functional Block Diagram
`
`SYMBOL
`ABU
`ACCB
`ACCH
`ACCL
`ALU
`ARAU
`ARB
`ARCR
`ARP
`ARR
`AR0–AR7
`AXR
`BKR
`BKX
`BMAR
`BRCR
`BSP
`C
`CBER1
`CBER2
`CBSR1
`CBSR2
`DARAM
`DBMR
`DP
`DRR
`DXR
`GREG
`HPI
`HPIAH
`HPIAL
`HPICH
`HPICL
`
`DESCRIPTION
`Auto-buffering unit
`Accumulator buffer
`Accumulator high
`Accumulator low
`Arithmetic logic unit
`Auxiliary-register arithmetic unit
`Auxiliary-register pointer buffer
`Auxiliary-register compare register
`Auxiliary-register pointer
`Address-receive register (ABU)
`Auxiliary registers
`Address-transmit register (ABU)
`Receive-buffer-size register (ABU)
`Transmit-buffer-size register (ABU)
`Block-move-address register
`Block-repeat-counter register
`Buffered serial port
`Carry bit
`Circular buffer 1 end address
`Circular buffer 2 end address
`Circular buffer 1 start address
`Circular buffer 2 start address
`Dual-access RAM
`Dynamic bit manipulati